JP4254933B2 - Memory controller and flash memory system - Google Patents

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed and is widely used as a storage medium for information devices (host systems) such as digital cameras.

  As the data handled by such devices has increased in capacity, the storage capacity of flash memory has also increased. In order to smoothly manage the storage area of the flash memory having such a large capacity, a method of managing the storage area by dividing it into a plurality of zones has been used in recent years (see, for example, Patent Document 1).

  More specifically, the storage area of the conventional flash memory having a plurality of zones is partitioned and managed in the form shown in FIG. 11, for example.

  That is, a specific physical block address (PBA) is assigned to each physical block that is a unit of data erasing and includes a predetermined number of pages that are units of physical data reading and writing. Each physical block is classified into one of a plurality of physical zones, and a unique physical zone number (PZN) is assigned to each physical zone. In the example of FIG. 11, a total of 2048 physical blocks are assigned consecutive PBAs # 0 to # 2047, and a total of 512 physical blocks PBA # 0 to # 511 are assigned to the physical zone of PZN # 0. A total of 512 physical blocks of PBA # 512 to # 1023 belong to the physical zone of PZN # 1, a total of 512 physical blocks of PBA # 1024 to # 1535 belong to the physical zone of PZN # 2, and PBA # A total of 512 physical blocks 1536 to # 2047 belong to the physical zone of PZN # 3.

  Each page is assigned a physical page address (PPA). The PPA has a form in which a page number (PN), which is a serial number of the page in the physical block, is added to the lower level of the PBA of the physical block to which the page belongs.

  On the other hand, the address space on the host system side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. The serial number assigned to the logical block is called a logical block number (LBN), and the serial number assigned to the logical zone is called a logical zone number (LZN). Further, the serial number in each logical zone of the logical block included in each logical zone is called a logical zone block number (LZIBN).

  Therefore, when the number of logical blocks included in each logical zone is n, the quotient when LBN is divided by n corresponds to LZN, and the remainder corresponds to LZIBN.

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Further, LZIBN (or LBN) of the logical block corresponding to the data is written in the redundant area of the physical block in which the data is written.

  Note that the correspondence between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table is created in order to manage the correspondence between the two at each time point, and the address conversion table is updated each time the correspondence changes. This address conversion table can be created for each logical zone. In other words, since the correspondence relationship between the logical zone and the physical zone is set in advance, the redundant area of the physical block in the physical zone in which the address translation table is created is referred to and the redundant area of the physical block in which the data is written is referred to. An address conversion table can be created based on the written LZIBN.

  Here, even if the information (hereinafter referred to as logical address information) specifying the logical block to be written in the redundant area is LBN, an address conversion table can be created, but generally LZIBN with a small amount of data is used. Is written in the redundant area as logical address information.

  Conventionally, a plurality of sectors with consecutive LBAs are assigned to each logical zone. In the example of FIG. 11, LBA # 0 to # 15999 sectors are in the LZN # 0 logical zone, LBA # 16000 to # 31999 sectors are in the LZN # 1 logical zone, and LBA # 32000 is in the LZN # 2 logical zone. ... To # 47999, and LBA # 48000 to # 63999 are assigned to the logical zone of LZN # 3, respectively. In this example, one page of the flash memory corresponds to one sector, and each physical block is composed of 32 pages.

The 16000 sectors assigned to each logical zone are managed as logical blocks in units of 32 sectors in which LBAs are continuous in the logical zone. Therefore, in other words, 32 sectors with consecutive LBAs are assigned as logical blocks, and 500 logical blocks with consecutive LBNs (LZIBN # 0 to # 499) are assigned to each logical zone. Here, the number of sectors included in the logical block is appropriately set so that the capacities of the logical block and the physical block match. When configuring a virtual block in which a plurality of physical blocks are virtually combined, the logical block and the virtual block have the same capacity. Since each page of physical blocks stores data in LBA order, it is based on the correspondence between the logical blocks included in each logical zone and the physical blocks included in the physical zone corresponding to the logical zone. The access destination in the flash memory can be specified.
JP 2005-18490 A

  However, when a sector having consecutive LBAs is assigned to each logical zone, if data writing or rewriting concentrates on a sector in which the LBA is in a specific range (for example, a sector in which a file allocation table is stored), the LBA becomes There is a problem that writing concentrates on physical blocks included in the physical zone corresponding to the assigned logical zone, and only the deterioration (bad block formation) of the physical block included in the physical zone is extremely accelerated.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory controller capable of avoiding that data writing is concentrated on a specific area of the flash memory, and a flash memory system including the memory controller. To do.

In order to achieve the above object, the memory controller of the present invention provides:
A memory controller that controls access to a flash memory in response to a command from a host system,
Zone management means for managing a correspondence relationship between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system;
Address management means for managing the correspondence between the logical address in the logical zone and the physical address in the physical zone between the logical zone and the physical zone in a correspondence relationship;
Logical address distribution means for sequentially allocating the sectors to a plurality of logical zones in units of a predetermined number of sectors in which logical addresses are continuous;
Equipped with a,
The predetermined number of sectors is less than the number of sectors included in one logical zone.
It is characterized by that.

  It is desirable that both the predetermined number of sectors and the number of zones of the logical zone to which the sectors allocated in units of the predetermined number of sectors are assigned to be a power of two.

For example, when the integer m is larger than the integer n, the integer n is 0 or more, the predetermined number of sectors is 2 to the nth power, and the number of zones is 2 to the (m−n) th power,
It determines the logical zone allocation destination based counted from the lower side of the given address value from n + 1 th bit to the m-bit counted from the host system.

  A flash memory system according to the present invention includes the memory controller and a flash memory.

  According to the present invention, a memory controller capable of avoiding that data writing is concentrated in a specific area of a flash memory even when writing or rewriting is concentrated in a sector whose LBA is in a specific range, and the memory controller A flash memory system is provided. In other words, when a physical zone in which a plurality of physical blocks in the flash memory are grouped and access is managed in units of each physical zone, writing is not concentrated on the physical blocks included in a specific physical zone. be able to.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  In the flash memory shown in FIG. 2, one page is composed of a user area 25 of 1 sector (512 bytes) and a redundant area 26 of 16 bytes, and one physical block is composed of 32 pages. . There is a flash memory in which one page is composed of a 4-sector user area and a 64-byte redundant area, and one physical block is composed of 64 pages. The user area 25 is an area for storing user data supplied from the host system 4.

  The redundant area 26 is an area for recording additional data such as an error collection code, logical address information, and a block status (flag).

  The error collection code is data for detecting and correcting an error included in the data stored in the user area 25.

  The logical address information is information for specifying a logical block corresponding to the data when valid data is stored in the user area 25 of at least one page included in each physical block of the flash memory 2. It is.

  For a physical block in which valid data is not stored in the user area 25, logical address information is not stored in the redundant area 26 of the block.

  Therefore, by determining whether or not logical address information is stored in the redundant area 26, it is possible to determine whether or not valid data is stored in the physical block including the redundant area 26. . That is, when no logical address information is stored in the redundant area 26, no valid data is stored in the physical block.

  As described above, one physical block includes a plurality of pages. Data cannot be overwritten on these pages. For this reason, even when only the data stored in one page is rewritten, the data stored in all the pages in the physical block including the page must be rewritten.

  That is, in normal data rewriting, data stored in all pages of a physical block including a page to be rewritten is written to another erased physical block. At this time, as for the data stored in the page where the data is not changed, the previously stored data is rewritten as it is.

  In rewriting data as described above, the rewritten data is usually written in a physical block different from the physical block stored previously. For this reason, the correspondence relationship between the logical block address and the physical block address dynamically changes every time data is rewritten in the flash memory 2.

  Therefore, it is necessary to manage the correspondence between the logical block and the physical block, and this correspondence is usually managed by the address conversion table. This address conversion table is created based on logical address information (LZIBN or LBN) stored in the redundant area 26 of the first page of each physical block. Note that such a dynamic address management method is a method generally used in a memory system using a flash memory as described above.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 26.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the controller 3. In contrast, the external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, ROM (Read Only Memory) 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set (sequence command) defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes.

  As shown in FIG. 3, the host interface block 7 includes a command register R1, a sector number register R2, and an LBA register R3, and exchanges data, address information, status information, external commands, etc. with the host system 4. To do. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  A work area 8 shown in FIG. 1 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and includes a plurality of SRAM (Static Random Access Memory) cells. The work area 8 stores, for example, an address conversion table for converting a logical address and a physical address, an empty block search table for searching for an empty block, and the like.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. More specifically, the flash memory interface block 10 includes an address processing unit, a command register, an instruction processing block, and the like. As shown in FIG. 3, the address processing unit includes a physical block address register R11, a page number register R12, a counter R13, and a command register R21.

  The physical block address register R11 stores the physical block address PBA of the physical block to be accessed in the flash memory 2. The physical block address PBA set in the physical block address register R11 is determined based on an address conversion table created in the work area 8. This address conversion table is formed for each pair of corresponding logical zone and physical zone, and stores the correspondence between the logical block number LZIBN in the logical zone and the physical block number PZIBN in the physical zone.

The page number register R12 stores the page number PN of the page to be accessed. The counter R13 counts the remaining amount of pages to be accessed in each physical block.
The command register R21 is set with a sequence command for instructing processing to be executed by the flash memory interface block 10.

  The instruction processing block outputs an internal command, a physical address, and the like for controlling the flash memory 2 in accordance with a sequence command stored in the command register R21.

  The flash memory interface block 10 supplies the internal command, address information, and the like output from the instruction processing block to the flash memory 2, thereby causing the flash memory 2 to execute processing such as reading and writing.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

  Next, a logical address / physical address conversion process realized by the flash memory system 1 having the above configuration will be described.

  In the present embodiment, the controller 3 assigns a specific logic that occurs when the controller 3 concentrates in a specific range of the LBA by sequentially allocating four consecutive sectors designated by the LBA to the 0th to third logical zones. Prevent concentration of access to the zone.

  More specifically, first, as shown in FIG. 4A, the LBA provided by the computer system is 16 bits, and the total is 64000 sectors (in this embodiment, 1 page = 1 sector, so 64000). Page) logical space can be specified.

  Conventionally, the upper 11 bits indicate a logical block number LBN which is a serial number assigned to a logical block, and the lower 5 bits indicate a sector number SN which is a serial number assigned to a sector in the logical block. . Further, the quotient obtained by dividing the logical block number LBN by the number of logical blocks included in the logical zone indicates the logical zone number (LZN: 0 to 3), and the remainder is the serial number assigned to the logical block in the logical zone. The logical zone block number LZIBN (0 to 499) is determined, and access processing to the flash memory 2 is performed. Since data is stored in the order of sector numbers in each page of the physical block, the sector number SN and the page number PN coincide with each other in the case of one-page flash memory.

  On the other hand, in the present embodiment, as shown in FIG. 4A, the 2nd bit of the 4th and 3rd bits from the lower order of the 16-bit LBA indicates the logical zone number (LZN: 0 to 3). It is determined that the upper 9 bits of the 14-bit LBA 'excluding these 2 bits indicate the logical zone block number LZIBN (0-499) and the lower 5 bits indicate the sector number SN (0-31). Then, an access process to the flash memory 2 is performed.

When such a determination is made, as shown in FIG. 4B, the four sectors in which each LBA is continuous are set as one unit and are sequentially assigned to the 0th to third logical zones.
For example, if the LBA is 1110001100110011, it is conventionally determined that the sector of the logical block of LBN # 1817 indicates the sector of SN # 19 by dividing it as “11100011001”; “10011”. Further, the quotient 3 obtained by dividing LBN # 1817 by 500 (the number of logical blocks included in the logical zone) is determined to be LZN, and the remainder 317 is determined to be LZIBN. To access.

  On the other hand, in the present embodiment, “00” of the fourth and third bits from the lower LBA indicates the logical zone of LZN # 0, and the upper 9 of LBA ′ = “111000011001111” excluding these 2 bits. It is determined that the bit “111000110” indicates LZIBN # 454 and the lower 5 bits “01111” indicates SN # 15, and the flash memory 2 is accessed.

  In this case, each logical block is composed of 32 consecutive sectors. For example, as shown in FIG. 5, the logical blocks of LZIBN # 0 in the logical zone of LZN # 0 are LBA = # 0 to # 3, # 16 to # 19, # 32 to # 35, # 48 to # 51, It consists of 32 sectors, # 64 to # 67, # 80 to # 83, # 96 to # 99, and # 112 to # 115. This logical block is associated with any physical block in the physical zone of PZN # 0 of the flash memory 2.

  Similarly, the logical blocks of LZIBN0 in the logical zone of LZN # 1 are LBA = # 4 to # 7, # 20 to # 23, # 36 to # 39, # 52 to # 55, # 68 to # 71, # 84. -# 87, # 100- # 103, and # 116- # 119 are comprised of 32 sectors. This logical block is associated with any physical block in the physical zone of PZN # 1 of the flash memory 2.

  By adopting such a configuration, each sector is sequentially allocated to four logical zones LZN # 0 to 3 in units of four sectors in which LBAs are continuous. By allocating in this way, even when access is concentrated in a specific area of the LBA (for example, an area in which FAT (file allocation table) is written), the access is concentrated in a specific logical zone, that is, a physical zone. There is nothing. That is, if each sector is distributed to each theoretical zone in such a unit that the LBA range where access is concentrated is divided into logical zones, access is distributed to each physical zone.

  Next, the operation of the flash memory system 1 will be described. First, the reading process will be described with reference to FIGS.

  In this read process, the process is executed based on the number of sectors set in the sector number register R2 of the host interface block 7, the leading value of the LBA set in the LBA register R3, and the external command set in the command register R1. .

  This read process is started when an external command that instructs the read process is set in the command register R1.

  First, the microprocessor 6 determines the logical zone number LZN of the access target area (shown in FIG. 4A) based on the head LBA stored in the LBA register R3 and the number of sectors to be accessed set in the sector number register R2. And the logical zone block number LZIBN (obtained from the upper 9 bits of LBA 'as shown in FIG. 4A). Is obtained in units of logical blocks (step S1). That is, when the access target area extends over a plurality of logical blocks, a plurality of sets of LZN and LZIBN are obtained.

  Next, based on the logical zone number LZN and the logical zone block number LZIBN obtained in this way, the physical block address PBA of the physical block for the logical block is obtained (step S2).

  The processing in step S2 will be described in detail. As shown in the flowchart of FIG. 7, first, for each logical block to be accessed, the physical zone block number PZIBN of the physical block corresponding to the logical block is assigned to the logical block. It is obtained by referring to the address conversion table for the logical zone to which (1) belongs.

  Subsequently, the physical block address PBA is obtained by adding the number of blocks corresponding to the physical zone existing before the physical zone PZN (hereinafter referred to as an offset) to the obtained physical zone block number PZIBN. (Step S22). For example, the physical zone block number PZIBN of the physical block to be accessed is #p, the number of physical zones existing before the physical zone to which the physical block to be accessed belongs is m, and the number of physical blocks included in the physical zone is b In this case, the physical block address PBA is obtained by adding an offset (m × b) to PZIBN # p.

  Next, the microprocessor 6 sets the physical block address PBA of the physical block to be read in the physical block address register R11 of the flash memory interface block 10, and the page number register R12 of the page to start reading in the physical block. A page number is set, the number of pages to be read is set in the counter R13, and a sequence command for instructing a data reading process is set in the command register R21. At this time, if the access target area extends over a plurality of logical blocks, the above settings are made in order from the younger LBA.

  Subsequently, the instruction processing block of the flash memory interface block 10 outputs an internal command for controlling the flash memory 2, address information, and the like according to the sequence command stored in the command register R 21, and stores data from the flash memory 2. The read data is stored in the buffer 9 (FIG. 6; step S3). The microprocessor 6 provides the data stored in the buffer 9 to the host system 4 via the host interface block 7 and the external bus 13.

The processing in step S3 will be specifically described. As shown in FIG. 8, the microprocessor 6 sets the physical block address PBA obtained in step S2 in the physical block address register R11 (step S31).
Subsequently, the microprocessor 6 sets the sector number SN corresponding to the lower 5 bits of LBA ′ (14 bits excluding 2 bits indicating the logical zone number LZN from LBA) as the page number PN in the page number register R12 ( Step S32).
Next, the page number (sector number) to be read is set in the counter R13 (step S33).
Subsequently, a sequence command for instructing reading is set in the command register R14 (step S34).

  In response to this sequence command, the flash memory interface block 10 generates a physical page address by adding (concatenating) the page number PN set in the page number register R12 to the PBA set in the physical block address register R11. The data is read from this page and stored in the buffer 9 (step S36).

Subsequently, the counter R13 is decremented (step S37), and it is determined whether or not the count value of the counter R13 has become 0 (step S38).
If it is determined in step S38 that the count value is not 0, that is, data reading has not been completed, the page number PN stored in the page number register R12 is incremented by 1 (step S39), and step S36. Return to. When the count value is 0, the process of step S3 is terminated.

  The above read processing will be described based on a specific example. For example, it is assumed that a read process for reading k sector data is instructed from LBA # i.

  First, based on the LBA, the logical zone number LZN and the logical zone block number LZIBN are obtained (step S1). The access target areas LBA # i to # (i + k-1) span two logical blocks, the logical block to which LBA # i to # j-1 belong and the logical block to which LBA # j to # (i + k-1) belong. If it is, the LZN and LZIBN of the logical block to which these sectors belong are obtained for the areas of the j-i sectors of LBA #i to # j-1. Next, for the area corresponding to (i−j + k) sectors of LBA # j to # (i + k−1), the logical zone number LZN of the logical block to which these sectors belong and the logical block number LZIBN in the logical zone are obtained.

  Next, the physical block address PBA of the physical block corresponding to the logical block is obtained based on the logical zone number LZN thus obtained and the intra-logical zone block number LZIBN (step S2).

  For example, when LBA # i to # j-1 are included in the LZIBN # n logical block of LZN # m and the physical zone of PZN # m corresponds to the logical zone of LZN # m, the LZIBN of LZN # m The PZIBN of the physical block corresponding to the #n logical block is obtained by referring to the address conversion table indicating the correspondence between the logical block belonging to the logical zone of LZN # m and the physical block belonging to the physical zone of PZN # m ( Step S21).

  An offset (m · b) corresponding to PZN # m is added to PZIBN # p of the obtained physical block to obtain a physical block address PBA (= m · b + p) (step S22). Note that b is the number of physical blocks included in the physical zone.

  Also, with respect to the area corresponding to i−j + k sectors of LBA # j to # (i + k−1), the physical block physical corresponding to the logical block to which LBA # j to # (i + k−1) belongs is obtained in the same procedure as described above. The block address PBA is obtained. For the areas of LBA #j to # (i + k−1), PZIBN is obtained by referring to the address conversion table of the logical zone to which the logical block including LBA #j to # (i + k−j) belongs.

  Next, the microprocessor 6 sets the physical block address PBA (= m · b + p) obtained by the above procedure in the physical block address register R11 of the flash memory interface block 10, and the start LBA of the access target area in the page number register R12. Sector number SN # q corresponding to the lower 5 bits of '(LBA # i to LBA # i in the case of LBA # i to # (j-1)') is set, and j-i is set to the counter R13. Further, a sequence command for instructing data reading is set in the command register R21. In response to this, the flash memory interface block 10 reads data from the #q page of the m · b + p physical block, and then updates (increments) #q and reads the data. When the reading of the j-i page data is finished, the reading from the m · b + p block is finished, and the microprocessor 6 is notified that the processing is finished. Further, the reading is executed for the area corresponding to (i−j + k) sectors of LBA # j to # (i + k−1) in the same procedure as described above.

  For the areas of LBA #j to # (i + k−1), the physical block address PBA of the physical block corresponding to the logical block including LBA #j to # (i + k−1) is set in the physical block address register. , The value of the lower 5 bits of LBA ′ of LBA # j is set in the page number register R12, and (i−j + k) is set in the counter R13.

  Next, the writing process to the flash memory 2 will be described. Also in the case of the writing process, when an external command instructing the writing process is set in the command register R1, the writing process is started, and the number of sectors set in the sector number register R2 of the host interface block 7 is set in the LBA register R3. The process is executed based on the set leading value of the LBA.

  Also, the logical zone number LZN to be accessed and the block number LZIBN in the logical zone are obtained in the same procedure as in the above-described reading process, and the address conversion from the logical address to the physical address is basically the same as the above-described reading operation. Are identical. However, since the data cannot be overwritten due to the characteristics of the flash memory, an empty block is detected at the time of writing (or an empty block is generated by appropriately erasing the physical block), and the user area 25 of the empty block is Data sequentially supplied from the host system 4 is written, and the logical block LZIBN corresponding to the data is written in the redundant area 26. In addition, the address conversion table showing the correspondence between LZIBN and PZIBN is updated with the portion where the correspondence has changed.

  As described above, in the flash memory system 1 of the present embodiment, a part of digits when the LBA is expressed in binary number indicates LZN, and a predetermined upper digit excluding this digit indicates LZIBN and remains. It has a structure in which a lower predetermined digit indicates SN. For this reason, when the digit value indicating the LBA LZN changes, the logical zone to which the LBA belongs is changed. As a result, it is avoided that data writing is concentrated in a specific logical zone, and the life of the flash memory 2 is prolonged. Become.

  In the example of FIG. 4, each sector is allocated to a plurality of logical zones with 4 sectors as one unit. However, one unit allocated to a logical zone is arbitrary as long as the number of sectors is less than the total number of sectors included in the logical zone. It can be set with. Note that one unit assigned to the logical zone is determined by the number of bits of bits lower than the bit indicating the LBA LZN.

  For example, as shown in FIG. 9 (a), when the lower 5 bits and the 4th bit of the LBA are 2 bits indicating LZN, the number of bits lower than the LZN bit is 3 bits (from the lower Therefore, each sector is assigned to four logical zones with 8 sectors as one unit. Therefore, as shown in FIG. 9B, the logical zone of the allocation destination changes every 8 sectors, and the 8 consecutive sectors of LBA # 0 to # 7 are transferred to the logical zone of LZN # 0. Eight consecutive sectors are allocated to the same logical zone in order of eight consecutive sectors to the logical zone of LZN # 1.

Further, as shown in FIG. 10A, when the 9th to 13th bits from the lower LBA are used as bits indicating LZN, the number of logical zones to be distributed is 32 (2 ⁵ ). Since the number of bits lower than the bit indicating LZN is 8, as shown in FIG. 10B, each sector is divided into 32 logical zones with 256 sectors (8 logical blocks) as one unit. It is done.

  As described above, when the number of bits indicating one unit allocated to the logical zone is larger than the number of bits corresponding to the number of sectors in the logical block (5 bits in the case of 32 sectors), a plurality of logical blocks are regarded as one unit. Each logical block is distributed to a plurality of logical zones.

  When the number of sectors that are continuously allocated to the same logical zone is smaller than the number of sectors per logical block, the LBA of the sectors in one logical block takes a discontinuous value. . For example, in the case of FIG. 9, the LBAs of 32 sectors in the logical blocks of LZN # 0 and LBN # 0 are # 0 to # 7, # 32 to # 39, # 64 to # 71, # 96 to It takes a partially discontinuous value of # 103.

  In the above description, the number of logical zones and the number of one-unit sectors allocated to the logical zones are both powers of 2. However, even if they are not powers of 2, writing concentrates in a specific area of the flash memory. You can avoid that. However, when the number of logical zones and the unit to be distributed to the logical zones are not a power of 2, LZN and LZIBN cannot be determined by specific bits of LBA.

1 is a block diagram schematically showing a flash memory system according to an embodiment of the present invention. It is a figure which shows roughly the structure of the address space of the flash memory of embodiment of this invention. It is a block diagram which shows the structure of a host interface block and a flash memory interface block. (A) is a figure which shows an example of the data structure of LBA, (b) is a figure which shows the transition of the zone to which the page of a writing destination belongs when data is written in the order of LBA shown to (a). is there. It is a figure which shows the structural example of a logical block, and a corresponding physical block. It is a flowchart for demonstrating a read-out process. It is a flowchart which shows the detail of the physical block address generation process of step S2 shown in FIG. It is a flowchart which shows the detail of the read-out process of step S3 shown in FIG. (A) is a figure which shows another example of the data structure of LBA, (b) shows the transition of the zone to which the page of the writing destination belongs when data is written in the order of LBA shown in (a). FIG. (A) is a figure which shows another example of the data structure of LBA, (b) shows the transition of the zone to which the page of the writing destination belongs when data is written in the order of LBA shown in (a). FIG. It is a figure which shows roughly the structure of the address space of the conventional flash memory.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 15 Internal clock source
25 User area 26 Redundant area

Claims (4)

A memory controller that controls access to a flash memory in response to a command from a host system,
Zone management means for managing a correspondence relationship between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system;
Address management means for managing the correspondence between the logical address in the logical zone and the physical address in the physical zone between the logical zone and the physical zone in a correspondence relationship;
Logical address distribution means for sequentially allocating the sectors to a plurality of logical zones in units of a predetermined number of sectors in which logical addresses are continuous;
Equipped with a,
The predetermined number of sectors is less than the number of sectors included in one logical zone.
A memory controller characterized by that.   The number of the predetermined sectors and the number of zones of the logical zone to which the sectors to be allocated in units of the predetermined sectors are both numerical values given as powers of 2. The memory controller described. When the integer m is larger than the integer n, the integer n is 0 or more, the predetermined number of sectors is 2 to the nth power, and the number of zones is 2 to the (m−n) th power,
You determine the logical zone allocation destination based counted from the lower side of the given address value from n + 1 th bit to the m-bit counted from the host system, according to claim 2, characterized in that Memory controller. The memory controller according to any one of claims 1 to 3, and a flash memory.
A flash memory system characterized by that.

Images