JP4111645B2 - Memory bus access control method after cache miss - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory bus access method of an information processing apparatus that performs instruction fetch, instruction hold, instruction decode, and execution by pipeline processing, and in particular, a branch success side instruction series (hereinafter, target side instruction series) and a branch non-establishment side instruction Provided is an efficient memory bus access method in a dual instruction fetch type information processing system for fetching a series (hereinafter referred to as a sequential instruction series) in parallel.
[0002]
[Prior art]
A microprocessor (or information processing device) that performs instruction fetch, instruction hold, instruction decode, and instruction execution by pipeline processing performs instruction fetch of a continuous instruction sequence in advance, and there is a vacancy in the execution stage in the execution unit. It eliminates the occurrence and realizes high-speed processing. However, when there is a branch instruction in the instruction series, the instruction series to be fetched next differs depending on whether the branch instruction is executed after branching to the target instruction series or the sequential instruction series is continued. As a result, there is a vacancy in the execution cycle of the execution unit temporarily. Here, the target side instruction series is a branch destination instruction series that is executed when a branch is established as a result of executing a branch instruction, and the sequential side instruction series is that the branch is not established as a result of executing the branch instruction. This is a sequence of instructions executed at the time.
[0003]
In order to prevent such a situation, the dual instruction in which the CPU issues an instruction fetch request simultaneously to both instruction sequences of the target side instruction sequence and the sequential side instruction sequence and stores them in two instruction buffers in the CPU, respectively. A fetch type information processing apparatus has been proposed. With this dual instruction fetch type, even if the execution result of a branch instruction is either a branch to the target side or a non-branch, the instruction sequence to be executed next is held in the instruction buffer. Execution stage delays associated with new instruction fetches due to branch direction mispredictions can be minimized.
[0004]
Further, the CPU that is a microprocessor uses a cache memory in order to speed up instruction fetch. Unless the external memory bus is used, the instructions and data cannot be fetched from the external main memory storing the instructions and data. Since such a memory bus access requires a relatively long time (many pipeline cycles), a cache memory for storing instructions and data in the main memory is provided adjacent to the CPU. Normally, instruction fetch from the CPU is requested from the cache memory, and the fetched instruction is stored in the instruction buffer. If a cache miss occurs without being stored in the cache memory, the instruction to be fetched is fetched from the main memory via the memory bus, stored in the instruction buffer, and also stored in the cache memory.
[0005]
[Problems to be solved by the invention]
However, if the memory bus access for fetching instructions from the main memory is frequently performed, traffic in the memory bus increases. Such an increase in memory bus traffic causes a delay in memory bus access. In particular, as a result of acquiring a target or sequential instruction that may not actually be executed from the main memory before executing a branch instruction from the main memory, an instruction required as a result of execution of the branch instruction is read from the main memory. It is not preferable that fetching takes a long time.
[0006]
Accordingly, an object of the present invention is to provide a memory bus access method for an information processing apparatus that reduces excessive memory bus access and enables more efficient instruction fetching.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, one aspect of the present invention provides an instruction fetch unit that fetches both sequential and target instruction sequences of a branch instruction, and a cache in response to a fetch request from the instruction fetch unit. In an information processing apparatus having a cache control unit that fetches an instruction from a memory or a main memory, a memory bus access unit that accesses the main memory, and an instruction buffer that holds the fetched instruction.
A branch prediction unit that performs branch prediction of a branch instruction stored in the instruction buffer prior to execution of the branch instruction, and the cache control unit performs branch prediction when a branch direction of the branch instruction is uncertain. A memory bus access to the main memory is performed in accordance with a branch prediction direction from the unit.
[0008]
In the first aspect of the invention described above, in a more preferred first embodiment, when the branch direction of the branch instruction is uncertain, the cache control unit performs main processing when a cache miss occurs for an instruction in the branch prediction direction of the branch instruction. When a memory miss is performed for an instruction that is not in the branch prediction direction, the instruction fetch is stopped without performing the memory bus access.
[0009]
That is, first, when the branch prediction direction of the branch instruction is on the target side, and a cache miss occurs for the sequential side instruction, the instruction fetch is stopped without performing the memory bus access, and secondly, When the branch prediction direction of the branch instruction is on the sequential side and a cache miss occurs with respect to the instruction on the target side, the instruction fetch is stopped without performing the memory bus access. In other cases, the cache control unit performs an instruction fetch by performing a memory bus access. In other cases, memory bus access is permitted after a cache miss.
[0010]
In the above-described invention, in a more preferred second embodiment, when the branch direction of the branch instruction is uncertain, the cache control unit determines that the branch instruction direction of the branch instruction is on the sequential side and the instruction on the target side When a cache miss occurs, instruction fetch is stopped without performing memory bus access. In other cases, the cache control unit performs an instruction fetch by performing a memory bus access. Therefore, unlike the first embodiment, in the second embodiment, when a branch prediction direction is on the target side and a cache miss occurs with respect to a sequential instruction, instruction fetch is performed by memory bus access. This is because the instruction fetch on the sequential side has a low probability of cache miss, and there is little need to prohibit memory bus access in such a low frequency case.
[0011]
In order to achieve the above object, another aspect of the present invention provides an instruction fetch unit for fetching both a sequential side and a target side instruction sequence of a branch instruction, and a cache in response to a fetch request from the instruction fetch unit. In an information processing apparatus having a cache control unit that fetches an instruction from a memory or a main memory, a memory bus access unit that accesses the main memory, and an instruction buffer that holds the fetched instruction.
A branch prediction unit that performs branch prediction of a branch instruction stored in the instruction buffer prior to execution of the branch instruction, and the cache control unit performs a cache miss when a branch direction of the branch instruction is uncertain. Then, the instruction fetch is stopped without performing the memory bus access, and when the branch instruction is confirmed, the memory bus access is performed when a cache miss occurs with respect to the instruction in the confirmed branch direction.
[0012]
According to the above invention, the memory bus access after the cache miss is performed only for the instruction in the branch direction after the branch is confirmed, and the memory bus traffic can be reduced. In other words, since it is unclear whether or not the branch is used at the stage where the branch is not yet determined, memory bus access after a cache miss is completely prohibited. Further, the instruction on the target side when the branch is unconfirmed is prefetched into the instruction buffer within the range stored in the cache memory.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.
[0014]
FIG. 1 is a system diagram of an information processing apparatus according to an embodiment of the present invention. The information processing apparatus shown in FIG. 1 is a microprocessor, and includes a CPU 40, a cache memory unit 50, and a memory bus access unit 60 in a chip. The left side from the memory bus access unit 60 is outside the chip, and is connected to the main memory 64 via the external memory bus 62.
[0015]
The CPU 40 includes an instruction decoder and an instruction execution unit 49 that decodes an instruction and executes the instruction. The CPU 40 shown in FIG. 1 includes instruction fetch units 410 and 411 of a dual instruction fetch system that fetches both the instructions on the sequence side and the target side of the branch instruction at the same time. Further, the CPU 40 has instruction buffers 470 and 471 for storing fetched instructions on the sequence side and the target side. Of the instructions in the instruction buffer, the instruction on the side selected by the selector 48 is sent to the instruction decoder 49. Supplied. Selection of the selector 48 is performed according to branch prediction signals S430 and S431 of a branch instruction to be described later.
[0016]
The instruction decoded by the instruction decoder is executed by the instruction execution unit 49, and the execution result is written in a predetermined register (not shown). The instruction decoder and instruction execution unit 49 supplies the branch destination address information S12 of the branch instruction to the branch side address generation unit 46. The branch side address generation unit 46 generates a branch destination address A10 according to the branch destination address information S12 and supplies it to the branch destination address buffer 45. The branch destination address buffer 45 holds the branch destination address, which is the address of the supplied instruction on the target side, for subsequent instruction fetch. Further, the continuous side address buffer 44 generates and holds the address of the sequential instruction by incrementing it.
[0017]
The instruction fetch units 410 and 411 have address selection units 420 and 421, respectively. The address selection units 420 and 421 generate the sequential address A1 from the continuous address buffer 44, the branch destination address A2 from the branch address buffer 45, and the instruction execution unit 49 as a result of instruction execution. Each address A3 is supplied, and an address selected from the addresses A3 is supplied to the cache memory unit 50 together with the instruction fetch request S20. In response to the branch decision signal S10 supplied from the instruction execution unit 49, one of the instruction fetch units 410 and 411 becomes a sequential instruction fetch unit, and the other becomes a target instruction fetch unit. Further, according to the branch confirmation signal S10, a distinction between whether the instruction fetch is a prefetch at a branch unconfirmed stage or a fetch after the branch is confirmed is attached to the instruction fetch request S20 and given to the cache memory unit.
[0018]
The cache memory unit 50 includes a cache memory 52 and cache control units 54 and 56. The cache control units 54 and 56 fetch an instruction from the cache memory 52 or the main memory 64 in response to the fetch request S20 from the instruction fetch units 410 and 411. Accordingly, the cache memory unit 50 has a two-port format that can simultaneously accept an instruction fetch request on the sequential side and the target side. The cache control units 54 and 56 fetch an instruction by giving an address AD to the cache memory 52, and a hit / miss signal CHM indicating whether a cache hit or a cache miss has occurred for the instruction fetch is a cache memory. 52 is returned to the respective cache control units 54 and 56.
[0019]
When each cache control unit 54, 56 fetches an instruction to the cache memory in response to the fetch request S20 and results in a cache hit, the fetched instruction is supplied to and stored in the corresponding instruction buffer 470, 471. When a cache miss occurs, the cache control units 54 and 56 make a memory bus access request to the memory bus access unit 60 to fetch an instruction from the main memory 64 according to an algorithm described later. However, in the present embodiment, this memory bus access is partially restricted at the stage where the branch has not yet been determined.
[0020]
The memory bus access unit 60 is connected to the main memory 64 via the external memory bus 62, controls the memory bus 62, and responds to fetch requests to the main memory 64 from the cache control units 54 and 56, Performs memory bus access. Instructions fetched from the main memory 64 are respectively supplied to the corresponding cache control units 54 and 56, stored in the corresponding instruction buffers 470 and 471, and also stored in the cache memory 52.
[0021]
In response to the fetch request signal S20, the cache control units 54 and 56 have fetched an instruction from the cache memory 52, accessed the memory bus, fetched an instruction from the main memory 64, or stopped the instruction fetch. The completion notification signal S22 is supplied to the corresponding address selectors 420 and 421.
[0022]
The information processing apparatus in FIG. 1 includes branch prediction units 430 and 431 in the CPU 40. The branch prediction units 430 and 431 perform branch prediction of the fetched branch instruction according to the branch prediction bits S30 and S32 included in the instruction code stored in the instruction buffer, and appropriately select the branch prediction information S430 and S431 as an address selection unit. 420 and 421. The address selectors 420 and 421 add the branch prediction information, the fetch destination address, and information on whether or not the branch is confirmed to the fetch request signal S20, and supply it to the cache controllers 54 and 56.
[0023]
The information processing apparatus shown in FIG. 1 is a dual instruction fetch method, fetches both a sequential instruction string and a target instruction string of an instruction string and stores them in instruction buffers 470 and 471. This instruction fetch is performed at a stage where the branch instruction is not yet confirmed before the branch instruction is executed by the instruction execution unit 49 and the branch is confirmed, and the prefetched sequential side and target side instruction sequences are stored in the instruction buffers 470 and 471. Stored in Therefore, as a result of execution of the branch instruction, regardless of which direction the branch is determined, the instruction decoding and execution stage after the branch instruction is determined can be performed without disturbing the pipeline cycle.
[0024]
Further, the information processing apparatus shown in FIG. 1 performs branch prediction of the instructions fetched by the branch prediction units 430 and 431, and executes one instruction of the instruction buffers 470 and 471 according to the branch prediction results S430 and S431. Decode. By decoding the instruction according to the branch prediction before the branch instruction is determined, it is possible to reduce disturbance in the pipeline processing cycle at the time of branch determination.
[0025]
In general, the cache control units 54 and 56 fetch an instruction from the cache memory 52 in response to a fetch request, and when a cache hit occurs, the fetched instruction is stored in the instruction buffer and a cache miss occurs. Issues a memory bus access request to the memory bus access unit 60 and fetches an instruction from the main memory 64.
[0026]
However, the data bus in the cache memory unit 50 is high-speed, whereas the external memory bus 62 has a low operating frequency and a narrow bus width. Therefore, if the memory bus access is frequently performed, the traffic to the memory bus 62 increases, and the memory bus access itself takes time. Therefore, if the frequency of access to the external memory bus 62 is increased, there is a problem that it takes time to access the memory bus when, for example, it becomes necessary to fetch an instruction that is suddenly needed from the main memory.
[0027]
As will be described later, the cache control units 54 and 56 according to the present embodiment cancel the instruction fetch without performing a memory bus access after a cache miss when necessary or when a branch is not confirmed. To do.
[0028]
In the first embodiment, for instructions that are not in the branch prediction direction, the instruction fetch is stopped without performing the memory bus access after the cache miss. In the case of an instruction that is not in the branch prediction direction, there is a high possibility that the instruction fetch will be wasted when the branch instruction is determined thereafter. Therefore, it is more efficient not to perform memory bus access to such an instruction. However, for the instruction in the branch prediction direction, the memory bus is accessed after a cache miss.
[0029]
In the second embodiment, when the branch prediction direction is the sequential side and a cache miss occurs with respect to the instruction on the target side, the instruction fetch is stopped without performing the memory bus access. However, if the branch prediction direction is the target side and a cache miss occurs for an instruction on the sequential side, even if the instruction is on the side different from the branch prediction direction, the memory bus is accessed and the instruction fetch is completed Let The reason for this is that when a memory bus is accessed due to a cache miss, instructions at addresses consecutive to that instruction are fetched to the cache memory 52 at a time, so that a sequential instruction sequence may cause a cache miss. Is low. Therefore, even if such infrequent memory bus access is permitted, the traffic on the memory bus 62 does not increase so much. In the case of the second embodiment, access to the memory bus is permitted after a cache miss for an instruction in the branch prediction direction.
[0030]
As a third embodiment, while the branch instruction is not confirmed, only the cache hit instruction is stored in the instruction buffer, and when the cache miss occurs, the instruction fetch is stopped without performing the memory bus access and the branch instruction is confirmed. In step 1, a memory bus access is performed for a cache missed instruction. Even in this case, as long as the previously fetched instruction is recorded in the cache memory, the instructions on both sides can be prefetched and stored in the instruction buffer by the dual instruction fetch method. Further, since the memory bus access is performed only for the instructions in the branch direction after the branch is determined to be used reliably, the access frequency to the memory bus can be reduced.
[0031]
FIG. 2 is a block diagram of the cache control unit. As described above, the fetch request S20B is supplied from the CPU 40 together with the fetch address S20A and the branch prediction information S20C. The address S20A is supplied to the cache memory 52 and held by the bus access address holding unit 72. The fetch request signal S20A and the branch prediction information S20C are supplied to the bus access necessity determination unit 70.
[0032]
The bus access necessity determination unit 70 determines the memory bus according to the cache hit determination result based on the cache hit / miss signal CHM from the cache memory 52, the branch prediction information S20C, the status of the current sequential side or the target side, and the like. Determine whether to request access. Further, the bus access necessity determination unit 70 supplies the determination result to the bus access control unit 74 as a bus access request signal S71 and supplies the bus access unnecessary signal S70 to the completion notification determination unit 78.
[0033]
If it is determined in the above determination that the memory bus access is necessary, the bus access control unit 74 sends a bus access request signal S76 to the memory bus access unit 60 in response to the bus access request signal S71, and also accesses the bus. The control signal S75 is output to the address holding unit 72 to output the held fetch address. If it is determined in the above determination that the memory bus access is unnecessary, the bus access control unit 74 does not perform the memory bus access. This determination is in accordance with the algorithm of the first, second, and third embodiments.
[0034]
When data is returned from the main memory 64 in response to the memory bus access, the bus access control unit 74 receives the data valid signal S77 from the memory bus access unit 60, and in response thereto, a bus access completion signal S74 is supplied to the completion notification determination unit 78. The completion notification determining unit 78 notifies completion according to the bus access completion signal S74 or the bus access unnecessary signal S70, whether the instruction is fetched from the cache memory 52, whether the instruction fetch is stopped, or fetched from the main memory by the memory bus access. The signal S22 is sent to the instruction fetch unit of the CPU.
[0035]
The instruction fetched from the main memory is stored in the cache memory and also in the instruction buffer via the cache control unit.
[0036]
The algorithm that does not perform memory bus access in the first, second, and third embodiments will be described below.
[0037]
FIG. 3 is a chart showing an instruction fetch operation in the first embodiment. The instruction fetch operation will be described with reference to the chart. In the first embodiment,
(1) If the branch direction of the branch instruction is not fixed,
(1-1) When the branch prediction direction by the branch prediction unit is the target side, first, when the instruction fetch on the sequential side causes an instruction cache miss, the instruction fetch is stopped without accessing the memory bus, Do not access the memory bus. Second, in the instruction fetch on the target side, when an instruction cache miss occurs, the memory bus is accessed to complete the instruction fetch.
(1-2) If the branch prediction direction in the branch instruction execution is the sequential side, first, the instruction fetch on the target side stops the instruction fetch without accessing the memory bus if an instruction cache miss occurs Do not access the memory bus. Second, in the sequential instruction fetch, when an instruction cache miss occurs, the memory bus is accessed to complete the instruction fetch.
(2) If the branch direction of the branch instruction is fixed,
Instruction fetch is performed only on the side where the branch direction is determined (sequential side or target side). In that case, if a cache miss occurs, the memory bus is accessed to complete the instruction fetch.
[0038]
As described above, in the first embodiment, while the branch direction is uncertain, only the instruction fetch in the branch prediction direction is permitted to perform a memory bus access after a cache miss, and the instruction fetch is not in the branch prediction direction. The memory bus access after a cache miss is prohibited, and the memory bus access for instruction fetch that is likely to be wasted is not performed. In any case, when a cache hit occurs, the instruction fetched by the cache hit is stored in the instruction buffer, and the instruction fetch is completed.
[0039]
Further, the address selection units 420 and 421 in the instruction fetch units 410 and 411 newly issue an instruction fetch request for an instruction for which instruction fetch has not been completed and whose branch is determined by the branch determination signal S10. put out. If a cache miss occurs at this time, access the memory bus.
Fetch the necessary instructions. At that time, the instruction sequence continuous with the instruction is also stored in the cache memory 52.
[0040]
FIG. 4 is a chart showing an instruction fetch operation in the second embodiment which is an improvement of the first embodiment. The instruction fetch operation will be described with reference to the chart. In the second embodiment,
(1) If the branch direction of the branch instruction is not fixed,
(1-1) When the branch prediction direction of the branch prediction unit is the target side, first, when an instruction cache miss occurs in the sequential instruction fetch, the memory bus is accessed and the instruction fetch is completed. Second, in the instruction fetch on the target side, when an instruction cache miss occurs, the memory bus is accessed to complete the instruction fetch.
(1-2) If the branch prediction direction in the branch instruction execution is the sequential side, first, the instruction fetch on the target side stops the instruction fetch without accessing the memory bus if an instruction cache miss occurs Do not access the memory bus. Second, in the sequential instruction fetch, when an instruction cache miss occurs, the memory bus is accessed to complete the instruction fetch.
(2) If the branch direction of the branch instruction is fixed,
Instruction fetch is performed only on the side where the branch direction is determined (sequential side or target side). In that case, if a cache miss occurs, the memory bus is accessed to complete the instruction fetch.
[0041]
The second embodiment differs from the first embodiment in that when the branch prediction direction is the target side and a cache miss occurs with respect to the instruction fetch on the sequential side, the instruction on the side different from the branch prediction direction However, the instruction is to complete the instruction fetch by accessing the memory bus. Such a case is very unlikely and therefore is less frequent, so allowing memory bus access does not increase memory bus traffic.
[0042]
FIG. 5 is a table showing an instruction fetch operation in the third embodiment. The instruction fetch operation will be described with reference to the chart. In the third embodiment,
(1) If the branch direction of the branch instruction is not fixed,
(1-1) When the branch prediction direction of the branch prediction unit is the target side, first, when the instruction fetch on the sequential side causes an instruction cache miss, the instruction fetch is stopped without accessing the memory bus, Do not access the memory bus. Second, in the case of instruction fetch on the target side, if an instruction cache miss occurs, the instruction fetch is stopped and the memory bus is not accessed without accessing the memory bus.
(1-2) When the branch prediction direction of the branch prediction unit is the sequential side, first, when the instruction fetch on the target side causes an instruction cache miss, the instruction fetch is stopped without accessing the memory bus, Do not access the memory bus. Secondly, the instruction fetch on the sequential side also stops the instruction fetch and does not access the memory bus without accessing the memory bus if an instruction cache miss occurs.
(2) If the branch direction is fixed,
Instruction fetch is performed only on the side where the branch direction is determined (sequential side or target side). In this case, even if a cache miss occurs, the memory bus is accessed and an instruction is fetched from the main memory to complete the instruction fetch.
[0043]
The third embodiment prohibits any memory bus access while the branch instruction is not executed and the branch is uncertain, and permits the memory bus access only for the instruction whose branch direction is determined. If the branch has not been determined, instruction fetch by memory bus access may be wasted, so that memory bus access is prohibited to reduce memory bus traffic. Since the branch-fixed instruction is stored in advance in the cache memory, the cache miss itself does not occur with a very high probability. Therefore, even if only prefetching is performed by fetching instructions from the cache memory and both the sequence side and target side instruction sequences are stored in the instruction decoder, the instructions can be executed without significantly disturbing the entire pipeline operation. Is possible.
[0044]
Finally, as a fourth embodiment, a method for reducing memory bus accesses other than those described above will be described. FIG. 6 is a table showing instruction fetch operations in the fourth embodiment. The instruction fetch operation will be described with reference to the chart. In the fourth embodiment, (1) when the branch direction of the branch instruction is not fixed
(1-1) When the branch prediction direction in the branch prediction unit is the target side, the instruction fetch on the sequential side stops the instruction fetch without accessing the memory bus if an instruction cache miss occurs, and accesses the memory bus Do not do. On the other hand, in the instruction fetch on the target side, when an instruction cache miss occurs, the memory bus is accessed to complete the instruction fetch.
(1-2) When the branch prediction direction in the branch prediction unit is the sequential side, first, the instruction fetch on the target side accesses the memory bus when an instruction cache miss occurs and completes the instruction fetch. Second, when an instruction cache miss occurs in the sequential side instruction, the memory bus is accessed to complete the instruction fetch.
(2) When the branch direction of the branch instruction is fixed
Instruction fetch is performed only on the side where the branch direction is determined (sequential side or target side). In this case, the instruction fetch that performed the memory bus access to the cache miss is completed.
[0045]
In the case of the fourth embodiment, when the branch instruction has not been determined, at least the branch prediction direction is the target side, and the memory bus access is not performed if a cache miss occurs in the instruction fetch on the sequential side. As a result, the number of memory bus accesses can be reduced accordingly.
[0046]
Similar to the fourth embodiment, even if the memory bus access is prohibited for an arbitrary instruction fetch when the branch is not yet determined, the number of memory bus accesses can be reduced by that amount. However, there are cases where instruction prefetching in the direction predicted to branch cannot be performed. It is desirable to set in consideration of the balance between memory bus access prohibition and instruction prefetch failure.
[0047]
Of the above four embodiments, the operation of the second embodiment that balances the prohibition of memory bus access and the failure of instruction prefetch to some extent will be described with reference to FIG. As a premise, it is assumed that the instruction fetch on the sequential side is performed on the port 0 side, and the instruction fetch on the target side is performed on the port 1 side.
(1) When the branch direction of the branch instruction is not fixed,
(1-1) When the branch prediction direction in the branch prediction units 430 and 431 is the target side, the instruction fetch unit 410 (Port-0) of the CPU 40 sends the instruction fetch request S20 to the cache memory unit 50 for sequential instruction fetch. And the instruction fetch request is passed to the instruction cache memory 52. In addition to the fetch address, this instruction fetch request is also attached with information indicating whether or not a branch has been determined, branch prediction information, and the like.
[0048]
If an instruction cache miss occurs in the instruction cache memory 52, the signal CHM is returned to the cache control unit 54, and the cache control unit 54 issues a memory bus access request to the memory bus access unit 60. In response to this, the memory bus access unit 60 accesses the memory bus 62, reads the instruction from the main memory 64, passes it to the cache control unit 54, writes it to the memory cache 52, and the instruction buffer (0) in the CPU 40. Store at 470 to complete the instruction fetch. An instruction fetch completion signal S22 is returned to the instruction fetch unit 410.
[0049]
Since the frequency of cache misses for sequential instruction fetches is not so high, even if memory bus access is permitted in this case, the efficiency of the entire memory bus is not reduced much.
[0050]
In the instruction fetch on the target side, an instruction fetch request is supplied from the instruction fetch unit 411 in the CPU 40 to the cache control unit 56 (Port-1), and the instruction fetch request is passed to the instruction cache memory 52.
[0051]
When an instruction cache miss occurs in the instruction cache memory 52, the cache control unit 56 (Port-1) issues a memory bus access request to the memory bus access unit 60, and the memory bus access unit 60 accesses the memory bus 62, The instruction is read from the main memory 64, transferred to the cache control unit 56 (Port-1), written to the cache memory 52, and stored in the instruction buffer (1) 471 of the CPU 40, thereby completing the instruction fetch. Then, an instruction fetch completion signal is returned to the instruction fetch unit 411.
[0052]
In this case, since the instruction in the branch prediction direction having a high use probability has a cache miss, allowing the memory bus access and completing the prefetch prevents the pipeline operation after the branch from being disturbed. .
(1-2) If the branch prediction direction in the branch prediction unit is the sequential side, the instruction fetch on the target side is sent from the instruction fetch unit 411 in the CPU 40 to the cache control unit 56 (Port-1). The instruction fetch request is passed to the instruction cache memory.
[0053]
Even if an instruction cache miss occurs in the instruction cache memory 52, the cache control unit (Port-1) 56 does not issue a memory bus access request to the memory bus access unit 60. As a result, the memory bus access unit 60 does not access the memory bus. Then, the cache control unit 56 stops the instruction fetch and returns a result signal indicating that the instruction fetch is canceled to the address selection unit 421.
[0054]
On the other hand, in the instruction fetch on the sequential side, an instruction fetch request is issued from the instruction fetch unit 410 in the CPU 40 to the cache control unit (Port-0) 54, and the instruction fetch request is passed to the instruction cache memory 52.
[0055]
If an instruction cache miss occurs in the instruction cache memory 52, the cache control unit 54 issues a memory bus access request to the memory bus access unit 60, and the memory bus access unit 60 accesses the memory bus 62 to store the instruction in the main memory 64. Is returned to the cache control unit 54. The cache control unit 54 writes the instruction to the cache memory 52 and stores it in the instruction buffer (0) 470 of the CPU, thereby completing the instruction fetch.
(2) When the branch direction is fixed by executing a branch instruction
The instruction fetch units 420 and 421 fetch instructions only on the side (sequential side or target side) on which the branch direction is determined by execution of the branch instruction. At that time, if the branch decision direction is the sequential side, the instruction fetch unit 420 requests the memory bus access unit 60 for bus access via the cache control unit (Port-0) 54. The memory bus access unit 60 reads the fetch requested instruction from the main memory 64, stores the instruction in the instruction buffer (0) 470 and the cache memory 52 via the cache control unit 54, and completes the instruction fetch.
[0056]
When the branch decision direction is the target side, the instruction fetch unit 411 requests the memory bus access unit 60 for bus access via the cache control unit (Port-1) 56. The memory bus access unit 60 reads the instruction requested to be fetched from the main memory 64, stores the instruction in the instruction buffer (1) 471 via the cache control unit 56, and completes the instruction fetch. Note that when the branch confirmation direction becomes the target side, the target side is changed to the sequential side, and the sequential side is changed to the target side.
[0057]
FIG. 7 is a chart showing a specific pipeline operation when memory bus access is restricted by the first or second embodiment. This example shows the pipeline operation by taking the sequential instruction sequences 01 to 09 and the target instruction sequences 51 to 54 corresponding to the branch instruction 03 shown below the table of FIG. In this example, the branch prediction for the branch instruction 03 is a case where a branch is not taken, that is, a sequential direction is predicted.
[0058]
Pipeline operations consist of the following stages.
P: Instruction fetch request stage: The CPU issues an instruction fetch request to the cache control unit. At this stage, an instruction fetch request is made with a distinction between prefetch with branch unconfirmed and fetch after branch confirmation.
T: Fetch stage: A hit miss determination is made in the cache memory and preparations for fetching an instruction are made.
C: Instruction buffer stage: An instruction is fetched into the instruction buffer.
D: Decode stage: The instruction decoder decodes the instruction and generates a control signal.
E: Execution stage: An instruction is executed in response to the control signal of the decoding result.
W: Write stage: The result of executing the instruction is written to the register.
M: Cache miss: A cache miss occurred.
B: Bus access holding stage: An address is held in the bus access address holding unit for accessing the memory bus.
R: Bus access request stage: A read request is issued to the memory bus access unit. Assume that 18 cycles are required until an instruction is read by bus access.
[0059]
Referring back to FIG. 7, the instruction 01 can fetch an instruction from the cache memory by the instruction fetch request stage P in cycle 1 and the fetch stage T in cycle 2 and the instruction is fetched into the instruction buffer in cycle 3 (stage D). . Then, the instruction is executed in three cycles of cycles 5, 6, and 7 (stage E). After execution, the instruction execution result is written into various registers (stage W).
[0060]
The instruction 02 is also taken into the instruction buffer through stages P, T, and C. Then, in the next cycle 8 when the execution stage E of the instruction 01 is completed, the instruction 02 waiting in the decode stage D is executed (stage E), and the execution result is written to the register (stage W).
[0061]
The instruction 03 is determined to be a branch instruction by the branch prediction unit at the time of the instruction buffer stage C, and the branch direction is predicted to be the sequential side. Accordingly, the instruction prefetch is also started from the instruction sequence 51, 52, 53 on the target side from the cycle 6.
[0062]
For the instructions 03 to 07, each execution stage E is executed without cache hitting and disturbing the pipeline cycle. Assume that instructions 08 to 10 cause a cache miss (stage M). Further, it is assumed that the instructions 51 to 53 on the target side also cause a cache miss (stage M).
[0063]
The instruction 08 is requested as an instruction prefetch in which the branch of the branch instruction 03 is unconfirmed at the time of cycle 8 and the branch is unconfirmed (stage P). Thus, although a cache miss occurs in cycle 10, in the first or second embodiment, if a sequential instruction causes a cache miss when the branch prediction is on the sequential side, the memory bus access is permitted. Therefore, the bus access holding stage B is entered in cycle 11 and the bus access request stage R is entered from cycle 12. Since it is assumed that the bus access request stage R requires 18 cycles, the instruction fetched in the cycle 30 is stored in the instruction buffer and becomes the instruction buffer stage C.
[0064]
As the instruction 08 accesses the memory bus, subsequent instructions are also fetched from the main memory and stored in the cache memory, so that the instruction buffer stage C after the instruction 09 follows the stage C of the instruction 08. .
[0065]
On the other hand, the instruction 51 causes a cache miss at the time of the cycle 8, but since the branch prediction direction is the sequential side, the memory bus access to the instruction 51 on the target side is prohibited. Similarly, instructions 52 and 53 are also prohibited from accessing the memory bus. Therefore, in the cycle 12 in which the instruction 08 requests the memory bus access, the memory bus is in an empty state and the memory bus can be accessed immediately, and the instruction 08 is executed in the cycle 32 (stage E).
[0066]
Since the instructions 11 and 12 reach the instruction fetch stage P after the branch is confirmed after the branch is confirmed, the memory bus access is executed even if a cache miss occurs. However, in the example of FIG. 7, since the instructions 11 and 12 are already stored in the cache memory by the memory bus access of the instruction 08, no cache miss has occurred.
[0067]
The example of FIG. 7 operates similarly in both the first embodiment and the second embodiment. That is, even if a cache miss occurs for the prefetch of the instruction 08 when the branch is not yet confirmed, the memory bus access is permitted for the instruction 08 on the branch prediction direction side.
[0068]
In the case of the third embodiment, the memory bus access after a cache miss is prohibited with respect to the prefetch of the instruction 08 when the branch is not confirmed. In this case, in response to the instruction fetch from the instruction fetch unit again after the branch is confirmed, the instruction is fetched by a memory bus access after a cache miss. In this case, the memory bus access is performed at high speed.
[0069]
FIG. 8 is a chart showing a specific pipeline operation when the memory bus access of the conventional example is not restricted. This example also shows the pipeline operation for the same instruction sequence as in FIG.
[0070]
In this example, instruction 51 is not in the branch prediction direction, but memory bus access is permitted. Therefore, the bus access request stage R starts from the cycle 10. Since this stage R requires 18 cycles, even if the instruction 08 causes a cache miss (stage M) in cycle 10, the memory bus is busy, and the memory bus access R is kept waiting until cycle 28. . As a result, the execution stage E of the instruction 08 is delayed until the cycle 48.
[0071]
As described above, compared to the conventional example, in this embodiment, the memory bus access at the stage where the branch is not yet determined is limited. Therefore, the memory bus access can be efficiently performed for the highly usable instruction. Pipeline cycle disturbance can be minimized.
[0072]
As described above, the protection scope of the present invention is not limited to the above-described embodiment, but extends to the invention described in the claims and equivalents thereof.
[0073]
【The invention's effect】
As described above, according to the present invention, the access to the main memory at the time of a cache miss is appropriately restricted with respect to the instruction fetch when the branch is unconfirmed, so the main memory for the instruction in the branch prediction direction and the instruction after the branch is confirmed Can be accessed more efficiently.
[Brief description of the drawings]
FIG. 1 is a system diagram of an information processing apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram of a cache control unit.
FIG. 3 is a chart showing an instruction fetch operation in the first embodiment.
FIG. 4 is a chart showing an instruction fetch operation in the second embodiment.
FIG. 5 is a chart showing an instruction fetch operation in the third embodiment;
FIG. 6 is a chart showing an instruction fetch operation in the fourth embodiment.
FIG. 7 is a chart showing a specific pipeline operation when memory bus access is restricted according to the first or second embodiment;
FIG. 8 is a chart showing a specific pipeline operation in the case of a conventional example.
[Explanation of symbols]
40 CPU
410,411 Instruction fetch section
430,431 Branch prediction unit
50 cache memory unit
52 cache memory
54, 56 Cache control unit
60 Memory bus access section
62 Memory bus
64 Main memory

Claims (5)

An instruction fetch unit that fetches both sequential and target instruction sequences of a branch instruction; a cache control unit that fetches an instruction from a cache memory or a main memory in response to a fetch request from the instruction fetch unit; and the main In an information processing apparatus having a memory bus access unit for accessing a memory and an instruction buffer for holding the fetched instruction,
A branch prediction unit that performs branch prediction of a branch instruction stored in the instruction buffer prior to execution of the branch instruction;
When the branch direction of the branch instruction is uncertain, the cache control unit fetches an instruction from the cache memory, and when a cache miss occurs for an instruction in the branch prediction direction of the branch instruction, An information processing apparatus that performs an instruction fetch by performing a memory bus access, and stops an instruction fetch without performing a memory bus access when a cache miss occurs for an instruction that is not in a branch prediction direction. An instruction fetch unit that fetches both sequential and target instruction sequences of a branch instruction; a cache control unit that fetches an instruction from a cache memory or a main memory in response to a fetch request from the instruction fetch unit; and the main In an information processing apparatus having a memory bus access unit for accessing a memory and an instruction buffer for holding the fetched instruction,
A branch prediction unit that performs branch prediction of a branch instruction stored in the instruction buffer prior to execution of the branch instruction;
When the branch direction of the branch instruction is uncertain, the cache control unit fetches an instruction from the cache memory, and when the branch instruction prediction direction of the branch instruction is on the sequential side, a cache miss is performed on the instruction on the target side. An information processing apparatus characterized in that when it happens, instruction fetch is stopped without performing memory bus access. In claim 1 or 2,
The cache control unit, when the branch instruction is confirmed, performs a memory bus access of a cache missed instruction for the instruction in the confirmed branch direction. 4. The information processing apparatus according to claim 3, wherein when the branch direction of the branch instruction is uncertain, the cache hit instruction is prefetched and stored in the instruction buffer. 4. The information processing apparatus according to claim 3 , wherein the instruction on the sequential side or the target side of the instruction in the instruction buffer is selected and decoded according to the branch direction of the branch prediction unit.

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