JP4100144B2 - Clock regeneration apparatus and clock regeneration method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock reproducing device for reproducing a transmission source clock on a receiving side using clock information transmitted from a transmission source in a communication or broadcasting device, and data communication for reproducing received data based on the reproduction clock. The present invention relates to an apparatus and a clock recovery method.
[0002]
[Prior art]
For example, in the conventional clock recovery device disclosed in Japanese Patent Laid-Open No. 2001-28537, the influence of network fluctuations is obtained by obtaining the sum of the differences between the received clock information (PCR) 8 and a counter using the recovered clock as a count. Smoothing. In other words, it is the same as calculating the sum of the difference between the reception clock information with an average network delay and the counter, and the difference can be calculated in a state where the network fluctuation can be ignored. By taking the sum of the difference from the counter for a predetermined period based on all the received clock information, the frequency control is performed without being affected by the fluctuation of the network.
[0003]
[Patent Document 1]
JP 2001-28537 A
[0004]
[Problems to be solved by the invention]
However, the conventional clock recovery device has a problem that clock recovery cannot be normally performed for a large network fluctuation.
[0005]
For example, in the case of the Internet or the like, the network fluctuation may reach several tens of ms, and the counter deviation when using a 27 MHz clock under such circumstances reaches 270000 or more. The fluctuation assumed in the conventional clock recovery apparatus is about several tens of counter differences. In this case, each difference can be recognized as a difference of about 1 digit by taking the sum, but even if the sum of the differences is taken under the situation where there is a large network fluctuation as described above, it cannot be corrected to an allowable range. As a result, the frequency of the clock to be reproduced fluctuates and stable clock reproduction cannot be performed.
[0006]
Accordingly, the present invention has been made to solve the above-described problems, and provides a clock recovery device, a data communication device, and a clock recovery method capable of performing stable clock recovery even under a large network fluctuation. For the purpose.
[0007]
[Means for Solving the Problems]
  In order to solve the above problems and achieve the above object, in the clock recovery apparatus of the present invention, a clock recovery means for outputting a recovered clock at a specified frequency, and a count means for counting the recovered clock output by the clock recovery means When,Receive clock information corresponding to the smallest counter value difference every predetermined time or every predetermined number based on the counter value difference obtained by subtracting the counter value of the reception clock information from the counter value of the counting means at the time of reception clock information reception As reception clock information with the shortest delay timeSelect this selectReceivingClock control means for designating and controlling the frequency of the reproduction clock output from the clock reproduction means based on the received clock information and the count value counted by the counting means.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a clock recovery apparatus according to Embodiment 1 of the present invention.
In the figure, 1 is a clock recovery means capable of controlling the frequency of the clock, 2 is a count means for counting the clock of the clock recovery means 1, and 3 is recovered clock information counted by the count means 2 (in accordance with the MPEG-2 system standard). STC) 7 and the clock control means for controlling the frequency of the clock recovery means 1 based on the received clock information (PCR in the case of the MPEG-2 system standard) 8 transmitted and received by the transmission device (not shown). is there.
[0009]
Next, the operation will be described.
When reception clock information (PCR) 8 is transmitted from the transmission device (not shown) side, first, the counting means 2 loads the reception clock information (PCR) 8 received first as the initial value of the counter. The clock control means 3 records two counter values, that is, the counter value of the received clock information (PCR) 8 and the counter value of the reproduction clock information (STC) 7 from the count means 2. At this initial time, the clock control means 3 does not perform frequency control on the clock recovery means 1. Therefore, the clock recovery means 1 outputs a clock at a default frequency. The reception clock information (PCR) 8 is “1000” which is periodically incremented by the counter value of the clock in the transmission device (not shown) at an arbitrary interval from the transmission device (not shown). , “1040”, “1100”,..., Which are affected by transmission delay until transmission to the receiving apparatus.
[0010]
Then, the counting means 2 counts the counter by incrementing the counter one by one from the initial value in synchronization with the frequency of the reproduction clock output from the clock reproduction means 1 and provides the clock control means 3 as reproduction clock information (STC) 7. Output to.
[0011]
Thereafter, the count value of the received clock information (PCR) 8 received n-th by the counting means 2 and the clock control means 3 is PCRn, and at that time, the counting means 2 is the counter value obtained by counting the reproduction clock from the clock reproduction means 1. It is assumed that certain reproduction clock information (STC) 7 is STCn and time is Tn.
[0012]
By the way, if the frequency of the clock on the side of the transmission device (not shown) that sends the reception clock information (PCR) 8 and the frequency of the clock of the clock recovery means 1 on the side of the reception device are different, the counter increment of the unit time is different. Therefore, the absolute value of the counter difference (STCn−PCRn) increases with time.
[0013]
Since the temporal change rate of the counter difference (STCn−PCRn) indicates a frequency shift, the clock control means 3 adjusts the frequency of the clock regeneration means 1 so that the difference does not change with time. The clock reproduction synchronized with the reception clock information (PCR) 8 can be performed.
[0014]
In this way, the system standard for transmitting clock information indicating the state of the clock on the transmission side and generating a clock synchronized with the clock on the transmission side based on this clock information in the receiving device that has received this clock information is ISO / There is IEC13818-1. This is called the MPEG-2 system standard and is incorporated in various image communication systems.
[0015]
FIG. 2 is an explanatory diagram for explaining a mechanism of clock synchronization compliant with the MPEG-2 system standard. The transmitting device A is provided with PCR (Program Clock Reference) generation means A1, while the receiving device B is provided with a clock recovery device B1, and this clock recovery device B1 is shown in FIG. 1 is a clock recovery device according to the present invention.
In this MPEG-2 system standard, clock information transmitted from the transmission side is called PCR (Program Clock Reference), and clock information reproduced on the reception side is called STC (System Time Clock), and PCR is used on the transmission side. The counter value of the counter operating with the clock and STC is the counter value of the counting means 2 operating with the clock regenerated on the receiving side. The receiving device uses the PCR sent from the transmitting device to match the STC frequency in the clock recovery device of the present invention with the clock of the transmitting device.
[0016]
In the MPEG-2 system standard, a system that performs fixed packet multiplexing is called MPEG-2 TS, a system that performs variable-length packet multiplexing is called MPEG-2 PS, and clock information to be transmitted is called PCR and SCR (System Clock Reference). It is out.
[0017]
When the network transmission delay is not constant, the arrival time of the reception clock information (PCR) 8 fluctuates, and the corresponding counter value of the counting means 2 fluctuates from a desired value. As a result, the counter difference (STCn−PCRn) also fluctuates, and normal clock recovery cannot be performed.
[0018]
Therefore, in the clock recovery device B1 of the first embodiment, the clock control means 3 uses only the reception clock information (PCR) 8 which has the same transmission delay time from the reception clock information (PCR) 8 as effective reception clock information (PCR) 8. By selecting this and performing clock recovery control, normal clock recovery can be performed.
[0019]
As described above, in the clock recovery device B1 of the first embodiment, the clock control means 3 uses only the received clock information with the same delay time from the received clock information (PCR) 8 to control the clock recovery. By performing the above, stable clock reproduction that is not affected by network fluctuations can be performed.
[0020]
By the way, even if the average of the transmission delay is taken, the average value of the transmission delay is not constant depending on the situation. Further, although the transmission delay increases as much as possible depending on the situation, it does not decrease more than a certain amount due to the network configuration. Therefore, accurate clock recovery can be performed by using only the reception clock information (PCR) 8 transmitted with a stable delay time and having a small delay time.
[0021]
FIG. 3 is an explanatory diagram for explaining the relationship between the transmission time and the reception time of the reception clock information (PCR) 8.
The vertical axis represents the counter value of the clock information, and the horizontal axis represents the time. The left straight line C and the point on the straight line C indicate that the counter value of the clock having a constant frequency increases linearly on the transmission side, and the counter value is transmitted discretely.
The counter value of the reception clock information (PCR) 8, which is a point on the straight line C on the transmission side, does not change due to transmission delay, but changes only at the time and reaches the reception side.
[0022]
On the receiving side, since the slope of the straight line C on the transmitting side, that is, the frequency of the received clock information (PCR) 8 is not known, several points are collected and the same frequency can be reproduced so that clock reproduction at the same frequency as the transmitting side can be performed. It is necessary to reproduce a straight line of inclination.
[0023]
In FIG. 3, for example, two pieces of clock information D2 and D6 having a small transmission delay time are used to draw a straight line as indicated by a broken line D to be reproduced on the receiving side. In this way, by selecting two pieces of clock information from the one with the smallest transmission delay time, it is possible to select the clock information that is not affected by the transmission delay as much as possible. As a result, the slope of the straight line D matches the slope of the straight line C on the transmission side as much as possible. For this reason, by using two pieces of clock information with a short delay time, it is possible to predict the slope of the straight line C on the transmission side, and the reproduction clock information (STC) on the reception side is transmitted from the transmission side and received. The frequency of the received clock information (PCR) 8 is substantially the same. Here, the description has been made so that the slope of the straight line C on the transmission side is predicted using, for example, two pieces of clock information having a small transmission delay time, but it is needless to say that two or more may be used.
[0024]
As described above, in the clock recovery device B1 of the first embodiment, the clock control means 3 uses, for example, two reception clock information (PCR) 8 having a delay time as small as possible from the reception clock information (PCR) 8. Then, the clock frequency of the reception clock information (PCR) 8 on the transmission side is predicted, and the clock regeneration control is performed so that the frequency becomes this frequency, so that stable clock regeneration that is not affected by the fluctuation of the network can be performed.
[0025]
Note that the amount of shift in the clock frequency when the clock control means 3 performs clock regeneration control on the clock regeneration means 1 is determined in advance.
[0026]
Next, a specific method for selecting the reception clock information (PCR) 8 having a small delay time when the clock control means 3 performs clock recovery control on the clock recovery means 1 will be described next.
[0027]
<Receiving clock information with small delay time (PCR) Method 1 for selecting 8>
FIG. 4 is an explanatory diagram showing an example of a method for selecting reception clock information (PCR) 8 having a small delay time.
If the transmission timing of the clock information on the transmitting side is known, it is easy to select clock information with a small transmission delay on the receiving side, but the receiving device side does not know the clock information on the transmitting device side. FIG. 4 shows an example of a method for selecting clock information with a small transmission delay on the receiving side in a situation where clock information on the transmitting side is unknown.
[0028]
Specifically, in the case shown in FIG. 4, the clock recovery device B1 of the first embodiment generates an approximate line E using a large number of received clock information (PCR) 8. The approximate line E is, for example, a line that minimizes the sum of the squares of the distances between the points and the approximate line E. The approximate straight line E and the position of each point in the horizontal direction (time axis direction) are compared, and a point on the left side of the approximate straight line E, that is, a point having a large time difference from the approximate straight line E is a clock with a small transmission delay time. Since it can be recognized as information, if two points having a large time difference from the approximate straight line E are selected, two reception clock information (PCR) 8 having a small delay time are determined, and the influence of the transmission delay is as much as possible. The clock information that has not been received can be selected, and as in the case shown in FIG. 3, it is possible to obtain an approximate straight line E having a slope that matches the slope of the straight line C on the transmission side as much as possible.
[0029]
As described above, in the clock recovery apparatus B1 of the first embodiment, as shown in FIG. 4, an approximate line E is created from a large number of received clock information (PCR) 8, and the approximate line E and each received clock are generated. By comparing the time with the information (PCR) 8, the reception clock information (PCR) 8 with the smallest possible delay time can be selected. As a result, as in the case shown in FIG. 3, the clock frequency of the reception clock information (PCR) 8 on the transmission side is predicted using, for example, two reception clock information (PCR) 8 with a small delay time, and this frequency By performing the clock regeneration control so as to become stable, stable clock regeneration that is not affected by the fluctuation of the network can be performed.
[0030]
<Receiving clock information with small delay time (PCR) Method 2 for selecting 8>
FIG. 5 is an explanatory diagram showing another example of a method for selecting reception clock information (PCR) 8 having a small delay time. The clock information is the same as that shown in FIGS. 3 and 4, and further includes a counter value locus F of the counting means 2.
Specifically, since the frequency of the count value counted by the counting means 2 is substantially the same as the clock frequency on the transmission side, the counter value of the counting means 2 is compared with the counter value of the reception clock information (PCR) 8. By doing so, clock information with a small delay time can be selected. That is, the smaller the value obtained by subtracting the counter value of the reception clock information (PCR) 8 from the counter value of the counting means 2 when the reception clock information (PCR) 8 is received, the smaller the reception clock information (PCR ) 8. In FIG. 5, the value is smaller as the point is higher than the straight line of the trajectory F of the counting means, and the clock information has a shorter delay time.
[0031]
As described above, in the clock recovery apparatus B1 of the first embodiment, as shown in FIG. 5, the reception clock information (PCR) is calculated from the counter value of the counting means 2 when the reception clock information (PCR) 8 is received. The reception clock information (PCR) 8 having a small delay time can be easily selected by selecting a value obtained by subtracting the counter value of 8). As a result, as in the case shown in FIG. 3, the clock frequency of the reception clock information (PCR) 8 on the transmission side is predicted using, for example, two reception clock information (PCR) 8 with a small delay time, and this frequency By performing the clock regeneration control so as to satisfy the above, stable clock regeneration that is not affected by network fluctuations can be performed.
[0032]
<Frequency control of recovered clock every predetermined time>
In the above description, the number of samples of the reception clock information (PCR) 8 used when selecting the reception clock information (PCR) 8 having a small delay time, the timing of clock control, etc. are not described at all. In selecting the reception clock information (PCR) 8 having a small delay time as described above, for example, among the reception clock information (PCR) 8 received every predetermined time, the transmission delay time as shown in FIG. 5, for example, only one reception clock information (PCR) 8 having a small difference from the counter value of the counting means 2 is selected as shown in FIG. The approximate straight line D shown in FIG. 3 may be selected based on only one received clock information (PCR) 8 selected in the same manner from another predetermined period. By doing so, the clock control can be performed at a constant interval, so that the control is stable, and the control interval can be increased, so that the processing load is reduced.
[0033]
As described above, in the clock recovery device B1 of the first embodiment, only one of the received clock information (PCR) 8 received at a predetermined time is selected, and the received clock information (PCR) 8 and the others are selected. By performing clock control using only one received clock information (PCR) 8 selected in the same manner from a predetermined period of time, it is possible to perform clock reproduction control with a stable and low processing load.
[0034]
<Receiving clock information (PCR) 8 is the frequency control of the regenerative clock every predetermined number>
As in the case of every predetermined time, after receiving the reception clock information (PCR) 8 every predetermined number, only one reception clock information (PCR) 8 having a small delay time or a small difference from the counting means 2 is obtained. From the received clock information (PCR) 8 and another selected number of received clock information (PCR) 8 such as before and after, for example, only one received clock information (PCR) 8 is selected similarly. The approximate straight line D shown in FIG. 3 may be selected to perform clock control. In this way, the reception clock information (PCR) 8 can be selected with a small delay time after always securing a predetermined number of samples, so that the reception clock information (PCR) 8 with a smaller delay time can be found reliably, More accurate clock recovery with less error is possible.
[0035]
As described above, in the clock recovery device B1 of the first embodiment, only one received clock information (PCR) 8 is selected for each predetermined number, and the received clock information (PCR) 8 and other information are selected. By performing clock control using only one reception clock information (PCR) 8 selected in the same manner from a predetermined number of reception clock information (PCR) 8, the reception clock information (PCR) 8 having a small delay time is increased. Clock recovery control can be performed with probability and stable and with a low processing load.
[0036]
<Initially loaded receive clock information (PCR) Example of frequency control of recovered clock when 8 is not a small delay time>
Further, the transition of the counter value of the counting means 2 to be reproduced by this method is an approximate straight line D on the right side in FIG. 3 connected by the reception clock information having a small delay time.
However, the count value of the reception clock information (PCR) 8 that is first loaded into the counting means 2 is not necessarily a small delay time. In order to put the count value of the counting means 2 on the straight line D on the right side in FIG. 3 from this initial state, control that causes a large frequency change is required, and the clock becomes unstable as a clock recovery function. Therefore, it is not preferable.
[0037]
Therefore, when the distance between the straight line D on the right side of FIG. 3 and the initially loaded reception clock information (PCR) 8 is kept constant, that is, when clock control is performed on the clock recovery means 1, the initially loaded reception clock information. By performing the clock control by adding the difference from (PCR) 8, the slope of the frequency for clock control with respect to the clock regeneration means 1 is parallel to the straight line D on the right side in FIG. Since it is a straight line passing through the reception clock information (PCR) 8, this may be used as a trace of the counter value of the counting means 2. As a result, it is possible to perform control so as to match the clock frequency on the transmission side from the time of initial loading, and stable clock reproduction can be performed.
[0038]
As described above, in the clock recovery device B1 of the first embodiment, the counter difference between the approximate line D on the right side shown in FIG. 3 and the initially loaded reception clock information (PCR) 8 is held, By performing clock regeneration control so that the locus obtained by adding the count difference to the approximate straight line D on the right side shown in FIG. 3 becomes the locus of the counter value of the counting means 2, the received clock information (PCR) 8 that has been initially loaded and the delay It is possible to prevent fluctuations in the clock frequency due to a difference from the approximate straight line D on the right side of FIG.
[0039]
<Region (zone) management for counter difference (STCn-PCRn)>
In addition, the temporal change rate of the counter difference (STCn−PCRn) between the recovered clock information (STC) 7 and the received clock information (PCR) 8 indicates the frequency shift of the recovered clock in the clock recovery means 1. When the counter difference (STCn−PCRn) includes an error due to network fluctuation, the clock frequency to be reproduced fluctuates when clock control is performed based on this difference.
[0040]
For this reason, the counter difference (STCn−PCRn) may always include an error, and the reproduction clock control may be performed only when the counter difference is generated such that it cannot be regarded as an error.
That is, management for the counter difference (STCn-PCRn) is performed in the area (zone), and the clock control is maintained as it is in the zone where the counter difference (STCn-PCRn) changes within a certain zone. The clock frequency is controlled at a time exceeding
[0041]
By doing this, stable and accurate clock recovery control can be performed by performing clock control when the frequency difference can be clearly recognized without disturbing the recovered clock due to an error included in the counter difference.
[0042]
As described above, management based on the counter difference (STCn-PCRn) is performed in the zone, and the reproduction clock is controlled only when the counter difference exceeds the zone. If the counter difference (STCn-PCRn) is within the zone even if an error is included, the clock control is not performed based on the counter difference (STCn-PCRn), and the frequency of the recovered clock varies due to network fluctuations. Can be prevented, and stable and accurate clock reproduction can be performed.
[0043]
<Frequency control of recovered clock when counter difference (STCn-PCRn) shifts in a larger or smaller direction>
When a sample with a small delay time is selected from a number of samples of the received clock information (PCR) 8 for each predetermined period or every predetermined number, there are cases in which a sample with a small transmission delay time is not actually included. It is possible. Then, it recognizes that the transmission delay time is not small but is small, and the deviation of the counter difference (STCn−PCRn) between the reproduction clock information (STC) 7 and the reception clock information (PCR) 8 is represented by the reproduction clock information ( The frequency difference between the STC) 7 and the received clock information (PCR) 8 is erroneously recognized.
[0044]
For this reason, a delay time or count difference sample detected in a previous period or a predetermined number of ranges is smaller than a delay time or a count difference sample that is not found in the next period or a predetermined number of ranges. When STCn-PCRn) is shifted in the direction of increasing, the number of samples is further increased to search for a sample having a smaller delay time or count difference, for example, a smaller counter difference (STCn-PCRn). Assuming that the frequency is really shifted, for example, clock control is performed using reception clock information (PCR) 8 with a small sample of delay time and count difference in that period or a predetermined number of ranges.
[0045]
On the other hand, when the counter difference (STCn−PCRn) decreases, it is a case where a sample with a smaller delay time is found, but there is a limit to the minimum value of the delay time, and a sample with an extremely small delay time. Does not exist. Therefore, when the counter difference deviates in the direction of decreasing, it is a time when the frequency is really shifted. Therefore, the reception clock information (PCR) 8 in which the delay time or the sample of the count difference is small within that period or a predetermined number of ranges immediately. To control the clock.
[0046]
As described above, based on the direction of deviation of the counter difference (STCn−PCRn), the number of samples is increased by increasing the sample extraction period or the number of extractions of the reception clock information (PCR) 8, or the sample extraction period or the number of extractions. Since the clock control is performed using the reception clock information (PCR) 8 having a small delay time and a small count difference within the range of the sample extraction period or the number of extractions, the counter difference is determined. The clock control can be changed according to the direction of deviation of (STCn-PCRn), and stable and quick clock regeneration control can be performed.
[0047]
Embodiment 2. FIG.
In the first embodiment described above, it has been described that the clock regeneration control is performed using coefficients such as a preset sample extraction period, the number of sample extractions, and a frequency shift regardless of the magnitude of the network fluctuation. However, in the second embodiment, the control method such as the coefficient is changed in accordance with the network fluctuation situation so that optimum clock regeneration can always be performed.
[0048]
FIG. 6 is a configuration diagram illustrating the clock recovery device according to the second embodiment.
In the figure, reference numeral 4 denotes fluctuation prediction means for predicting the magnitude of network fluctuation from information of the reproduction clock information (STC) 7 and the reception clock information (PCR) 8. In FIG. 6, the same reference numerals as those in FIG. 1 are the same or equivalent elements as those in FIG.
[0049]
Next, the operation will be described. The operation is the same as that of the first embodiment except for the operation described below.
The fluctuation prediction means 4 predicts the magnitude of the network fluctuation from the fluctuation of the counter difference (STCn−PCRn) between the reproduction clock information (STC) 7 and the reception clock information (PCR) 8, and the clock control means 3 Notify
[0050]
The clock control means 3 determines and controls the frequency of the recovered clock of the clock recovery means 1 from the recovered clock information (STC) 7, the received clock information (PCR) 8, and the network fluctuation prediction information predicted by the fluctuation prediction means 5. To do.
[0051]
Since the magnitude of the network fluctuation is proportional to the amount of fluctuation of the counter difference (STCn−PCRn), it can be estimated to some extent by the difference between the maximum value and the minimum value of the counter difference within a certain time or the number of samples.
[0052]
When the network fluctuation is large, the possibility that the delay time of the reception clock information (PCR) 8 approaches the minimum value is low. If the clock recovery control is performed without using the reception clock information (PCR) 8 whose delay time is close to the minimum value, an error is likely to be included, so that accurate clock recovery cannot be performed. Therefore, when the network fluctuation is large, increasing the number of samples of the reception clock information (PCR) 8 increases the probability of selecting the reception clock information (PCR) 8 whose delay time is close to the minimum value, and accurate clock recovery. Can be performed. By increasing the sample time, the number of samples can be increased.
[0053]
However, increasing the number of samples of the received clock information (PCR) 8 and the sample time result in a longer control interval, which makes it impossible to perform rapid clock recovery.
[0054]
Therefore, when the fluctuation is small, the clock time can be quickly reproduced by reducing the sample time or the number of samples of the reception clock information (PCR) 8 and controlling the frequency of the reproduction clock of the clock reproduction means 1.
[0055]
As described above, according to the second embodiment, the fluctuation prediction means 5 predicts the magnitude of the network fluctuation, and the period and the number of samples of the reception clock information (PCR) 8 sampled according to the predicted magnitude of the network fluctuation. Therefore, the clock can be quickly and stably reproduced according to the magnitude of the network fluctuation.
[0056]
Further, when the clock difference is managed in the zone as described in the first embodiment, in the second embodiment, the size of the zone may be changed depending on the size of the network fluctuation. In other words, when the network fluctuation is large, stable clock reproduction can be performed by increasing the zone of the clock difference so that the fluctuation is not erroneously recognized as a frequency change. When the fluctuation is small, the clock difference zone is reduced to shorten the time until the zone is exceeded. As a result, the control interval is also shortened and the clock regeneration control can be performed quickly.
[0057]
As described above, it is possible to perform quick and stable clock reproduction by predicting the magnitude of the network fluctuation by the fluctuation prediction means 5 and changing the size of the zone for managing the counter difference according to the predicted fluctuation magnitude. it can.
[0058]
In the second embodiment, “received clock information with a small delay time” is a variety of processing performed when the clock control unit 3 described in the first embodiment performs clock recovery control on the clock recovery unit 1. “Method 1 for selecting (PCR) 8”, “Method 2 for selecting reception clock information (PCR) 8 with a short delay time”, “Frequency control of regenerative clock every predetermined time”, “ "Received clock information (PCR) 8 is frequency control of regenerated clock for every predetermined number", "Example of frequency control of regenerated clock when initially loaded received clock information (PCR) 8 is not a small delay time", "Counter difference The frequency control of the reproduction clock when (STCn-PCRn) deviates in a large or small direction may be performed. In this way, the effect described in the first embodiment is obtained together with the effect of the second embodiment.
[0059]
Embodiment 3 FIG.
In the first and second embodiments described above, the clock recovery control is performed under the condition where the transmission delay is caused by the network fluctuation. However, in the third embodiment, more accurate regardless of the presence or absence of the network fluctuation. An embodiment for performing high clock recovery control will be described. The configuration of the clock recovery device is the same as that of the first embodiment shown in FIG. 1 or the second embodiment shown in FIG. Only the operation will be described.
[0060]
Since the basic clock regeneration control operation excluding the control algorithm in the clock control means 3 is the same as in the first and second embodiments, the description thereof will be omitted.
[0061]
FIG. 7 is an explanatory diagram showing changes in counter values on the transmission side and the reception side.
The transmitting side and receiving side clocks each operate at a predetermined frequency, and the counter means 2 is incremented at that frequency. For this reason, the transition of the counter value is increased step by step like a staircase. FIG. 7 shows a locus when it is assumed that the counter continuously increases. The counter value at a certain time is obtained by rounding down or rounding up the decimal value of the counter value indicated by the point intersecting with the time on the straight line indicating the locus F of the counter value. For example, the counter value on the transmission side at time t0 indicates 123.2 on the straight line, but the actual counter value becomes 123 when rounded down.
[0062]
In order to recognize the frequency difference between transmission and reception, the amount of change in the difference between the transmission and reception counters per unit time is required.
The counter difference from t0 to t13 in FIG. 7 is -1, 0, 0, 1, 1, 0, 1, 1, 1, 2, 1, 1, 2, 2.
When obtaining the difference between the counter values that change stepwise in this way, an error of ± 1 due to rounding down or rounding up is added, and an accurate frequency difference cannot be obtained. This is a kind of quantization error.
[0063]
Since the frequency difference in FIG. 7 is a variation of the difference indicated by two straight lines per unit time, if the frequency difference is obtained using only the information of the point that accurately indicates the difference between the two straight lines, the frequency difference is accurate. Clock reproduction can be performed. The value obtained by subtracting the straight line on the transmission side from the straight line on the reception side increases with time. The counter difference indicates 1 when there is one counter value change point between two straight lines. At this time, the difference between the two straight lines is greater than 0 and smaller than 2.
[0064]
When the counter difference increases little by little as shown in FIG. 7, the linear difference increases with time at a plurality of times having the same counter difference. The first change point of the counter difference value has the smallest linear difference among the points having the same counter difference value. At this time, the linear difference is close to a value obtained by subtracting 1 from the counter difference.
Therefore, the first change point of the counter difference value is a value close to {Linear difference + 1}.
[0065]
By performing clock control using only points at which straight line differences can be obtained with a certain degree of accuracy, accurate clock reproduction can be performed. Therefore, clock control is performed using only the first change point of the value of the counter difference.
In FIG. 7, when the frequency difference is obtained using the counter difference between t3 and t9, which is the first change point of the counter difference value, a more accurate frequency difference is obtained. The frequency difference obtained by the calculation is {(counter difference at t9) − (counter difference at t3)) / time = (2-1) / 6Δt = 1 / 6Δt, and the difference between the slopes of the two straight lines shown in FIG. Is almost the same.
[0066]
Even if only the last change point of the counter difference value is used, an accurate frequency difference can be obtained. The last change point of the counter difference value is close to {Linear difference-1}.
In FIG. 7, the frequency difference obtained by using t5 and t11, which is the last change point of the counter difference value, is similarly 1 / 6Δt.
[0067]
As described above, according to the third embodiment, even when the counter difference changes only slightly, an accurate frequency difference is obtained by using only information on the first or last change point of the counter difference. Accurate clock recovery can be performed.
[0068]
In the third embodiment, the control algorithm in the clock control means 3 is different from that in the first and second embodiments. However, the present invention is not limited to this, and the clock control means 3 in the first and second embodiments is not limited thereto. Of course, the control algorithm of the third embodiment may be purchased for the control algorithm in FIG.
[0069]
In the first to third embodiments described above, PCR (Program Clock Reference) and STC (System Time Clock) in the MPEG-2 system standard are described as examples of the reception clock information 8 or the reproduction clock information 7, but the present invention is not limited thereto. However, the present invention is not limited to this, and any invention may be used as long as it generates synchronization by generating the reproduction clock information 7 on the reception side based on the clock information 8 on the transmission side, and is not limited to the MPEG-2 system standard. .
[0070]
【The invention's effect】
According to the present invention, the reproduction clock is counted and only valid reception clock information (PCR) 8 is selected from the reception clock information (PCR) 8 received from the transmission side, and the selected reception clock information (PCR) is selected. ) Since the frequency of the recovered clock is controlled based on 8 and the count value, it is possible to perform stable clock recovery even under a large network fluctuation.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a clock recovery device according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram illustrating a clock synchronization mechanism compliant with the MPEG-2 system standard.
FIG. 3 is an explanatory diagram for explaining a relationship between a transmission time and a reception time of reception clock information (PCR) 8;
FIG. 4 is an explanatory diagram showing an example of a method for selecting reception clock information (PCR) 8 having a small delay time.
FIG. 5 is an explanatory diagram showing another example of a method for selecting reception clock information (PCR) 8 having a small delay time.
FIG. 6 is a configuration diagram showing a clock recovery device according to a second embodiment;
FIG. 7 is an explanatory diagram showing changes in counter values on the transmission side and the reception side in the third embodiment.
[Explanation of symbols]
1 clock recovery means, 2 count means, 3 clock control means, fluctuation estimation means.

Claims (8)

Clock recovery means for outputting a recovered clock at a specified frequency;
Counting means for counting the recovered clock output by the clock recovery means;
Receive clock information corresponding to the smallest counter value difference every predetermined time or every predetermined number based on the counter value difference obtained by subtracting the counter value of the reception clock information from the counter value of the counting means at the time of reception clock information reception select the smallest receive clock information delay time, specified by controlling the frequency of the recovered clock said counting means and the selected received clock information is output from said clock reproduction means based on the count value obtained by counting And a clock control device. Fluctuation estimation means for estimating fluctuations in the transmission delay time of the network from the received clock information,
2. The clock recovery apparatus according to claim 1, wherein the clock control means determines the predetermined time based on a fluctuation magnitude of a network transmission delay time estimated by the fluctuation estimation means.   The clock recovery means according to claim 1, wherein the clock control means controls the reproduction clock frequency output from the clock recovery means by maintaining the transmission delay time of the received clock information received first. apparatus. Said clock control means, characterized in that the the value of the counter value difference is classified into a plurality of zones, the counter value difference to control the frequency of the reproduction clock output from said clock reproduction means only when it is classified into different zones The clock recovery device according to claim 1. It said clock control means, depending on the size of the fluctuation of the transmission delay time of the network, and change the size of the zone for classifying pre Symbol counter value difference to specify the frequency of the reproduced clock output from the clock recovery means 5. The clock recovery device according to claim 4 , wherein the clock recovery device is controlled. As a result of calculating the counter value difference, the clock control means increases the predetermined time or the predetermined number when the counter value of the counting means increases from before and the counter value difference enters a different zone. 5. The clock according to claim 4 , wherein the counter value difference is calculated by controlling the frequency of the recovered clock output from the clock recovery means only when the counter value difference is classified into different zones. Playback device. Said clock control unit, when the counter value difference is within the range of the quantization error, select the receive clock information for the first or last change point in its counter value difference as the smallest receive clock information pre Symbol transmission delay time The clock recovery apparatus according to claim 1, wherein: A clock recovery step for outputting a recovered clock at a specified frequency;
A counting step for counting the recovered clock output by the clock recovery step;
The reception clock information corresponding to the smallest counter value difference is transmitted every predetermined time or every predetermined number based on the counter value difference obtained by subtracting the counter value of the reception clock information from the counter value of the count step at the time of reception clock information reception. select the smallest receive clock information delay time, specified by controlling the frequency of the recovered clock said counting step and the selected received clock information is output from the clock reproducing step based on the count value obtained by counting A clock regenerating method comprising the steps of:

Images