JP4145375B2 - Data driving device and driving method for liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device (TFT-LCD), and more particularly, to a data driver (Source Driver) and a driving method of a liquid crystal display device incorporating a multi-scan function.
[0002]
[Prior art]
In general, “multiplex-scan” is to display a low resolution (lower video mode) video signal in a vertical direction on a high resolution LCD panel. A method of enlarging image data in the vertical direction using a frame memory or the like, whereas expansion in the horizontal direction is made relatively easy by increasing the sampling rate. Is not easy. Of course, reducing the high resolution video source to display on the low resolution LCD panel is also included in the multi-scan, which is possible by removing some of the video source data. However, in order to display a low-resolution video source on a high-resolution LCD module, a data driving device of a conventional liquid crystal display device should always supply a video signal with a resolution corresponding to the LCD module to the driving IC. Separately, the resolution of the video signal should be converted according to the LCD module to be displayed.
[0003]
Hereinafter, a data driving circuit of a conventional liquid crystal display device will be described with reference to the accompanying drawings.
[0004]
FIG. 1 is a block diagram of a conventional data driving device of a liquid crystal display device, showing an internal structure of a 192-output 6-bit gray-scale data driving IC. FIG. 2 is a detailed block diagram of the 192 × 6 bit 2-line latch portion of FIG.
[0005]
As shown in FIG. 1, a conventional data driving device of a liquid crystal display device shifts a carry input / output signal (carry I / O) in both directions based on an external clock signal and outputs it in both directions. R, G, B video signal data (6 bits each) input from the outside based on a carry register input / output signal output from the shift register (64 bits Bidirectional Shift Resistor) 1 and the 64-bit bidirectional shift register 1 192 × 6 bits 2-line latch unit (192 × 6 bits 2-line Latch) 2 for outputting the stored data based on an external load signal, and the 192 × 6 192 × 6 bits Digital / Analog Converter (192 × 6 bits Digital / Analog Converter) 3 for converting video signal data output from the bit 2-line latch unit 2 into an analog signal based on an external POL signal , And a the 192 × 6-bit digital / 192 data output section for outputting the TFT-LCD panel based analog video signal to an external POL signal outputted from the analog conversion unit 3 (192 Data Output Circuits) 4.
[0006]
A detailed configuration of the 192 × 6 bit 2-line latch unit 2 of the data driver of the conventional liquid crystal display device configured as described above is shown in FIG.
[0007]
That is, the 192 × 6 bit two-line latch unit 2 includes two latches (first latch 2a and second latch 2b), and each latch 2a and 2b latches R, G, and B video signals, respectively. Requires three 192 × 6 bit latches or registers. When the first latch unit 2a stores the data based on a load signal input from the outside, the second latch unit 2b outputs the stored data to the 192 × 6 bit digital / analog conversion unit 3 and outputs the second latch When the unit 2b stores, the first latch unit 2a is configured to output the stored data, and alternately performs the function of storing and outputting for each line.
[0008]
The operation of the data driving circuit of such a conventional liquid crystal display device will be described below.
[0009]
First, if the LCD module to be displayed is a VGA (640 × 480 image), at least 10 drive ICs described in FIG. 1 are required, and the LCD module is an XGA (1024 × 768 image). In this case, at least 16 drive ICs are required. This is because the VGA module is composed of 640 × 3 = 1920 dots, the driving IC shown in FIG. 1 has 192-outputs, and the R, G, and B signals constitute one pixel, so that the number of dots of 1920 is obtained. For this purpose, 10 pieces (192 × 10 = 1920) are required. Since the XGA module is composed of 1024 × 3 = 3072 dots, 16 (192 × 16 = 3072) are required.
[0010]
As described above, conventionally, as many drive ICs as necessary according to the LCD module must be attached to the LCD panel, and a video signal corresponding to the module must be applied to the data drive IC. For this reason, when an externally input video signal is applied to the LCD module, the latch unit 2 latches and stores the data alternately input from the first latch and the second latch based on the load signal. Or output stored data. The data output from the latch unit 2 is converted into an analog signal by the digital / analog conversion unit 3 and applied to each data line of the LCD panel via the data output unit 4.
[0011]
[Problems to be solved by the invention]
However, the data driving circuit of the conventional liquid crystal display device has the following problems.
[0012]
First, the data driving circuit of the conventional liquid crystal display device should have a driving IC in accordance with the LCD module. Since the video signal corresponding to the module is not supplied to the driving IC, it is not displayed. Could not be displayed.
[0013]
Second, when a video signal that does not correspond to a module is displayed without replacing or adding a driving IC, a separate module conversion device should be added to the outside.
[0014]
The present invention has been made to solve the above problems, and a liquid crystal display having a built-in multi-scan function capable of displaying a video source different from a panel in a suitable size by enlarging and reducing the video source. It is an object of the present invention to provide a data driving apparatus and a driving method of the apparatus.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the data driving device of the liquid crystal display device of the present invention records one line signal of a video signal input based on external control at a corresponding address or reads out the recorded signal. First, second, and third memory units that output, an output selection unit that selects and outputs only one output signal from the first, second, and third memory units, and the first, second, Each of the first, second, and third memories so that one of the third memory units operates as an input mode, the other operates as a holding mode, and the other operates as an output mode. And a control unit that controls writing and reading of the unit and controls the output of the output selection unit.
[0016]
In order to achieve the above object, a data driving method for a liquid crystal display device according to the present invention includes a first, a second and a third memory unit, and a data driving method for a liquid crystal display device which displays video signals having different resolutions. The input mode is repeatedly selected in the order from the first memory to the third memory, and the output mode is set to be repeatedly selected in the order from the third memory to the first and second memories. Due to the difference between the first stage and the input speed and the output speed, every time the memory operating as the input mode should be selected as the output mode, the memory previously selected as the output mode is again set as the output mode. And a second stage to be selected.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the data driving device and driving method of the liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.
[0018]
FIG. 3 is a block diagram showing the configuration of the data driving device of the liquid crystal display device according to the first embodiment of the present invention, taking an example of a 192-output 6-bit size (Gray-Scale). 4 is a detailed configuration diagram of the latch unit of FIG. 3, FIG. 5 is a detailed configuration diagram of the control unit of FIG. 3, and FIG. 6 is a circuit configuration diagram of the comparison unit of FIG.
[0019]
As shown in FIG. 3, the data driving device of the liquid crystal display device of the present invention has a 64-bit bi-directional shift register (64 bits Bidirectional Shift Resistor) that shifts and outputs a carry input / output signal in both directions based on an external clock signal. ) 11 and three latches (first latch, second latch, and third latch). Based on an external control signal, a carry input / output signal output from the 64-bit bidirectional shift register 11 for each latch is provided. R, G, and B video signal data (six bits each) that are synchronized and input from the outside are sequentially stored (data latch mode), and the stored data is retained (data retention mode) data hold mode), and output the held video signal data (data output mode) from the latch unit 12 and the latch unit 12 192 × 6 bits digital / analog converter 13 for converting input video signal data into analog signals based on an external POL signal, and the 192 × 6 bits digital / analog converter The 192 data output circuit (192 Data Output Circuits) 14 for outputting the analog video signal output from the unit 13 to the TFT-LCD panel based on the external POL signal, and the data of the 192 × 6 bit 3-line latch unit 12 It is comprised with the control part 15 which controls an input, an output, and holding | maintenance.
[0020]
Here, as an example, three latches of the latch unit 12 are illustrated using a 192 × 6 bit 3-line memory. That is, the latch unit 12 includes three latches (a first latch 12a, a second latch 12b, and a third latch 12c) as shown in FIG. 4, and each of the latches 12a, 12b, and 12c is inputted with R, G, and B. The video signal data is latched, and the data latch mode, the data holding mode, and the data output mode are repeatedly performed based on the control signal of the control unit 15.
[0021]
The configuration of the control unit 15 is as shown in FIG.
[0022]
That is, the control unit 15 operates as a data latch mode among the three latches of the latch unit 12 by using the horizontal synchronization signal of the video signal as a clock signal and the vertical synchronization signal as a clear and load signal. The first selection unit 16 that outputs a selection signal for selecting the latch to be selected and the horizontal synchronization signal of the input video signal are divided into the number of lines of the corresponding LCD module (1024 in the case of 1024 × 769). A PLL unit 17 for outputting a dot clock or a master clock and an LCD module for one vertical synchronization period so that the frequency can be varied and the vertical expansion and reduction can be performed. The variable oscillation section 18 that outputs the number of scan lines (768 in the case of 1024 × 768) gate start pulse, and the data output mode and data in the latch section 12 The latch unit 12 is configured so that the latch mode is not simultaneously performed in one latch, the signal output from the comparator 19 is a clock signal, and the vertical synchronization signal is a clear & load signal. The second selection unit 20 selects a latch operated as a data output mode.
[0023]
Here, the comparison unit 19 is as shown in FIG.
[0024]
That is, the first latch mode selection signal (IN A) output from the first selection unit 16 and the third output mode selection signal (OUT C) output from the second selection unit 20 are ANDed and inverted. The first NAND gate 19a to be output, the second latch mode selection signal (IN B) output from the first selection unit 16, and the first output mode selection signal (OUT A output from the second selection unit 20). ) And the second NAND gate 19b that inverts and outputs, the third latch mode selection signal (IN C) output from the first selection unit 16, and the second NAND gate 19b output from the second selection unit 20. A third NAND gate 19c that performs a logical product operation and inverts and outputs the two output mode selection signal (OUT B), and a logical product operation of the signals output from the first, second, and third NAND gates 19a, 19b, and 19c. Output first AND gate 9d and, and a second 2AND gate 19e for outputting an output signal of the output signal of the first 1AND gate 19d variable oscillation unit 18 ANDs the clock signal of the second selector 20.
[0025]
The operation of the data driving device of the liquid crystal display device according to the first embodiment of the present invention thus configured will be described below.
[0026]
FIG. 7 is an explanatory diagram for explaining the multi-scan operation of the data driver of the liquid crystal display device according to the first embodiment of the present invention. In order to more easily understand the operation of the data driving device of the liquid crystal display device of the present invention, a method of displaying video signal data of VGA resolution (640 × 480) on an LCD panel having XGA resolution (1024 × 768). This will be described as an example.
[0027]
First, the first selection unit 16 uses the horizontal synchronization signal (H-sync) of the video signal of VGA resolution as a clock signal, and each time there is a horizontal synchronization signal (H-sync), the first selection unit 16 of the latch unit 12 2. The third latches 12a, 12b, and 12c are selected so as to be sequentially rotated to the data latch mode. At this time, the first latch 12a is selected first, and the second latch 12b and the third latch 12c are rotated in this order, and the vertical synchronization signal (V-sync) is input in the repeated process. Then, it is initialized so that the first latch 12a is operated again.
[0028]
The PLL unit 17 divides the horizontal synchronization signal (H-sync) of the input VGA video signal into 1024 and outputs it as a dot clock signal of the data driver of the present invention. As described above, the first selection unit 16 selects one of the three latches to be operated in the latch mode, and the second selection unit 20 is also operated in the output mode among the three latches. Select. The operation of the second selection unit 20 is also initialized so that the third latch 12c is first operated in the output mode, and is rotated in the order of the first and second latches 12a and 12b. The control unit 19 operates as follows.
[0029]
That is, when initialized, the first selection unit 16 selects the first latch 12a in the data latch mode, and the second selection unit 20 selects the third latch 12c in the data output mode. The variable oscillator 18 outputs 768 gate start pulses so that the XGA resolution can be displayed during one vertical synchronization period.
[0030]
The comparison unit 19 performs a logical operation on the current selection signal of the first selection unit 16 and the selection signal of the second selection unit 20 so that the clock signal from the variable oscillation unit 18 is output. That is, as shown in FIG. 7, the first selection unit 16 outputs a selection signal (IN A) so that the first latch 12a is operated in the data latch mode, and the second selection unit 20 outputs the third signal. Since the selection signal (OUT C) is output so that the latch is operated in the data output mode, the first NAND gate 19a of the comparison unit 19 outputs the “low (L)” signal. For this reason, a “low” signal is output from the first AND gate 19d and the second AND gate 19e regardless of the outputs of the second and third NAND gates 19b and 19c, so that the clock signal is not applied to the second selection unit 20. Therefore, the second selection unit 20 operates the third latch 12c in the data output mode. However, since no data is stored in the third latch 12c, there is no output data.
[0031]
As described above, when the first selection unit 16 selects the first latch 12a as the data latch mode and the first one line of the input video signal is stored in the first latch 12a, it is synchronized with the next horizontal synchronization signal. Then, the second latch 12b is selected in the data latch mode, so that the input video signal of the second one line is stored in the second latch 12b. At this time, in the comparison unit 19, the first selection unit 16 selects the second latch 12b in the data latch mode (IN B), and the second selection unit 20 selects the third latch 12c in the data output mode. (OUT C), the first, second, and third NAND gates 19a, 19b, and 19c all output “high (H)” signals, and the first AND gate 19d also outputs “high” signals. Thus, the second AND gate 19 e outputs the pulse of the variable oscillation unit 18 to the second selection unit 20. Therefore, the second selection unit 20 outputs the selection signal (OUT A) so that the first latch 12a operates in the data output mode at the moment when the pulse output from the second AND gate 19e is input. The latch 12b is operated in the data latch mode, the first latch 12a is operated in the data output mode, and at that moment, the selection signal (IN B) and the selection signal (OUT A) are supplied to the second NAND gate 19b of the comparison unit 19. Since “high” is input, the comparator 19 does not output a clock signal.
[0032]
As described above, the first latch 12a operates in the data output mode and the second latch 12b operates in the data latch mode at the same time, but the second latch 12b operates at a VGA resolution (640 × 480) speed of the input video signal. Since the data is latched at the first latch 12a and the data is output at the XGA resolution (1024 × 768) speed, before the second one line of the input video signal is all latched by the second latch 12b. In addition, the video signal of the first line latched by the first latch 12 a is output to the digital / analog converter 13. However, even if all the data latched in the first latch 12a is output, the clock signal is not output from the comparison unit 19 to the second selection unit 20, so that the second selection unit 20 continues to output the data from the first latch 12a. The selection signal (OUT A) is output so as to operate as a mode. Therefore, as shown in FIG. 7, while the second latch 12b is latching data, the data latched in the first latch 12a is output twice.
[0033]
When the video signal of the second one line is completely latched in the second latch 12b and the next horizontal synchronization signal is input, the first selector 16 operates the third latch 12c in the data latch mode. Thus, since the selection signal (IN C) is output and the comparison signal 19 is “high” in the selection signal (IN C, OUT A) and “low” in the rest, the clock signal is output to the second selection unit 20. Output to. Accordingly, the second selection unit 20 outputs the selection signal (OUT B) so that the second latch 12b is operated in the data output mode by the above-described method. At this time, the third NAND gate 19c of the comparison unit 19 is output. Outputs a “low” signal and no clock signal is applied to the second selector 20.
[0034]
When all the data latched in the second latch is output in such a manner that the data latch of the third latch 12c is not completely performed, the data latched in the second latch is output again. When the first selector 16 selects the first latch 12a in the data latch mode, the second selector 20 causes the third latch 12c to operate in the data output mode. At this time, when the data latched in the third latch 12c is being output in time, all the input video signal data for one line is latched in the first latch 12a, and then the second latch 12b receives the next data. Since the data of the second line is latched, the data latched in the third latch 12c is output only once, and the latched data is output in the first latch 12a. Five lines of the video signal having VGA resolution inputted in this manner are multi-scanned into eight lines, and finally 480-lines are displayed on 768-lines.
[0035]
FIG. 8 is a conceptual explanatory diagram of the data driving device of the liquid crystal display device according to the second embodiment of the present invention, and FIG. 9 is a block diagram of the configuration of the data driving circuit of the liquid crystal display device of the second embodiment. 10 is a detailed circuit diagram of the control unit of FIG. The driving method of the data driving device of the liquid crystal display element of the second embodiment of the present invention is the same as that of the first embodiment of the present invention, but the driving device is different.
[0036]
As shown in FIG. 8, the data driver of the liquid crystal display device according to the second embodiment of the present invention includes three line memories, and rotates to an input mode, a holding mode, and an output mode using a multiplexer and a demultiplexer. However, the switching is performed so that the multi-scanning can be performed as in the first embodiment of the present invention. Here, a memory such as SRAM or DRAM may be used instead of the line memory.
[0037]
As in the first embodiment, the description will be made on the assumption that a video signal of VGA resolution is displayed on an XGA resolution panel, and data driving of the same structure is performed for each of the R, G, and B video signals. Although a device is required, only one color signal will be described.
[0038]
As shown in FIG. 9, the configuration of the data driving device of the liquid crystal display device according to the second embodiment of the present invention includes a first memory 26 and a first multiplexer 27, and is input based on an external control signal. It consists of a first memory 21, a second memory 28, and a second multiplexer 29 that record one line signal of a video signal to a corresponding address, or read and output the recorded signal. It comprises a second memory 22 for recording one line signal of a video signal inputted based on the address, reading out the recorded signal and outputting it, a third memory 30 and a third multiplexer 31, and external control. A third memory 23 for recording one line signal of a video signal input based on the signal at a corresponding address, or reading and outputting the recorded signal, and a tri-state buffer (Tri-State Buffer) 32, 33, 34, an output selection unit 24 that selects and outputs only one output signal from the video signals output from the first, second, and third memory units 21, 22, 23, and an input One of the first, second, and third memory units 21, 22, and 23 is inputted with a vertical synchronization signal (IV-sync) and a horizontal synchronization signal (IH-sync) of a VGA resolution video signal. The operation (reading or writing) of the memories 26, 28, and 30 of each of the memory units 21, 22, and 23 so that the other one operates in the holding mode and the other operates in the output mode. It is comprised with the control part 25 which controls the output of each multiplexer 27, 29, and 31 and the output of an output selection part.
[0039]
Here, the configuration of each memory unit will be described in detail below.
[0040]
That is, the VGA video signal is input to the input terminals (IN) of the memory units 26, 28, and 30, and the selection signal of the control unit 25 is connected to the inverters 60, 61, and 62 at the read / write terminals (read / write). The output signals of the multiplexers 27, 29, and 31 are input to the address clock terminal (address clock), and the output terminal (OUT) is connected to the output selection unit 24. The logical clear operation signal of the input of the corresponding memory and the output selection signal is input to the address clear end (address clear) of each memory 26, 28, 30 via the OR gates 63, 64, 65. An input clock signal (ICLK) and an output clock signal (OCLK) are input to the input terminals of the multiplexers 27, 29, and 31, and a selection signal of the control unit 25 is input to the selection terminal (select). Here, the input clock signal (ICLK) is a sampling clock obtained by dividing the horizontal synchronizing signal of the input VGA video signal into a PLL, and can sample 1024 signals during one horizontal period. It is a thing. The output clock signal (OCLK) is a clock for reading data from the memory to drive the LCD panel, and is a clock input to the driving IC.
[0041]
On the other hand, the configuration of the control unit 25 is as shown in FIG.
[0042]
That is, the first ternary counter 52 And the first decoder 51 The horizontal synchronization signal (IH-sync) of the input VGA video signal is used as a clock signal, and the vertical synchronization signal (IV-sync) of the VGA video signal is used as a reset signal. A first selection unit 41 that outputs a selection signal (IA, IB, IC) so that one of the memory units 21, 22, 23 can be operated in an input mode, and a horizontal synchronization signal (IH) of an input VGA video signal -sync) is divided into 1024, and the PLL unit 44 outputs a clock signal (ICLK) so that 1024 samples can be sampled for one horizontal period, and the vertical synchronization signal (IV-sync) of the input VGA video signal ) As a reset signal, oscillates 768 gate start pulse signals (OCLK) for one vertical period, and counts 1024 clock signals output from the variable oscillating section 42 to 1024 counter 45 that outputs as synchronization signal (OH-sync), 4 AND gates 53, 54, 55, 57 and 1 NOR gate 56 The first selection unit selection signals (IA, IB, IC) and the second selection unit selection signals (OA, OB, OC) described later are subjected to a first logical operation, and the output pulse of the 1024 counter A second logical operation of the signal, a comparison unit 43 that compares one of the memory units so that the memory unit is not operated in the input mode and the output mode at the same time, a second ternary counter 58, and a second The first, second, and third memory units 21 include a decoder 59, and the vertical synchronization signal (IV-sync) of the input VGA video signal is used as a reset signal, and the output signal of the comparison unit 43 is used as a clock signal. , 22, and 23, the second selection unit 46 that outputs selection signals (OA, OB, OC) so that one memory unit operates in the output mode.
[0043]
The configuration of the control unit 25 will be described in detail below.
[0044]
The first selection unit 41 includes a first ternary counter 52 that outputs a ternary count using the vertical synchronization signal of the input VGA video signal as a reset signal and a horizontal synchronization signal as a clock signal; The first decoder 51 outputs a selection signal (IA, IB, IC) so that one of the three memory units is operated in the input mode by decoding the signal output from the ternary counter 52. The Here, the selection signal (IA) is a selection signal for operating the first memory unit 21 in the input mode, and the selection signal (IB) is a selection signal for operating the second memory unit 22 in the input mode. The selection signal (IC) is a selection signal for operating the third memory unit 23 in the input mode, and the selection signal (IA) is always output initially.
[0045]
The second selection unit 46 uses the vertical synchronization signal of the input VGA video signal as a reset signal, the output signal of the comparison unit 43 as a clock signal, and outputs a second ternary counter 58 that performs ternary counting, The second decoder 51 outputs the selection signal (OA, OB, OC) so that one of the three memory units is operated in the output mode by decoding the signal output from the second ternary counter 52. It consists of. Here, the selection signal (OA) is a selection signal for operating the first memory unit 21 in the output mode, and the selection signal (OB) is a selection signal for operating the second memory unit 22 in the output mode. The selection signal (OC) is a selection signal for operating the third memory unit 23 in the output mode, and the selection signal (OC) is always output initially.
[0046]
The comparison unit 43 includes a first AND gate 53 that outputs a logical product of the selection signal (OA) of the second selection unit 46 and the selection signal (IB) of the first selection unit 41, and the selection of the second selection unit 46. A second AND gate 54 that outputs a logical product of the signal (OB) and the selection signal (IC) of the first selection unit 41, the selection signal (OC) of the second selection unit 46, and the selection of the first selection unit 41 A third AND gate 55 for performing an AND operation on the signal (IA) and outputting it, and a NOR gate for performing an AND operation on the output signals of the first, second and third AND gates 53, 54 and 55 and inverting and outputting them. 56, and a fourth AND gate 57 that performs an AND operation on the output of the NOR gate 56 and the output of the 1024 counter 45 and outputs the result as a clock signal of the second selection unit 46.
[0047]
The operation of the data driving device of the liquid crystal display device according to the second embodiment of the present invention thus configured will be described below.
[0048]
The operation of the data driver of the second embodiment of the present invention is the same as the operation of the first embodiment of the present invention. That is, three memory units are provided, and each memory unit is rotated in the input mode, the holding mode, and the output mode. The difference between the time required to record one line of the video signal with the VGA module and the time required to read one line of the recorded video signal with the XGA module (the speed of the XGA module is more If the memory to be read is in the write mode (input mode), the video signal data recorded in the previous memory is once again used. Operates to multiplex-scan using the read method.
[0049]
A specific operation of the control unit 25 that controls such an operation will be described below.
[0050]
First, in the first selection unit 41, the first ternary counter 52 counts the horizontal synchronization signal of the input VGA (640 × 480) video signal, and the first decoder 51 decodes the first ternary counter 52 to decode the first synchronization signal. The selection signals (IA, IB, IC) are output so that the VGA video signal is repeatedly input line by line in the order of the memory unit 21, the second memory unit 22, and the third memory unit 23. This process is repeated for one vertical period, and is initialized each time a vertical synchronizing signal is input.
[0051]
The PLL unit 44 converts the horizontal synchronization signal of the input VGA video signal to 1024 clocks (XGA data drive clock). Multiplication To output the dot clock (ICLK). This is because 640 VGA video signals are sampled during one horizontal synchronization period, but 1024 samples are required for XGA video signals.
[0052]
The variable oscillator 42 oscillates 768 pulse signals for one vertical synchronization period using the vertical synchronization signal (IV-sync) of the input VGA video signal as a reset signal, and outputs it as a gate pulse. That is, the VGA video signal should oscillate 468 pulses during one vertical synchronization period, and 768 pulses should be oscillated during one vertical synchronization period to display the XGA video signal. The data is read at the memory selected as the output mode. The 1024 counter 45 counts the signal (OCLK) output from the variable oscillating unit 42 by a 1024-ary number, and outputs it as a horizontal synchronization signal (OH-sync) necessary for display on the panel of the XGA module.
[0053]
The comparison unit 43 compares the selection signal (IA, IB, IC) of the first selection unit 41 with the selection signal (OA, OB, OC) of the second selection unit 46, and compares the signal (OA) with the signal (IB ) Are simultaneously selected, or the signal (OB) and the signal (IC) are simultaneously selected, or the signal (OC) and the signal (IA) are simultaneously selected. (OH-sync) is not output, and other than that, the signal (OH-sync) output from the 1024 counter 45 is output to the second selection unit 46. That is, when the signal (OA) and the signal (IB) are simultaneously selected, the first AND gate 53 outputs a “high” signal, and when the signal (OB) and the signal (IC) are simultaneously selected, the second AND gate is output. When the signal (OC) and the signal (IA) are simultaneously selected, the third AND gate 55 outputs a “high” signal. When a “high” signal is output from the first, second, and third AND gates, the NOR gate 56 outputs a “low” signal, so that no clock signal is input to the second selection unit 46. Similarly to the first selection unit, the second selection unit 46 rotates the third memory unit 23, the first memory unit 21, and the second memory unit 22 by the pulse signal input to the clock end and sets the output mode. A selection signal is output to be operated.
[0054]
As described above, the control unit 25 initially selects the first memory unit as the input mode, selects the third memory unit as the output mode, and records one line of the VGA video signal in the first memory unit. When the input mode of the first memory unit is completed, the second memory unit is selected as the input mode and the first memory unit is selected as the output mode. At this time, one line of video signal is recorded in the memory at the speed of the VGA resolution in the input mode, and one line of data recorded at the speed of the XGA resolution is read out in the output mode. Therefore, the output mode is faster than the input mode. proceed.
[0055]
At this time, since one memory unit cannot be selected as the input mode and the output mode at the same time, the first memory unit is again selected as the output mode while the second memory unit is selected as the input mode. Thereafter, when the input mode of the second memory unit is completed, the third memory unit is selected as the input mode, and the second memory unit is selected as the output mode. Similarly, when the output mode of the second memory unit is completed before the completion of the input mode of the third memory unit, the second memory unit is again selected as the output mode. Through such control, five lines of the VGA video signal are multiplexed and scanned by the eight XGA video signal modules.
[0056]
【The invention's effect】
The data driving device and driving method for the liquid crystal display device of the present invention as described above have the following effects.
[0057]
First, the circuit configuration required for the multiple scan is relatively simple.
[0058]
Second, when the data driving device of the present invention is attached to the LCD panel, video signals of various resolutions can be multiplexed and scanned without adding a separate circuit.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram of a data driving circuit of a conventional liquid crystal display device.
FIG. 2 is a detailed configuration diagram of a 192 × 6 bit 2-line latch unit of FIG. 1;
FIG. 3 is a configuration block diagram of a data driving circuit of the liquid crystal display device according to the first embodiment of the present invention.
4 is a detailed configuration diagram of a latch unit in FIG. 3. FIG.
FIG. 5 is a detailed configuration diagram of a control unit in FIG. 3;
6 is a circuit configuration diagram of a comparison unit in FIG. 5;
FIG. 7 is an explanatory diagram for explaining a multi-scan operation of the data driver of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 8 is a conceptual explanatory diagram of a data driving device of a liquid crystal display device according to a second embodiment of the present invention.
FIG. 9 is a configuration block diagram of a data driving circuit of a liquid crystal display device according to a second embodiment of the present invention.
FIG. 10 is a detailed circuit diagram of a control unit in FIG. 9;
[Explanation of symbols]
11 Shift register
12 Latch part
12a, 12b, 12c latch
13 Digital / analog converter
14 Data output section
15 Control unit
16, 41 1st selection part
17, 44 PLL section
18, 42 Variable oscillator
19, 43 Comparison part
19a, 19b, 19c NAND gate
19d, 19e, 53, 54, 55, 57 AND gate
20, 46 Second selection unit
21, 22, 23 Memory unit
24 Output selector
25 Control unit
26, 28, 30 memory
27, 29, 31 Multiplexer
45, 52, 58 counter
51, 59 decoder
56 NOR gate
60, 61, 62 Inverter
63, 64, 65 OR gate

Claims (14)

A shift register that shifts and outputs a carry input / output signal;
First, second, and third latches are provided, and R, G, and B video signal data input from the outside synchronized with the carry input / output signal output from the shift register are sequentially stored or stored. A latch unit that holds the held data or outputs the held video signal data,
A digital / analog converter that converts the video signal data output from the latch unit into an analog signal based on an external POL signal;
A data output unit for outputting an analog video signal output from the digital / analog conversion unit to the LCD panel based on the POL signal;
A control unit for controlling the operation of the three latches of the latch unit so that the data input and the data output are not operated by the same latch;
A data driving device for a liquid crystal display device. The control unit outputs a selection signal for selecting a latch operated as a data latch mode among the three latches of the latch unit;
A PLL section that divides the horizontal sync signal of the input video signal into the number of lines of the corresponding LCD module and outputs a dot clock;
A variable oscillation unit that outputs a gate start pulse of the number of scan lines of the LCD module during one vertical synchronization period;
A comparison unit for comparing the data output mode and the data latch mode so as not to occur simultaneously in one latch in the latch unit;
A second selection unit that selects a latch operated as a data output mode among the three latches of the latch unit, based on a signal output from the comparison unit;
2. The data driving device for a liquid crystal display device according to claim 1, further comprising:   The first selection unit repeatedly uses the horizontal synchronization signal of the input video signal as a clock signal, the vertical synchronization signal as a clear and load signal, and the latch mode is selected in order from the first latch to the third latch. 3. The data driving device for a liquid crystal display device according to claim 2, comprising a rotator that outputs a selection signal.   The second selection unit selects the data output mode in the order of the third latch, first latch, and second latch, using the output signal of the comparison unit as the clock signal, the vertical synchronization signal of the input video signal as the clear and load signal, The data driving device of a liquid crystal display device according to claim 2, wherein the data driving device comprises a rotator that repeatedly outputs a selection signal. The comparison unit performs an AND operation on the first latch mode selection signal (IN A) output from the first selection unit and the third output mode selection signal (OUT C) output from the second selection unit. First NAND gate that inverts and outputs,
The second latch mode selection signal (IN B) output from the first selection unit and the first output mode selection signal (OUT A) output from the second selection unit are ANDed and output. A second NAND gate to
The third latch mode selection signal (IN C) output from the first selection unit and the second output mode selection signal (OUT B) output from the second selection unit are ANDed and output. A third NAND gate to
A first AND gate that outputs a logical product of signals output from the first, second, and third NAND gates;
A second AND gate that performs an AND operation on the output signal of the first AND gate and the output signal of the variable oscillation unit and outputs the logical product to the second selection unit;
3. The data driving device for a liquid crystal display device according to claim 2, further comprising: First, second, and third memory units that record one line signal of a video signal input based on external control at a corresponding address or read and output a recorded signal;
An output selection unit that selects and outputs only one output signal among the video signals output from the first, second, and third memory units;
Each of the first, second, and third memory units operates as an input mode, the other one operates as a holding mode, and the other one operates as an output mode. A control unit that controls writing and reading of the second and third memory units and controls the output of the output selection unit;
With
The first , second and third memory units are
A multiplexer for outputting one of the read clock and the write clock based on the control signal of the controller,
An OR gate that outputs the logical input / output selection signal of the corresponding memory, and
An inverter for inverting the input selection signal of the control unit;
An output of the multiplexer as an address clock, an output of the OR gate as an address clear signal, a selection signal of the control unit is input via the inverter, and a memory for reading or writing based on control of the control unit,
The data driving device for a liquid crystal display device according to claim Rukoto equipped with.   The output selection unit is configured by three state buffers so as to buffer and output the data output from each of the first, second, and third memory units based on the control of the control unit. 7. The data driving device for a liquid crystal display device according to claim 6, wherein: The control unit is configured to output a selection signal (IA, IB, IC) so that one of the first, second, and third memory units can be operated as an input mode; and
A PLL section that divides the horizontal sync signal of the input video signal into the number of lines of the corresponding LCD module and outputs a dot clock;
A variable oscillation unit that outputs a gate start pulse of the number of scan lines of the LCD module during one vertical synchronization period;
A vertical synchronization signal counter that counts the number of lines of the corresponding LCD module and outputs the clock signal output from the variable oscillation unit as a vertical synchronization signal of the LCD panel;
Of the memory units, a comparison unit for comparing so that one memory unit is not operated as an input mode and an output mode at the same time;
A second selection unit that outputs a selection signal (OA, OB, OC) so that one of the first, second, and third memory units operates as an output mode;
7. The data driving device for a liquid crystal display device according to claim 6, further comprising: The first selection unit is a ternary counter that performs ternary counting using the vertical synchronizing signal of the input video signal as a reset signal and the horizontal synchronizing signal as a clock signal,
A decoder that decodes a signal output from the ternary counter and outputs a selection signal (IA, IB, IC) so that one of the three memory units is operated as an input mode;
9. The data driving device for a liquid crystal display device according to claim 8 , comprising: 9. The data of the liquid crystal display device according to claim 8 , wherein the first selection unit outputs a selection signal so as to repeatedly operate in the input mode in order from the first memory unit to the third memory unit. Drive device. The second selection unit, the vertical synchronization signal of the input video signal as a reset signal, the output signal of the comparison unit as a clock signal, a ternary counter that performs ternary counting,
A decoder for decoding a signal output from the ternary counter and outputting a selection signal (OA, OB, OC) so that one of the three memory units is operated as an output mode;
9. The data driving device for a liquid crystal display device according to claim 8 , comprising: The second selection unit, the third memory unit, the first memory unit, in the order of the second memory portion, so as to operate as iteratively output mode, according to claim 8, characterized in that for outputting a selection signal Data driving device for liquid crystal display device. The comparison unit includes a first AND gate that performs a logical AND operation on the first memory unit selection signal (OA) of the second selection unit and the second memory unit selection signal (IB) of the first selection unit,
A second AND gate that outputs a logical product of the second memory unit selection signal (OB) of the second selection unit and the third memory unit selection signal (IC) of the first selection unit;
A third AND gate that performs a logical AND operation on the third memory unit selection signal (OC) of the second selection unit and the first memory unit selection signal (IA) of the first selection unit; and
A NOR gate that inverts the output signals of the first, second, and third AND gates by performing a logical operation;
A fourth AND gate that performs an AND operation on the output of the NOR gate and the output of the vertical synchronization signal counter and outputs the AND signal as the clock signal of the second selection unit;
9. The data driving device for a liquid crystal display device according to claim 8 , further comprising: In a data driving method of a liquid crystal display device that includes first, second, and third memory units and displays video signals having different resolutions,
The input mode is set to be repeatedly selected in the order from the first memory to the third memory, and the output mode is set to be repeatedly selected in the order from the third memory to the first and second memories. Stages,
The second stage in which the memory previously selected as the output mode is selected again as the output mode whenever the memory operating as the input mode should be selected as the output mode due to the difference between the input speed and the output speed. When,
A third step of repeating the above process during the vertical synchronization period of the input video signal;
A data driving method for a liquid crystal display device.

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