JP4032785B2 - Image processing apparatus and method, recording medium, and program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus and method, a recording medium, and a program. For example, the present invention relates to an image processing apparatus and method, a recording medium, and a program suitable for converting an interlaced video signal into a progressive video signal. .
[0002]
[Prior art]
Video signals from television broadcasts, video signals recorded on recording media such as video cassettes and DVDs (Digital Versatile Discs), etc. are interlaced in which ODD field images and EVEN field images are alternately arranged.
[0003]
A video signal in which frame images having a vertical resolution twice as large as that of a field image are continuously arranged with respect to the interlace method is referred to as a progressive method.
[0004]
Conventionally, for the purpose of displaying high-quality video with higher vertical resolution, an interlace video signal (hereinafter referred to as an interlace video signal) is converted into a progressive video signal (hereinafter referred to as a progressive video signal). There are television receivers, DVD players, and the like that are displayed after being converted to (describe).
[0005]
FIG. 1 shows a conventional circuit for converting an interlace video signal into a progressive video signal (in other words, converting a field image into a frame image) mounted on such a television receiver or DVD player (hereinafter referred to as a frame image). , Described as a first conventional circuit).
[0006]
In the first conventional circuit, the field image F input from the input terminal 1 _t Is supplied to the field memory 2 and the motion vector detection circuit 5. The field memory 2 stores the input field image F _t Is delayed by one field period and output to the intra-field interpolation circuit 3 and the field memory 4. Hereinafter, field image F _t Field image one field before the field image F _t-1 Is described.
[0007]
The intra-field interpolation circuit 3 receives the input field image F _t-1 (Eg, field image F _t-1 If is an ODD field image, it points to the EVEN line. The interpolated field image F ′ is obtained by interpolating the pixels of the interpolation line using the pixels of the existing line. _t-1 Is output to the mixing circuit 8. The interpolation method is, for example, the field image F _t-1 Is an ODD field image, the average value of two pixels of the ODD line existing above and below the EVEN line as an interpolation line is applied.
[0008]
The field memory 4 stores the input field image F _t-1 Is delayed by one field period and output to the motion vector detection circuit 5 and the horizontal / vertical movement circuit 6. Hereinafter, field image F _t Field image before two fields, field image F _t-2 Is described.
[0009]
The motion vector detection circuit 5 uses a block matching method to generate a field image F that is spaced by the input two field periods. _t , F _t-2 The inter-frame motion vector of the subject on the screen is calculated and output to the horizontal / vertical moving circuit 6 together with the block difference value indicating the reliability of the calculated inter-frame motion vector. The motion vector detection circuit 5 also outputs a block difference value indicating the reliability of the inter-frame motion vector to the mixture ratio determination circuit 7.
[0010]
The horizontal / vertical moving circuit 6 receives the field image F input from the field memory 4 by ½ of the inter-frame motion vector input from the motion vector detection circuit 5 (that is, the motion vector corresponding to one field period). _t-2 Are translated and output to the mixing circuit 8.
[0011]
Based on the block difference value indicating the reliability of the inter-frame motion vector input from the motion vector detection circuit 5, the mixing ratio determination circuit 7 interpolates the interpolated field image F ′ in the mixing circuit 8. _t-1 Field image F translated _t-2 And the mixing ratio of the block unit of the pixel located at the same coordinate is determined and output to the mixing circuit 8. For example, when it can be determined that the reliability of the inter-frame motion vector is high based on the block difference value, the field image F _t-2 Are mixed, and the interpolated field image F ′ is mixed. _t-1 The mixing ratio is determined so that the ratio of the pixels to be mixed is reduced. On the other hand, if it can be determined that the reliability of the motion vector is low, the field image F _t-2 The proportion of the mixed pixels is small, and the interpolated field image F ′ _t-1 The mixing ratio is determined so that the ratio of mixing the pixels increases.
[0012]
The mixing circuit 8 is based on the mixing ratio input from the mixing ratio determination circuit 7 and interpolated field image F ′. _t-1 Field image F translated _t-2 By mixing pixels located at the same coordinates with the field image F _t-1 Is generated and output to the double speed conversion circuit 9. The double speed conversion circuit 9 receives the field image F output from the field memory 2. _t-1 And the field image F input from the mixing circuit 8. _t-1 Are alternately output at a horizontal scanning period twice that at the time of input, so that a frame image (sequentially scanned image) H is output. _t-1 And output to the subsequent stage via the output terminal 10.
[0013]
Next, problems of the first conventional circuit shown in FIG. 1 will be described. In the first conventional circuit, the field image F _t , F _t-2 The inter-frame motion vector of the frame image F is detected. _t-1 For example, if the movement of the subject is fast enough to jump over adjacent blocks within one frame period, the generated frame image has degraded image quality. May occur.
[0014]
For example, the field images F shown in FIGS. 2A to 2C, respectively. _t-2 To F _t Field image F _t-2 , The circular object in which the block (2-b) is present is the field image F. _t-1 Moves to block (2-c) and field image F _t In the case of moving to the block (2-d), the field image F _t-1 The inter-frame motion vector corresponding to the block (2-c) of the field image F _t-2 Block (2-c) and field image F _t Therefore, in this case, the inter-frame motion vector of the block (2-c) is detected as 0 with high reliability.
[0015]
Therefore, the field image F output from the mixing circuit 8 _t-1 The interpolation line corresponding to the field image F which is not substantially translated from the horizontal vertical movement circuit 6 is translated. _t-2 Frame image H output from the double-speed conversion circuit 9 since the pixels are mixed at a high rate. _t-1 As shown in FIG. 3, there is a problem that a horizontal gap is generated in the moving circular object.
[0016]
As a method for solving such a problem that may occur when the moving speed of the subject is high, for example, there is a circuit as shown in FIG. 4 (hereinafter referred to as a second conventional circuit).
[0017]
In the second conventional circuit, the field image F input from the input terminal 21 _t Is supplied to the intra-field interpolation circuit 21, the vertical filter 22, the field memory 23, and the double speed conversion circuit 29.
[0018]
The intra-field interpolation circuit 21 receives the input field image F _t The interpolated field image F ′ is obtained by interpolating the pixels of the interpolated line using the pixels of the existing line. _t Is output to the mixing circuit 8. The interpolation method is, for example, the field image F _t Is an ODD field image, the average value of the pixels d0 and d2 of the ODD line existing above and below is applied as the pixel d1 of the EVEN line that is the interpolation line.
[0019]
The vertical filter 22 receives the input field image F _t More specifically, as shown in FIG. 5A, for example, as shown in FIG. _t The pixels on the horizontal line (line 0 to line 4 in the figure) that do not actually exist are weighted and averaged (for example, upper pixel × 3/4 + lower pixel × 1/4) on the pixels existing above and below the horizontal line. And is output to the motion vector detection circuit 25.
[0020]
The field memory 23 stores the input field image F _t Field image F delayed by one field period _t-1 Is output to the vertical filter 24 and the horizontal / vertical moving circuit 26.
[0021]
The vertical filter 24 receives the input field image F _t-1 For example, as shown in FIG. 5A, the field image F is filtered in the vertical direction. _t-1 The pixels on the horizontal line (line 0 to 4 in the figure) that do not actually exist are weighted and averaged (for example, upper pixel × 1/4 + lower pixel × 3/4) on the pixels existing above and below the horizontal line. And is output to the motion vector detection circuit 25.
[0022]
The motion vector detection circuit 25 uses the block matching method to filter the field image F that has been filtered in the vertical direction. _t , F _t-1 The inter-field motion vector of the subject on the screen is calculated and output to the horizontal / vertical moving circuit 26 together with the block difference value indicating the reliability of the calculated inter-field motion vector. The motion vector detection circuit 25 also outputs a block difference value indicating the reliability of the inter-frame motion vector to the mixture ratio determination circuit 27.
[0023]
The horizontal / vertical movement circuit 26 applies only the inter-field motion vector input from the motion vector detection circuit 5 to the field image F input from the field memory 23. _t-1 Are translated and output to the mixing circuit 28.
[0024]
Based on the block difference value indicating the reliability of the inter-field motion vector input from the motion vector detection circuit 25, the mixing ratio determination circuit 27 interpolates the interpolated field image F ′ in the mixing circuit. _t Field image F translated _t-1 And the mixing ratio of the block unit of the pixel located at the same coordinate is determined and output to the mixing circuit 8. For example, when it can be determined that the reliability of the inter-field motion vector is high based on the block difference value, the field image F _t-1 Are mixed, and the interpolated field image F ′ is mixed. _t The mixing ratio is determined so that the ratio of the pixels to be mixed is reduced. Conversely, if it can be determined that the reliability of the field motion vector is low, the field image F _t-1 The proportion of the mixed pixels is small, and the interpolated field image F ′ _t The mixing ratio is determined so that the ratio of mixing the pixels increases.
[0025]
The mixing circuit 28 is based on the mixing ratio input from the mixing ratio determination circuit 7 and interpolated field image F ′. _t Field image F translated _t-1 By mixing pixels located at the same coordinates with the field image F _t Are generated and output to the double speed conversion circuit 29. The double speed conversion circuit 29 receives the field image F from the input terminal 21. _t And a field image F input from the mixing circuit 28. _t By alternately outputting the interpolation line corresponding to the image with a horizontal scanning period of 2 times, a frame image (sequentially scanned image) H _t And output to the subsequent stage via the output terminal 30.
[0026]
As described above, in the second conventional circuit, the field image F _t , F _t-1 Is detected as a field image F. _t-1 For example, it is possible to detect a motion vector corresponding to the movement of a subject as fast as it moves over an adjacent block within one frame period. Is possible. However, the field image F filtered in the vertical direction _t , F _t-1 Based on the above, there is a possibility that the vertical component of the motion vector is erroneously detected due to the detection of the inter-field motion vector.
[0027]
This will be specifically described. For example, when a subject having a horizontal line pattern with a width of 2 lines is present in a stationary state, the field image F as shown in FIG. 5A. _t-1 The lower side of the horizontal line pattern appears in the field image F _t A state in which the upper side of the horizontal line pattern appears (hereinafter referred to as phase 1) and a field image F as shown in FIG. _t-1 The upper side of the horizontal line pattern appears in the field image F _t In this state, the lower side of the horizontal line pattern appears (hereinafter referred to as phase 2). In addition, the numerical value (100, 200, etc.) beside each pixel indicates the signal level of each pixel.
[0028]
In phase 1, the vertically filtered field images F output from the vertical filters 22 and 24, respectively. _t , F _t-1 Is as shown in FIG. 5B.
[0029]
That is, for example, the field image F _t-1 The pixel of line 1 is calculated as 125 (= the actual upper pixel (200) × 1/4 + the actual lower pixel (100) × 3/4), and the field image F _t-1 The pixel of line 2 is calculated as 175 (= the actual upper pixel (100) × 1/4 + the actual lower pixel (200) × 3/4), and the field image F _t-1 The pixel of line 3 is calculated as 200 (= the actual upper pixel (200) × 1/4 + the actual lower pixel (200) × 3/4).
[0030]
For example, the field image F _t The pixel of line 1 is calculated as 125 (= the actual upper pixel (100) × 3/4 + the actual lower pixel (200) × 1/4), and the field image F _t The pixel of line 2 is calculated as 200 (= the actual upper pixel (200) × 3/4 + the actual lower pixel (200) × 1/4), and the field image F _t The pixel of line 3 is calculated as 200 (= the actual upper pixel (200) × 3/4 + the actual lower pixel (200) × 1/4).
[0031]
Similarly, in phase 1, the vertically filtered field images F output from the vertical filters 22 and 24, respectively. _t , F _t-1 Is as shown in FIG. 6B.
[0032]
That is, for example, the field image F _t-1 The pixel of line 1 is calculated as 125 (= the actual upper pixel (200) × 1/4 + the actual lower pixel (100) × 3/4), and the field image F _t-1 The pixel of line 2 is calculated as 175 (= the actual upper pixel (100) × 1/4 + the actual lower pixel (200) × 3/4), and the field image F _t-1 The pixel of line 3 is calculated as 200 (= the actual upper pixel (200) × 1/4 + the actual lower pixel (200) × 3/4).
[0033]
For example, the field image F _t The pixel of line 1 is calculated as 175 (= the actual upper pixel (200) × 3/4 + the actual lower pixel (100) × 1/4). _t The pixel of line 2 is calculated as 125 (= the actual upper pixel (100) × 3/4 + the actual lower pixel (200) × 1/4), and the field image F _t The pixel of line 3 is calculated as 200 (= the actual upper pixel (200) × 3/4 + the actual lower pixel (200) × 1/4).
[0034]
Here, the field image F filtered in the vertical direction _t Considering the case of using the block matching method with three lines (line 1 to line 3) as one block, in phase 1, the field image F _t As a block having the highest correlation with three lines (line 1 to line 3) of the field image F _t-1 Line 1 to line 3 are detected. Therefore, in phase 1, the vertical component of the inter-field motion vector of the block is detected as 0 without being erroneously detected.
[0035]
On the other hand, in phase 2, the field image F _t As a block having the highest correlation with three lines (line 1 to line 3) of the field image F _t-1 Line 0 to line 2 are detected. Therefore, in phase 2, it is not detected as a vertical component of the inter-field motion vector of the block, and is erroneously detected.
[0036]
[Problems to be solved by the invention]
As a method for solving such a problem of the second conventional circuit, for example, Japanese Patent Application Laid-Open No. Hei 8-163573 discloses that a field vector is detected after detecting an inter-field motion vector for the purpose of use in image data compression processing. There is a technology that improves the accuracy of motion vector detection (hereinafter referred to as the prior application technology) by further detecting inter-frame vectors centered on the movement position obtained in the inter-motion vector detection process. To do.
[0037]
However, the method of detecting both the inter-field motion vector and the inter-frame motion vector as in the prior application technique has a problem that it takes time for processing and the circuit scale increases.
[0038]
In the prior application technique, when an image including a caption moving horizontally on the screen is processed, there is a problem that image quality deterioration is conspicuous.
[0039]
The present invention has been made in view of such a situation, and when converting an interlaced video signal to a progressive video signal, Picture An object of the present invention is to prevent image quality deterioration of an image including a caption moving horizontally on a screen.
[0040]
[Means for Solving the Problems]
The image processing apparatus according to the present invention includes, among the continuous first to third field images constituting the interlaced video signal, Vertically filtered Detect an inter-field motion vector in units of blocks corresponding to the second and third field images In addition, the inter-field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images is detected. Inter-field motion vector detecting means, horizontal moving means for moving the first field image in the horizontal direction based on the inter-field horizontal motion vector, and the first field image moved by the horizontal moving means When Third field image With Limited to the horizontal direction of the corresponding block unit Horizontal travel Detect Horizontal travel Detection means; a first evaluation value indicating the reliability of the inter-field motion vector; Horizontal travel Comparing means for comparing the second evaluation value indicating the reliability of If the comparison result indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as the final motion vector, and the comparison result of the comparison unit is If the amount of horizontal movement does not indicate that it is more reliable than the inter-field motion vector, the inter-field motion vector is And determining means for determining a final motion vector.
[0041]
The comparison unit may count the number of horizontal motion blocks for each line, offset the first evaluation value corresponding to the number of horizontal motion blocks, and then compare with the second evaluation value. it can.
[0042]
The horizontal moving means may include one or more buffer memories for storing pixels for one line, and address generating means for generating a write address and a read address of the buffer memory, and the address generating means In addition to generating a serial value as a write address, a read address can be generated by adding a value obtained by doubling the inter-field horizontal motion vector and a predetermined offset value to the generated write address.
[0043]
The image processing apparatus according to the present invention translates the second field image based on the intra-field interpolation means for generating the pixels of the interpolation line corresponding to the third field image by intra-field interpolation and the final motion vector. It may further include translation means and mixing means for mixing the pixels of the interpolation line generated by the intra-field interpolation means with corresponding pixels of the second field image translated by the translation means.
[0044]
The image processing apparatus according to the present invention includes a horizontal edge detecting unit that detects a horizontal edge existing in the third field image, and a horizontal edge detecting unit among the pixels of the second field image translated by the parallel moving unit. Correction means for correcting pixels adjacent to the detected horizontal edge may be further included.
[0045]
The image processing apparatus of the present invention If the horizontal movement amount is not 0 and the 1/2 pixel motion flag that is valid only when the horizontal movement amount indicates that the reliability is higher than the inter-field motion vector, it is corrected. If the output of the means is selected as a pixel in block units of the interpolation line and the 1/2 pixel motion flag is not valid, the output of the mixing means is The image processing apparatus may further include selection means for selecting as a block unit pixel of the interpolation line.
[0046]
The image processing method of the present invention includes the first to third field images that constitute the interlaced video signal. Vertically filtered Detect an inter-field motion vector in units of blocks corresponding to the second and third field images In addition, the inter-field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images is detected. The first field image moved by the processing of the horizontal movement step, the horizontal movement step of moving the first field image in the horizontal direction based on the inter-field motion vector detection step, the inter-field horizontal direction motion vector When Third field image With Limited to the horizontal direction of the corresponding block unit Horizontal travel Detect Horizontal travel A detection step; a first evaluation value indicating the reliability of the inter-field motion vector; Horizontal travel And a comparison step for comparing the second evaluation value indicating the reliability of If the comparison result indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as the final motion vector, and the comparison result of the comparison unit is If the amount of horizontal movement does not indicate that it is more reliable than the inter-field motion vector, the inter-field motion vector is And a determining step for determining a final motion vector.
[0047]
The recording medium program according to the present invention includes the first through third field images constituting the interlaced video signal. Vertically filtered Detect an inter-field motion vector in units of blocks corresponding to the second and third field images In addition, the inter-field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images is detected. The first field image moved by the processing of the horizontal movement step, the horizontal movement step of moving the first field image in the horizontal direction based on the inter-field motion vector detection step, the inter-field horizontal direction motion vector When Third field image With Limited to the horizontal direction of the corresponding block unit Horizontal travel Detect Horizontal travel A detection step; a first evaluation value indicating the reliability of the inter-field motion vector; Horizontal travel And a comparison step for comparing the second evaluation value indicating the reliability of If the comparison result indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as the final motion vector, and the comparison result of the comparison unit is If the amount of horizontal movement does not indicate that it is more reliable than the inter-field motion vector, the inter-field motion vector is A decision step to determine the final motion vector; To cause a computer to execute a process including .
[0048]
The program according to the present invention includes the first to third field images constituting the interlaced video signal. Vertically filtered Detect an inter-field motion vector in units of blocks corresponding to the second and third field images In addition, the inter-field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images is detected. The first field image moved by the processing of the horizontal movement step, the horizontal movement step of moving the first field image in the horizontal direction based on the inter-field motion vector detection step, the inter-field horizontal direction motion vector When Third field image With Limited to the horizontal direction of the corresponding block unit Horizontal travel Detect Horizontal travel A detection step; a first evaluation value indicating the reliability of the inter-field motion vector; Horizontal travel And a comparison step for comparing the second evaluation value indicating the reliability of If the comparison result indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as the final motion vector, and the comparison result of the comparison unit is If the amount of horizontal movement does not indicate that it is more reliable than the inter-field motion vector, the inter-field motion vector is A decision step to determine the final motion vector; To cause a computer to execute a process including .
[0049]
The present invention In In the continuous first to third field images constituting the interlaced video signal, Vertically filtered Inter-field motion vectors in block units corresponding to the second and third field images are detected And an inter-field horizontal motion vector limited to the horizontal direction of the block unit corresponding to the second and third field images is detected, Based on the inter-field horizontal motion vector, the first field image is moved in the horizontal direction. Also, the moved first field image When Third field image With Limited to the horizontal direction of the corresponding block unit Horizontal travel And a first evaluation value indicating the reliability of the inter-field motion vector; Horizontal travel The second evaluation value indicating the reliability of the Indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as the final motion vector, and the comparison result is Is not more reliable than the inter-field motion vector, the inter-field motion vector is The final motion vector is determined.
[0050]
DETAILED DESCRIPTION OF THE INVENTION
A configuration example of a sequential scanning line conversion apparatus according to an embodiment of the present invention will be described with reference to FIG. This sequential scanning line converter converts an input interlaced video signal into a progressive video signal.
[0051]
The input terminal 41 is a field image F that constitutes an interlaced video signal that is sequentially input. _t Are supplied to the field memory 42, the vertical filter 44, the horizontal motion vector detection circuit 48, the intra-field interpolation circuit 49, the horizontal edge detection circuit 52, and the double speed conversion circuit 58.
[0052]
The field memory 42 receives a field image F from the input terminal 41. _t Are delayed by one field period, the field memory 43, the vertical filter 45, and Horizontal / vertical moving circuit 51 Output to. The field memory 43 is a field image F input from the field memory 42. _t-1 Is delayed by one field period and output to the horizontal movement circuit 47.
[0053]
The vertical filter 44 is the same as the vertical filter 22 in FIG. _t On the other hand, a vertical filtering process is performed and output to the motion vector detection circuit 46. Similarly, the vertical filter 45 receives the field image F from the field memory 42. _t-1 On the other hand, a vertical filtering process is performed and output to the motion vector detection circuit 46.
[0054]
The motion vector detection circuit 46 receives the vertically filtered field image F from the vertical filter 44. _t In addition, a reference block of horizontal P pixels and vertical Q lines centered on coordinates (x, y) is set, and a field image F filtered in the vertical direction from the vertical filter 45 is set. _t-1 A reference block having the same size as the base block and centering on the coordinates (x + mx, y + my) is set in the field image F filtered in the vertical direction by the block matching method. _t , F _t-1 The inter-field motion vector mv1 of the subject on the screen is detected. At this time, mx and my indicating the search range are changed in a range of −MX to + MX or −MY to + MY, respectively.
[0055]
The motion vector detection circuit 46 outputs a block difference value df1 indicating the reliability to the vector determination circuit 50 together with the detected inter-field motion vector mv1. Here, the block difference value refers to the integrated value of the difference between the corresponding pixels in the base block and the reference block, and the block difference value df1 refers to the minimum value.
[0056]
Further, the motion vector detection circuit 46 performs the vertical filtering of the field image F from the vertical filter 45. _t-1 A reference block having the same size as the base block and centering on the coordinates (x + mx, y) is set, and the field image F is filtered in the vertical direction by the block matching method. _t , F _t-1 The inter-field motion vector mv2 in the horizontal direction on the screen is detected and output to the horizontal movement circuit 47 and the vector determination circuit 50. Actually, it is not necessary to detect the inter-field motion vector mv2 again, and the result of the process of detecting the inter-field motion vector mv1 is used.
[0057]
The horizontal movement circuit 47 receives the field image F from the field memory 43. _t-2 Is moved by twice the horizontal inter-field motion vector mv2 from the motion vector detection circuit 46 and output to the horizontal motion vector detection circuit 48.
[0058]
FIG. 8 shows a configuration example of the horizontal movement circuit 47 when, for example, horizontal 8 pixels × vertical 4 lines are made into one block.
[0059]
The horizontal movement circuit 47 generates a write address and a read address based on the multiplication circuit 61 that doubles the horizontal inter-field motion vector mv2 input from the motion vector detection circuit 46, and the horizontal movement amount (2 · mv2). Address generation circuit 62, field image F input from the upper stage _t-1 The line buffers 64, 66, and 68 for delaying one line of pixels by one line period and outputting them to the subsequent stage, and the input one line of pixels to the read address generated by the address generation circuit 62 It is composed of buffer memories 63, 65, 67, and 69 for writing and reading in units of 8 horizontal pixels from the read address generated by the address generation circuit 62.
[0060]
FIG. 9 shows an example of a write address and a read address generated by the address generation circuit 62. For example, as shown in FIG. 9A, the write address incremented by 1 (in the case of FIG. 9, 13 to 13) is applied to each pixel of one line input to each of the buffer memories 63, 65, 67, and 69. 27) is generated. When the horizontal movement amount of the block of horizontal 8 pixels × vertical 4 lines sequentially input at this time is 0, −4, 4 as shown in FIG. 9B, a read address is generated based on the following equation.
Read address = write address + horizontal movement amount-offset value
[0061]
In the case of FIG. 9, write addresses 5 to 7, 4 to 11, and 20 to 23 are generated corresponding to the write addresses 13 to 27 generated by incrementing by one. However, in this case, the offset value is 8.
[0062]
In the horizontal movement circuit 47, the buffer memories 63, 65, 67 and 69 write pixels according to the read address generated by the address generation circuit 62, and then read the pixels according to the read address generated by the address generation circuit 62. , Field image F input from the field memory 43 _t-2 Can be moved quickly in the horizontal direction in units of blocks.
[0063]
Returning to FIG. The horizontal motion vector detection circuit 48 receives the field image F from the input terminal 41. _t In addition, a horizontal block centered at coordinates (x, y) is set as a reference block having P pixels and the vertical direction is Q lines, and the field image F moved in the horizontal direction is input from the horizontal movement circuit 47. _t-2 Set a reference block having the same size as the standard block and centered on coordinates (x + mx, y), and by block matching method, Horizontal movement amount dmv2 (hereinafter also referred to as inter-frame motion vector dmv2) Is detected. At this time, mx indicating the search range does not need to be varied in a wide range, and is varied in a range of, for example, about −3 to +3.
[0064]
Thus, setting the search range of mx to be a narrow range of about −3 to +3 not only reduces the circuit scale of the horizontal motion vector detection circuit 48 but also the inter-frame motion vector dmv2 limited in the horizontal direction. It is possible to suppress erroneous detection as a remarkably large value compared to the direction-to-field motion vector mv2.
[0065]
The horizontal motion vector detection circuit 48 outputs a block difference value df2 indicating the reliability along with the detected horizontal inter-frame motion vector dmv2 to the vector determination circuit 50.
[0066]
The intra-field interpolation circuit 49 receives the field image F from the input terminal 41. _t The interpolated field image F ′ is interpolated by using the pixels of the existing line corresponding to the interpolated line pixels. _t And output to the edge processing circuit 55. The interpolation method is, for example, the field image F _t Is an ODD field image, the average value of two pixels of the ODD line existing above and below the EVEN line as an interpolation line is applied.
[0067]
The vector determination circuit 50 selects one of the inter-field motion vector mv1 and the horizontal inter-field motion vector mv2 from the motion vector detection circuit 46 as a final inter-field motion vector and outputs it to the horizontal / vertical moving circuit 51. Then, one of the block difference values df1 and df2 is output as a correlation level signal to the mixing ratio determination circuit 53, and a 1/2 pixel motion flag is generated and output to the selector 56.
[0068]
FIG. 10 shows a configuration example of the vector determination circuit 50. In the vector determination circuit 50, the counting circuit 81 counts blocks (hereinafter referred to as horizontal motion blocks) in which a comparison result of a corresponding comparison circuit 89 (described later) is 0 among blocks (horizontal P pixels) on one line. To the holding circuit 83. The counting circuit 82 counts blocks (horizontal P pixels) existing on one line and outputs them to the holding circuit 85. The multiplication circuit 84 multiplies the number of horizontal motion blocks existing on one line by the predetermined number n and outputs the result to the comparison circuit 86. The comparison circuit 86 compares the value obtained by multiplying the number of horizontal motion blocks by a predetermined number n with the total number of blocks existing on one line held in the holding circuit 85, and compares the comparison result with the selector 87. Output to.
[0069]
The selector 87 outputs a predetermined offset value ofst1 or 0 to the addition circuit 88 based on the comparison result from the comparison circuit 86. Specifically, when the comparison result of the comparison circuit 86 is “the total number of blocks existing on one line is smaller”, a predetermined offset value ofst1 is output to the addition circuit 88 and the comparison circuit 86 compares If the result is not “the total number of blocks existing on one line is smaller”, 0 is output to the adder circuit 88.
[0070]
The adder circuit 88 adds the output of the selector 87 (predetermined offset value ofst1 or 0) to the block difference value df1 from the motion vector detection circuit 46, and outputs the result to the comparison circuit 89 as a block difference value df3. The comparison circuit 89 compares the block difference value df2 from the horizontal motion vector detection circuit 48 with the block difference value df3 from the addition circuit 88, and generates 1 when it is determined that the block difference value df2 is smaller. If it is not determined that the block difference value df2 is smaller, 0 is generated and output as a comparison result to the counting circuit 81, the selector 90, and the AND circuit 93.
[0071]
Based on the comparison result from the comparison circuit 89, the selector 90 uses the block difference value df <b> 1 from the motion vector detection circuit 46 or the block difference value df <b> 2 from the horizontal motion vector detection circuit 48 as a correlation level signal, and the mixture ratio determination circuit 53. Output to. Specifically, when the comparison result from the comparison circuit 89 is 1, the block difference value df2 is output as a correlation level signal, and when the comparison result from the comparison circuit 89 is 0, the block difference value df1 is output as the correlation level. Output as a signal. The selector 90 supplies the comparison result from the comparison circuit 89 to the selector 91.
[0072]
Based on the comparison result of the comparison circuit 89, the selector 91 supplies the inter-field motion vector mv1 or the horizontal inter-field motion vector mv2 from the motion vector detection circuit 46 as the final inter-field motion vector to the horizontal / vertical movement circuit 51. Output. Specifically, when the comparison result of the comparison circuit 89 is 1, Horizontal When the inter-field motion vector mv2 is output as the final inter-field motion vector and the comparison result of the comparison circuit 89 is 0, F The inter-field motion vector mv1 is output as the final inter-field motion vector.
[0073]
The mismatch determination circuit 92 determines whether or not the horizontal inter-frame motion vector dmv2 from the horizontal motion vector detection circuit 48 is 0. If the horizontal inter-frame motion vector dmv2 is not 0, 1 is ANDed. Output to the circuit 93. On the other hand, when the interframe motion vector dmv2 in the horizontal direction is 0, 0 is output to the AND circuit 93.
[0074]
The AND circuit 93 outputs the logical product of the comparison result from the comparison circuit 89 and the output from the mismatch determination circuit 92 to the selector 56 as a ½ pixel flag.
[0075]
That is, when the 1/2 pixel flag is 1, the horizontal inter-frame motion vector dmv2 is not 0, but is any of -3, -2, -1, 1, 2, and 3. If the horizontal inter-frame motion vector dmv2 is -3, -1, 1, or 3, the actual motion of the pixel between the corresponding fields is -1.5, -0.5, 0.5. Or 1.5, since the corresponding inter-field motion vector mv2 is calculated in integer units, there is a difference of 1/2 pixel between the inter-field motion vector mv2 and the actual motion. Become. When the 1/2 pixel flag is set to 1, this indicates that this shift has occurred.
[0076]
If the horizontal inter-frame motion vector dmv2 is −2 or 2, Horizontal There is no deviation between the inter-field motion vector mv2 and the actual motion, Horizontal Accuracy of inter-field motion vector mv2 But Since the pixel is considered to have fallen, the 1/2 pixel flag is set to 1.
[0077]
Returning to FIG. The horizontal / vertical moving circuit 51 receives the field image F from the field memory 42. _t-1 Are translated by the final inter-field motion vector from the vector determination circuit 50 and output to the mixing circuit 54.
[0078]
The horizontal edge detection circuit 52 receives the field image F from the input terminal 41. _t The side extending in the vertical direction of the subject (hereinafter referred to as a horizontal edge) is detected, and the coordinate information of the horizontal edge is output to the edge processing circuit 55 and the selector 56.
[0079]
FIG. 11 shows a configuration example of the horizontal edge detection circuit 52. The horizontal edge detection circuit 52 receives the input field image F. _t Among the total lines, two lines are sequentially shifted one line at a time to be processed.
[0080]
In the horizontal edge detection circuit 52, the pixels existing in the upper line of the two lines to be processed are sequentially input to the holding circuit 111 and the subtracting circuit 112, and the pixels existing in the lower line are input to the holding circuit 114 and the subtracting circuit. The signals are sequentially input to the circuit 115.
[0081]
The holding circuit 111 delays the pixels in the upper line sequentially input at a predetermined cycle by one cycle and outputs the delayed pixels to the subtractor circuit 112. The subtraction circuit 112 calculates a difference between two pixels that are input simultaneously (that is, two pixels adjacent in the upper line) and outputs the difference to the absolute value circuit 113. The absolute value circuit 113 outputs the absolute value of the difference between two adjacent pixels to the maximum value selection circuit 117.
[0082]
The holding circuit 114 delays the pixels in the lower line that are sequentially input at a predetermined period and outputs the pixels to the subtraction circuit 115 with a delay of one period. The subtraction circuit 115 calculates a difference between two pixels that are input simultaneously (that is, two pixels adjacent in the lower line) and outputs the difference to the absolute value circuit 116. The absolute value circuit 116 outputs the absolute value of the difference between two adjacent pixels to the maximum value selection circuit 117.
[0083]
The maximum value selection circuit 117 is the difference between the absolute value of the difference between two adjacent pixels in the upper line and the absolute value of the difference between two adjacent pixels in the lower line, which are simultaneously input from the absolute value circuits 113 and 116. Is selected and output to the holding circuit 118 and the determination circuit 119 as the right edge level ED_R. The holding circuit 118 delays the right edge level ED_R sequentially input from the maximum value selection circuit 117 at a predetermined period by one period, and outputs the delayed edge level ED_L to the determination circuit 119 as the left edge level ED_L.
[0084]
The determination circuit 119 compares the right edge level ED_R and the left edge level ED_L, which are simultaneously input from the maximum value selection circuit 117 and the holding circuit 118, with a predetermined edge determination threshold ed_th, and ED_R>ED_L> ed_th. When the determination is made, it is determined that there is an edge in the right direction in the middle of two adjacent pixels (a subject having a higher signal level on the right side than the middle of the two pixels). If it is determined that ED_L>ED_R> ed_th, it is determined that there is an edge in the left direction in the middle of two adjacent pixels (the edge of the subject having a higher signal level is on the left side of the middle of the two pixels).
[0085]
Further, the determination circuit 119 generates an edge flag indicating whether or not there is an edge between two adjacent pixels and an edge direction flag indicating the direction of the edge corresponding to the determination result to generate a coordinate information generation circuit. To 120.
[0086]
The coordinate information generation circuit 120 uses the field image F based on the edge flag and the edge direction flag input from the determination circuit 119. _t Are generated and output to the edge processing circuit 55 and the selector 56.
[0087]
Returning to FIG. The mixing ratio determination circuit 53 is based on the correlation level signal from the vector determination circuit 50 and interpolates the field image F ′ interpolated from the intra-field interpolation circuit 49 in the mixing circuit 54. _t And the translated field image F from the horizontal / vertical moving circuit 51. _t-1 And the mixing ratio of the block unit of the pixel located at the same coordinate as is determined and output to the mixing circuit 54.
[0088]
For example, as the correlation level signal (that is, the block difference value df1 or df2) is smaller, it can be determined that the reliability of the final inter-field motion vector calculated by the motion vector determination circuit 50 is higher. Translated field image F from horizontal / vertical moving circuit 51 _t-1 The ratio s for mixing the pixels of the pixel is large, and the interpolated field image F ′ _t The mixing ratio is determined so that the ratio (1-s) of the pixels to be mixed is reduced.
[0089]
Based on the mixing ratio from the mixing ratio determination circuit 53, the mixing circuit 54 interpolates the field image F ′ interpolated from the intra-field interpolation circuit 49. _t And the translated field image F from the horizontal / vertical moving circuit 51. _t-1 The pixel located at the same coordinate with (the field image F translated) _t-1 Pixel) × s + (interpolated field image F ′) _t Pixel) × (1−s), and outputs to the selector 56.
[0090]
The edge processing circuit 55 receives the horizontal edge coordinate information from the horizontal edge detection circuit 52 and the interpolated field image F ′ from the intra-field interpolation circuit 49. _t The translated field image F from the horizontal / vertical moving circuit 51 is _t-1 Among the pixels, the pixels adjacent to the horizontal edge are corrected and output to the selector 56.
[0091]
The processing of the edge processing circuit 55 will be specifically described with reference to FIG. For example, the edge processing circuit 55 includes a field image F from the intra-field interpolation circuit 49 as shown in FIG. 12A. _t (In fact, the interpolated field image F _t Of all the lines of 'and not the interpolation line) and the translated field image F from the horizontal / vertical moving circuit 51 _t-1 Is entered.
[0092]
Here, as shown in FIG. 12A, the coordinate information of the horizontal edge from the horizontal edge detection circuit 52 indicates that a horizontal edge exists so as to connect the boundary between the pixels Pe and Pd and the boundary between the pixels Po and Pp. The translated field image F _t-1 Of these pixels, the pixels Pi and Pj adjacent to the horizontal edge are replaced with the pixels PX and PY (FIG. 12B) generated using the neighboring pixels.
[0093]
Specifically, the average value of the four pixels of the pixel Pi, its upper and lower pixels Pc, Po, and its left adjacent pixel Ph is used for the pixel PX to be replaced with the pixel Pi located on the left side of the horizontal edge. . Further, an average value of four pixels of the pixel Pj, its upper and lower pixels Pd and Pp, and its right adjacent pixel Pk is used as the pixel PY to be replaced with the pixel Pj located on the right side of the horizontal edge.
[0094]
By such processing of the edge processing circuit 55, as shown in FIG. 12A, the translated field image F _t-1 Is field image F _t Even if the horizontal line has a jagged shape (in this case, the 1/2 pixel flag is set to 1 by the vector determination circuit 50), the jagged portion is shown in FIG. 12B. It will be blurred and inconspicuous. Therefore, image degradation such as subtitles moving in the horizontal direction on the screen is suppressed.
[0095]
Returning to FIG. The selector 56 receives, from the edge processing circuit 55, the block image whose half pixel flag is 1 from the vector determination circuit 50. The field image F that is translated and corrected in the vicinity of the horizontal edge. _t-1 On the other hand, for the block whose 1/2 pixel flag from the vector determination circuit 50 is 0, the corresponding block of the field image Ft-1 composed of the mixed pixels from the mixing circuit 54 Is used to output the field image F '' to the subsequent stage. _t-1 Is generated.
[0096]
The double speed conversion circuit 57 receives the field image F from the input terminal 41. _t And the field image F '' from the selector 56 _t-1 Are alternately output at a horizontal scanning period twice as long as that at the time of input, thereby generating a frame image (sequentially scanned image) H. _t And output to the subsequent stage via the output terminal 58.
[0097]
Next, conversion processing for converting an interlaced video signal into a progressive video signal by the progressive scanning line conversion apparatus of FIG. 7 will be described with reference to FIG. It is assumed that the field image constituting the interlaced video signal is sequentially input to the sequential scanning line conversion device via the input terminal 41.
[0098]
In step S1, the intra-field interpolation circuit 49 receives the field image F input through the input terminal 41. _t The interpolated field image F ′ is interpolated by using the pixels of the existing line corresponding to the interpolated line pixels. _t And output to the edge processing circuit 55.
[0099]
In step S2, the vertical filter 44 receives the field image F input via the input terminal 41. _t On the other hand, a vertical filtering process is performed and output to the motion vector detection circuit 46. The vertical filter 45 is a field image F input from the field memory 42. _t-1 On the other hand, a vertical filtering process is performed and output to the motion vector detection circuit 46.
[0100]
In step S <b> 3, the motion vector detection circuit 46 performs field image F on which the vertical filtering process has been performed. _t , F _t-1 The inter-field motion vector mv1 in the block unit is detected and output to the vector determination circuit 50 together with the block difference value df1 indicating the reliability. Further, the motion vector detection circuit 46 detects the inter-field motion vector mv2 in the horizontal direction and outputs it to the horizontal movement circuit 47 and the vector determination circuit 50.
[0101]
In step S 4, the horizontal movement circuit 47 receives the field image F input from the field memory 43. _t-2 Is moved by twice the horizontal inter-field motion vector mv2 input from the motion vector detection circuit 46 and output to the horizontal motion vector detection circuit 48. The horizontal motion vector detection circuit 48 receives the field image F input via the input terminal 41. _t And the field image F moved in the horizontal direction by the horizontal movement circuit 47. _t-2 The inter-frame motion vector dmv2 limited to the horizontal direction is detected and output to the vector determination circuit 50 together with the block difference value df2 indicating the reliability.
[0102]
In step S 5, the vector determination circuit 50 receives the inter-field motion vector mv 1 input from the motion vector detection circuit 46, the corresponding block difference value df 1, the horizontal inter-field motion vector mv 2, and the horizontal motion vector detection circuit 48. Is calculated based on the horizontal inter-frame motion vector dmv2 and the block difference value df2 corresponding thereto, and is output to the horizontal / vertical moving circuit 51, and the block difference value df1, One of df2 is output as a correlation level signal to the mixture ratio determination circuit 53, and a 1/2 pixel motion flag is generated and output to the selector 56.
[0103]
In step S6, the horizontal / vertical moving circuit 51 receives the field image F input from the field memory 42. _t-1 Are translated by the final inter-field motion vector input from the vector determination circuit 50 and output to the mixing circuit 54. The mixing circuit 54 is based on the mixing ratio from the mixing ratio determination circuit 53 and receives the interpolated field image F ′ input from the intra-field interpolation circuit 49. _t And the translated field image F input from the horizontal / vertical moving circuit 51. _t-1 Are mixed according to the mixture ratio determined by the mixture ratio determination circuit 53 and output to the selector 56.
[0104]
In step S6, the horizontal edge detection circuit 52 receives the field image F input via the input terminal 41. _t Is detected and the coordinate information is output to the edge processing circuit 55 and the selector 56. In step S 7, the edge processing circuit 55 receives the coordinate information of the horizontal edge from the horizontal edge detection circuit 52 and the interpolated field image F ′ from the intra-field interpolation circuit 49. _t The translated field image F from the horizontal / vertical moving circuit 51 is _t-1 Among the pixels, the pixels adjacent to the horizontal edge are corrected and output to the selector 56.
[0105]
In step S8, the selector 56, for the block whose 1/2 pixel flag from the vector determination circuit 50 is 1, is the field that is input from the edge processing circuit 55 and is translated and corrected for pixels near the horizontal edge. Image F _t-1 On the other hand, for the block in which the 1/2 pixel flag from the vector determination circuit 50 is 0, the field image Ft-1 including the mixed pixels input from the mixing circuit 54 is used. Field image F '' output to the subsequent stage using the corresponding block _t-1 Is generated.
[0106]
In step S 9, the double speed conversion circuit 57 receives the field image F input via the input terminal 41. _t And the field image F '' input from the selector 56 _t-1 Are alternately output at a horizontal scanning period twice as long as that at the time of input, thereby generating a frame image (sequentially scanned image) H. _t And output to the subsequent stage via the output terminal 58.
[0107]
As described above, the field image F constituting the interlaced video signal. _t Is the previous two field images F _t-1 , F _t-2 Based on the frame image H constituting the progressive video signal _t Is converted to
[0108]
Note that the edge processing circuit 55 in the sequential scanning line conversion apparatus shown in FIG. 7 receives the translated field image F input from the horizontal / vertical moving circuit 51. _t-1 All pixels adjacent to the horizontal edge are corrected, but the edge processing circuit 55 is inputted with the 1/2 pixel flag from the vector determination circuit 50 to the edge processing circuit 55. 55 is a translated field image F _t-1 Of these pixels, only the pixels belonging to the block whose 1/2 pixel flag is 1 and adjacent to the horizontal edge may be corrected. In this way, the processing amount by the edge processing circuit 55 can be reduced.
[0109]
Next, FIG. 14 shows another configuration example of the sequential scanning line conversion apparatus to which the present invention is applied. The difference from the configuration example shown in FIG. 7 is the arrangement of field memories 121 and 122 corresponding to the field memories 42 and 43 in FIG.
[0110]
In the configuration example of FIG. 14, the field image F from the input terminal 41. _t Is input to the field memory 121 and the horizontal movement circuit 123. Field image F from the field memory 121 _t-1 Are input to the vertical filter 44, the intra-field interpolation circuit 49, the horizontal edge detection circuit 52, the double speed conversion circuit 57, and the field memory 122. Field image F from the field memory 122 _t-2 Are input to the horizontal motion vector detection circuit 48, the horizontal / vertical movement circuit 51, and the vertical filter 45.
[0111]
The horizontal movement circuit 123 receives the field image F from the input terminal 41. _t Is moved by -2 times the horizontal inter-field motion vector mv2 from the motion vector detection circuit 46 and output to the horizontal motion vector detection circuit 48.
[0112]
The other constituent circuits are common and are given the same numbers, and the description thereof is omitted.
[0113]
In the case of the configuration example of FIG. 14, the field image F _t Frame image H one field period before _t-1 Is output as the processing result.
[0114]
Incidentally, the sequential scanning line conversion apparatus to which the present invention is applied can be realized by hardware, but can also be realized by software. When implemented by software, a general-purpose computer that can execute various functions by installing a computer that is built into dedicated hardware or installing various programs. Installed from a recording medium on a personal computer.
[0115]
FIG. 15 shows a configuration example of a personal computer that operates as a sequential scanning line converter by executing dedicated software.
[0116]
This personal computer includes a CPU (Central Processing Unit) 141. An input / output interface 145 is connected to the CPU 141 via the bus 144. A ROM (Read Only Memory 142 and a RAM (Random Access Memory) 143 are connected to the bus 144.
[0117]
The input / output interface 145 includes an operation input unit 146 including an input device such as a keyboard and a mouse for a user to input an operation command, a display including a CRT (Cathode Ray Tube) or an LCD (Liquid Crystal Display) for displaying a processing result. 147, a storage unit 148 including a hard disk drive for storing programs and various data, a communication unit 149 for communicating data etc. via a network represented by the Internet, and recording media such as magnetic disk 151 to semiconductor memory 154 On the other hand, a drive 150 for reading and writing data is connected.
[0118]
A program for causing this personal computer to execute an operation as a sequential scanning line converter is a magnetic disk 151 (including a flexible disk), an optical disk 152 (CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc)). To the hard disk drive supplied to the personal computer in a state stored in the semiconductor memory 154, read by the drive 150, and built in the storage unit 148. Installed. The program installed in the storage unit 148 is loaded from the storage unit 148 to the RAM 143 and executed in response to a command from the CPU 141 corresponding to a command from the user input to the operation input unit 146.
[0119]
In the present specification, the step of describing the program recorded in the recording medium is not limited to the processing performed in time series according to the described order, but is not necessarily performed in time series, either in parallel or individually. The process to be executed is also included.
[0120]
【The invention's effect】
As described above, according to the present invention, when an interlaced video signal is converted into a progressive video signal, Picture It is possible to suppress deterioration in image quality of an image including a caption moving horizontally on the surface.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a conventional circuit for converting an interlaced video signal into a progressive video signal.
FIG. 2 is a diagram for explaining problems of the conventional circuit of FIG. 1;
FIG. 3 is a diagram for explaining a problem of the conventional circuit of FIG. 1;
FIG. 4 is a block diagram illustrating an example of a conventional circuit that converts an interlaced video signal into a progressive video signal.
5 is a diagram for explaining problems of the conventional circuit of FIG. 4;
6 is a diagram for explaining a problem of the conventional circuit of FIG. 4;
FIG. 7 is a block diagram showing a first configuration example of a sequential scanning line conversion apparatus to which the present invention is applied.
8 is a block diagram showing a configuration example of the horizontal movement circuit 47 of FIG.
9 is a diagram for explaining an address generation circuit 62 of FIG. 8. FIG.
10 is a block diagram illustrating a configuration example of the vector determination circuit 50 of FIG.
11 is a block diagram illustrating a configuration example of a horizontal edge detection circuit 52 in FIG. 7;
12 is a diagram for explaining an edge processing circuit 55 in FIG. 7; FIG.
FIG. 13 is a flowchart illustrating conversion processing by a sequential scanning line conversion apparatus to which the present invention is applied.
FIG. 14 is a block diagram showing a second configuration example of a sequential scanning line conversion apparatus to which the present invention is applied.
FIG. 15 is a block diagram illustrating a configuration example of a personal computer that operates as a sequential scanning line conversion apparatus by executing predetermined software.
[Explanation of symbols]
42, 43 Field memory, 44, 45 Vertical filter, 46 Motion detection circuit, 47 Horizontal movement circuit, 48 Horizontal motion vector detection circuit, 49 Intra-field interpolation circuit, 50 Vector decision circuit, 51 Horizontal vertical movement circuit, 52 Horizontal edge detection Circuit, 53 mixing ratio determination circuit, 54 mixing circuit, 55 edge processing circuit, 56 selector, 57 double speed conversion circuit, 62 address generation circuit, 141 CPU, 151 magnetic disk, 152 optical disk, 153 magneto-optical disk, 154 semiconductor memory

Claims (9)

In an image processing apparatus for converting an interlaced video signal into a progressive video signal,
Of the consecutive first to third field image constituting the interlaced video signal, detects the inter-field motion vector of a block unit corresponding to the second and third field images filtered in the vertical direction Inter-field motion vector detection means for detecting an inter- field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images ;
Horizontal moving means for moving the first field image in the horizontal direction based on the inter-field horizontal motion vector;
A horizontal movement amount detection means for detecting a horizontal movement amount limited to the horizontal direction of the corresponding block unit of the first field image and the third field image moved by the horizontal movement means;
Comparison means for comparing a first evaluation value indicating the reliability of the inter-field motion vector and a second evaluation value indicating the reliability of the horizontal movement amount ;
If the comparison result of the comparison means indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as a final motion vector, A determination means for determining the inter-field motion vector as a final motion vector if the comparison result of the comparison means does not indicate that the horizontal movement amount is more reliable than the inter-field motion vector ; An image processing apparatus comprising: The comparison means counts the number of horizontal motion blocks for each line, offsets the first evaluation value corresponding to the number of horizontal motion blocks, and compares the first evaluation value with the second evaluation value. The image processing apparatus according to claim 1, wherein: The horizontal moving means includes
One or more buffer memories for storing pixels for one line;
Address generating means for generating a write address and a read address of the buffer memory,
The address generation means generates a serial value as the write address, and adds the read address by adding a value obtained by doubling the horizontal motion vector between fields and a predetermined offset value to the generated write address. The image processing apparatus according to claim 1, wherein the image processing apparatus is generated. Intra-field interpolation means for generating pixels of an interpolation line corresponding to the third field image by intra-field interpolation;
Translation means for translating the second field image based on the final motion vector;
And further comprising: mixing means for mixing the pixels of the interpolation line generated by the intra-field interpolation means with the corresponding pixels of the second field image translated by the translation means. Item 8. The image processing apparatus according to Item 1. Horizontal edge detection means for detecting a horizontal edge present in the third field image;
Correction means for correcting a pixel adjacent to the horizontal edge detected by the horizontal edge detection means among the pixels of the second field image translated by the translation means. The image processing apparatus according to claim 4. A 1/2 pixel motion flag that is valid only when the horizontal movement amount is not 0 and the horizontal movement amount indicates higher reliability than the inter-field motion vector is effective. In this case, the output of the correcting unit is selected as a pixel of the block of the interpolation line, and when the 1/2 pixel motion flag is not valid, the output of the mixing unit is selected as a pixel of the block of the interpolation line. The image processing apparatus according to claim 5, further comprising a selection unit. In an image processing method of an image processing apparatus for converting an interlaced video signal into a progressive video signal,
Of the consecutive first to third field image constituting the interlaced video signal, detects the inter-field motion vector of a block unit corresponding to the second and third field images filtered in the vertical direction An inter-field motion vector detecting step for detecting an inter- field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images ;
A horizontal movement step of moving the first field image in a horizontal direction based on the inter-field horizontal motion vector;
A horizontal movement amount detection step for detecting a horizontal movement amount limited to the horizontal direction of the corresponding block unit of the first field image and the third field image moved in the processing of the horizontal movement step;
A comparison step of comparing a first evaluation value indicating the reliability of the inter-field motion vector with a second evaluation value indicating the reliability of the horizontal movement amount ;
If the comparison result of the comparison step indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as a final motion vector, and A determination step of determining the inter-field motion vector as a final motion vector if the comparison result of the comparison means does not indicate that the horizontal movement amount is more reliable than the inter-field motion vector ; An image processing method comprising: A program for controlling an image processing apparatus that converts an interlaced video signal into a progressive video signal,
Of the consecutive first to third field image constituting the interlaced video signal, detects the inter-field motion vector of a block unit corresponding to the second and third field images filtered in the vertical direction An inter-field motion vector detecting step for detecting an inter- field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images ;
A horizontal movement step of moving the first field image in a horizontal direction based on the inter-field horizontal motion vector;
A horizontal movement amount detection step for detecting a horizontal movement amount limited to the horizontal direction of the corresponding block unit of the first field image and the third field image moved in the processing of the horizontal movement step;
A comparison step of comparing a first evaluation value indicating the reliability of the inter-field motion vector with a second evaluation value indicating the reliability of the horizontal movement amount ;
If the comparison result of the comparison step indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as a final motion vector, and A determination step of determining the inter-field motion vector as a final motion vector if the comparison result of the comparison means does not indicate that the horizontal movement amount is more reliable than the inter-field motion vector ;
A recording medium on which is recorded a program that causes a computer to execute a process including: A program for controlling an image processing apparatus that converts an interlaced video signal into a progressive video signal,
Of the consecutive first to third field image constituting the interlaced video signal, detects the inter-field motion vector of a block unit corresponding to the second and third field images filtered in the vertical direction An inter-field motion vector detecting step for detecting an inter- field horizontal motion vector limited to the horizontal direction in block units corresponding to the second and third field images ;
A horizontal movement step of moving the first field image in a horizontal direction based on the inter-field horizontal motion vector;
A horizontal movement amount detection step for detecting a horizontal movement amount limited to the horizontal direction of the corresponding block unit of the first field image and the third field image moved in the processing of the horizontal movement step;
A comparison step of comparing a first evaluation value indicating the reliability of the inter-field motion vector with a second evaluation value indicating the reliability of the horizontal movement amount ;
If the comparison result of the comparison step indicates that the horizontal movement amount is more reliable than the inter-field motion vector, the inter-field horizontal motion vector is determined as a final motion vector, and A determination step of determining the inter-field motion vector as a final motion vector if the comparison result of the comparison means does not indicate that the horizontal movement amount is more reliable than the inter-field motion vector ;
A program for causing a computer to execute a process including:

Images