JP4000880B2 - Image processing apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus in which a plurality of arithmetic processing apparatuses share processing data and perform parallel processing, and a method thereof.
[0002]
[Prior art]
In recent years, graphics LSIs that execute three-dimensional computer graphics (3D Computer Graphics) at high speed with hardware have been widely used. Especially, game machines and personal computers (PCs) are equipped with this graphics LSI as a standard. There are many things.
In addition, technological advances in graphics LSIs are fast, and functional expansions such as “Vertex Shader” and “Pixe 1 Shader” adopted in “DirectX” continue to be expanded, and performance exceeds the CPU speed. Has improved.
[0003]
In order to improve the performance of the graphics LSI, it is effective not only to increase the operating frequency of the LSI but also to use a parallel processing technique. The parallel processing methods can be broadly classified as follows.
The first is a parallel processing method by area division, the second is a parallel processing method at a primitive level, and the third is a parallel processing method at a pixel level.
[0004]
The above classification is based on the granularity of parallel processing, the granularity of region division parallel processing is the largest, and the granularity of pixel level parallel processing is the finest. The outline of each method is described below.
[0005]
Parallel processing by area division
This is a technique of dividing a screen into a plurality of rectangular areas and performing parallel processing while assigning areas to which each of the plurality of processing units is responsible.
[0006]
Parallel processing at the primitive level
This is a technique in which different primitives (for example, triangles) are given to a plurality of processing units to operate in parallel.
FIG. 1 conceptually shows the parallel processing at the primitive level.
In FIG. 1, PM0 to PMn-1 indicate different primitives, PU0 to PUn-1 indicate processing units, and MM0 to MMn-1 indicate memory modules, respectively.
When primitives PM0 to PMn-1 having relatively equal sizes are given to the respective processing units PU0 to PUn-1, the loads on the respective processing units PU0 to PUn-1 are balanced and efficient parallel processing can be performed. .
[0007]
Parallel processing at the pixel level
This is the method of parallel processing with the finest granularity.
FIG. 2 is a diagram conceptually illustrating parallel processing at a primitive level based on a parallel processing technique at a pixel level.
As shown in FIG. 2, in the parallel processing technique at the pixel level, when rasterizing triangles, pixels are divided into units of rectangular areas called pixel stamps (Pixel Stamp) PS made up of pixels arranged in a 2 × 8 matrix. Generated.
In the example of FIG. 2, a total of eight pixel stamps from pixel stamp PS0 to pixel stamp PS7 are generated. A maximum of 16 pixels included in these pixel stamps PS0 to PS7 are processed simultaneously.
This method is more efficient in parallel processing because of its finer granularity than other methods.
[0008]
[Problems to be solved by the invention]
However, in the case of the parallel processing based on the region division described above, in order to efficiently operate each processing unit in parallel, it is necessary to classify objects to be drawn in each region in advance, and the load of scene data analysis is heavy.
In addition, drawing is not started after all the scene data for one frame is prepared, but parallelism is drawn when drawing in so-called immediate mode in which drawing is started immediately when object data is given. I can't.
[0009]
In the case of parallel processing at the primitive level, there is actually a variation in the size of the primitives PM0 to PMn-1 constituting the object, so one primitive is processed for each processing unit PU0 to PUn-1. There is a difference in the time to do. When this difference becomes large, the drawing area of the processing unit is also greatly different, and the locality of data is lost. For example, page misses of the DRAM constituting the memory module frequently occur and the performance deteriorates.
In addition, this method has a problem that the wiring cost is high. Generally, hardware that performs graphics processing performs memory interleaving using a plurality of memory modules in order to widen the memory bandwidth.
At that time, as shown in FIG. 1, it is necessary to connect all the processing units PU0 to PUn-1 and all the built-in memory modules MM0 to MMn-1.
[0010]
On the other hand, the parallel processing at the pixel level has an advantage that the efficiency of parallel processing is good because the granularity is fine as described above, and the processing including actual filtering is performed according to the procedure shown in FIG. ing.
[0011]
That is, DDA (Digital Differential Analyzer) parameters, for example, DDA parameters such as slopes of various data (Z, texture coordinates, color, etc.) necessary for rasterization are calculated (ST1).
Next, the texture data is read from the memory (ST2), the subword rearrangement process is performed (ST3), and then globally distributed to each processing unit by the crossbar circuit (ST4).
Next, texture filtering is performed (ST5). In this case, the processing units PU0 to PU3 perform filtering processing such as 4-neighbor interpolation using the read texture data and the (u, v) address using the decimal part obtained at the time of calculation.
Next, pixel-level processing (Per-Pixel Operation), specifically, pixel-based computation is performed using filtered texture data and various data after rasterization (ST5).
Then, the pixel data that passes the various tests in the pixel level processing is drawn in the frame buffer and the Z buffer on the memory modules MM0 to MM3 (ST6).
[0012]
By the way, since the memory access of the texture read system is different from the memory access of the drawing system, it is necessary to read from the memory belonging to another module.
Therefore, for the memory read type memory access, as described above, wiring such as a crossbar circuit is required.
[0013]
However, in the conventional image processing apparatus, as described above, global distribution is performed to each processing unit by the crossbar circuit, and then texture filtering is performed. Therefore, the amount of data to be globally distributed is large (for example, 4 Tbps). There is a disadvantage that the crossbar circuit as a bus becomes large and hinders the speeding up of processing from the viewpoint of wiring delay.
[0014]
The present invention has been made in view of such circumstances, and an object thereof is to provide an image processing apparatus and method for reducing the size of a crossbar circuit and increasing the processing speed.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention is an image processing apparatus in which a plurality of processing modules share processing data and perform parallel processing, and the plurality of processing modules include at least data related to filtering processing. A memory module that stores memory, texture data for filtering processing, a processing circuit that performs processing in charge determined in advance by corresponding memory interleaving based on the processing data, and when the processing module is in charge of pixels The process data obtained in the above processing circuit and the partial calculation data of only the filter value of the texel in charge in each processing module are received and the respective partial calculation data are added to obtain the final texture value after filtering. The first arithmetic unit that performs arithmetic processing and the above processing circuit And performing a partial calculation of the filter value of only the texel in charge based on the filtering processing data handled by the self-processing module and the data related to the filtering processing stored in the memory module, and the arithmetic processing by the first computing unit A plurality of second arithmetic units that receive data and draw the data on the memory module, and further, the plurality of first arithmetic units and the plurality of second arithmetic units of each processing module are mutually connected. Filtering data obtained by the above processing circuit in each processing module is supplied to a second arithmetic unit of the same processing module, and is filtered by the second arithmetic unit of each processing module. The subsequent partial calculation data is aggregated in the first calculation unit of the processing module in charge of the pixel, Having a crossbar circuit supplies the operation process data of the first computing unit to the second operator.
[0016]
In the first aspect, both the frame buffer and the texture buffer are interleaved in all memory modules.
[0017]
In addition, in the first aspect, there is provided a setup circuit that performs an operation on the vertex data of a primitive, sets up one primitive, and outputs data in charge to each processing circuit of each processing module.
[0018]
Preferably, the setup circuit distributes all texture information to the processing circuits of the processing modules.
[0019]
A second aspect of the present invention is an image processing method in which a plurality of processing modules share processing data and perform parallel processing. In each processing module, texture data for filtering processing is obtained and based on the processing data Performs the processing in charge determined in advance by the corresponding memory interleaving, and in each processing module, only the texel in charge based on the filtering processing data handled by the own processing module and the data related to the filtering processing stored in the memory module The partial calculation data of each of the processing modules is aggregated in the processing module in charge of the pixels via the global bus, and the partial calculation data is collected in the processing module in which the partial calculation data is aggregated. Add Obtains a texture value after final filtering Te, draws the final processing data to the memory module.
[0020]
In the second aspect, both the frame buffer and the texture buffer are interleaved in all memory modules.
[0021]
In the second aspect, all texture information is distributed to each processing module.
[0022]
According to the present invention, for example, in a setup circuit, an operation is performed on vertex data, one primitive is set up, and setup information for the assigned texture is output to each processing module.
In the processing circuit in each processing module, for example, DDA parameters, specifically, DDA parameters such as inclinations of various data (Z, texture coordinates, color, etc.) necessary for rasterization are calculated based on information from the setup circuit. .
Each processing circuit determines, for example, whether or not the triangle is an area in charge of the triangle based on the parameter data. If the triangle is the area in charge, rasterization is performed.
Further, each processing circuit performs calculation of a mipmap level by LOD calculation and (u, v) address calculation for texture access.
[0023]
In each processing circuit, the obtained texture coordinates, address information for texture access, and the like are output to the second arithmetic unit.
On the other hand, in each processing circuit, information such as a color other than the obtained texture is supplied to the first computing unit.
The second computing unit of each processing module receives coordinate data and address data related to the texture supplied from the processing circuit, reads the texture data from the memory module, and reads the texture data ( The u, v) address is subjected to texture filtering such as 4-neighbor interpolation using the decimal part obtained at the time of calculation. At this time, the second calculator of each processing module performs a partial calculation of the filter value of only the texel in charge.
Each partial calculation data after filtering by the second calculator is supplied to the first calculator of the processing module in charge of the pixel via the crossbar circuit.
The first arithmetic unit of this processing module receives the partial calculation data of the filter value of only the texel in charge in each processing module and adds the partial calculation data to obtain the final filtered texture value And the result is output to the second computing unit.
Then, the second arithmetic unit receives the pixel level processing result supplied from the first arithmetic unit, and draws pixel data that has passed various tests in the pixel level processing in the memory module.
The above processing is performed in parallel in each module.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 is a block diagram showing an embodiment of the image processing apparatus according to the present invention.
[0025]
As illustrated in FIG. 4, the image processing apparatus 10 according to the present embodiment includes a setup circuit 11, processing modules 12-0 to 12-3, and a crossbar circuit 13.
[0026]
In the image processing apparatus 10, a plurality of processing modules 12-0 to 12-3 in the present embodiment are connected in parallel to the setup circuit 11, and a plurality of processing modules 12-0 to 12-3 are connected. Process data in parallel and process in parallel.
With respect to the texture read system, memory access to other processing modules is required. For this access, a crossbar circuit 13 as a global access bus is used.
[0027]
The configuration and function of each component will be described below in order with reference to the drawings.
[0028]
The setup circuit 11 performs data exchange with the CPU and external memory and data exchange with each of the processing modules 12-0 to 12-3, performs operations on vertex data, sets up one primitive, Setup information for the assigned texture is output to each of the processing modules 12-0 to 12-3.
Specifically, the setup circuit 11 performs a Per-Vertex operation when data is input.
In this process, when the vertex data of three-dimensional coordinates, normal vectors, and texture coordinates is input, the calculation for the vertex data is performed. Typical calculations include coordinate conversion calculation processing that performs deformation of an object, projection onto a screen, lighting calculation processing, and clipping calculation processing.
[0029]
The processing module 12-0 includes a DDA (Digital Differential Analyzer) circuit 121-0 as a processing circuit, a first arithmetic unit (arithmetic unit 1) 122-0, a second arithmetic unit (arithmetic unit 2) 123-0, And a memory module (MEM) 124-0 made of, for example, a DRAM.
[0030]
Similarly, the processing module 12-1 includes a DDA circuit 121-1 as a processing circuit, a first computing unit (calculating unit 1) 122-1, a second computing unit (calculating unit 2) 123-1, and, for example, It has a memory module (MEM) 124-1 made of DRAM.
The processing module 12-2 includes a DDA circuit 121-2 as a processing circuit, a first arithmetic unit (arithmetic unit 1) 122-2, a second arithmetic unit (arithmetic unit 2) 123-2, and a DRAM, for example. It has a memory module (MEM) 124-2.
The processing module 12-3 includes a DDA circuit 121-3 as a processing circuit, a first arithmetic unit (arithmetic unit 1) 122-3, a second arithmetic unit (arithmetic unit 2) 123-3, and a DRAM, for example. It has a memory module (MEM) 124-3.
[0031]
Then, as will be described in detail later, the first computing units 122-0 to 122-3 and the second computing units 123-0 to 123-3 of the processing modules 12-0 to 12-3 are crossbars. They are connected to each other through a circuit 13.
[0032]
FIG. 5 is a diagram showing a basic architecture and a processing flow of the image processing apparatus according to the present embodiment. In FIG. 5, arrows with circles indicate the flow of data regarding texture, and arrows without circles indicate the flow of data regarding pixels.
[0033]
In the present embodiment, in each of the processing modules 12-0 to 12-3, the memory modules 124-0 to 124-3 are interleaved in units of a predetermined size, for example, a 4 × 4 rectangular area.
Specifically, as shown in FIG. 5, both the so-called frame buffer and texture buffer are interleaved in all memory modules.
[0034]
The DDA circuit 121-0 in the processing module 12-0 calculates DDA parameters based on information from the setup circuit 11.
In this process, DDA parameters such as inclinations of various data (Z, texture coordinates, color, etc.) necessary for rasterization are calculated.
Further, the DDA circuit 121-0 determines, for example, whether or not the triangle is an area in charge of the triangle based on the parameter data. If the triangle is the area in charge, the DDA circuit 121-0 performs rasterization.
Specifically, it is determined whether or not the triangle belongs to an area that the user is in charge of, for example, an area interleaved in units of a rectangular area of 4 × 4 pixels. Rasterize texture coordinates, color, etc.) In this case, the generation unit is 2 × 2 pixels in one cycle per local module.
Next, the DDA circuit 121-0 performs perspective correction of the texture coordinates (Perspective Collection). Further, this processing stage includes calculation of a mipmap (MipMap) level by LOD (Level of Detail) calculation, and (u, v) address calculation for texture access.
[0035]
Then, for example, as shown in FIG. 6, the DDA circuit 121-0 performs texture processing such as texture coordinates and address information for texture access by the texture DDA unit 1211, and obtains information about the texture as the first information. The result is output to the second calculator 123-0 via the calculator 122-0 and the crossbar circuit 13.
On the other hand, the DDA circuit 121-0 performs processing of colors and the like other than the texture in the other DDA unit 1212 and outputs the result to the first computing unit 122-0.
In this embodiment, the DDA circuit 121 (−0 to 3) is provided with a FIFO (First-In First-Out) only on the data input side of the other DDA unit 1212 to take into account the time of texture filtering processing. The time is adjusted.
Also, the texture DDA unit 1211 generates texture data for all the pixels, and the other DDA units 1212 are generated only for the assigned part by memory interleaving.
[0036]
The first computing unit 122-0 receives data other than the texture information supplied by the DDA circuit 121-0 and the second processing modules 12-0 to 12-3 received via the crossbar circuit 13. Pixel level processing (Per) which receives the partial calculation data after texture filtering processing by the arithmetic units 123-0 to 123-3 and adds the partial calculation data to obtain the final filtered texture value (Per -Pixel Operation) and outputs the result to the second arithmetic unit 123-0 via the crossbar circuit 13.
In the pixel level processing, calculation in units of pixels is performed using the texture data after filtering and various data after rasterization. The processing performed here corresponds to so-called Pixel Shader such as lighting at the pixel level (Per-PixelLighting).
[0037]
The second computing unit 123-0 receives coordinate data and address data related to the texture supplied from the DDA circuit 121-0, reads the texture data from the memory module 124-0, and performs texture filtering.
At this time, the second computing unit 123-0 performs only the partial computation of the filter value of only the texel in charge, and has a frame buffer corresponding to the stamp via the crossbar circuit 13 for the filtered partial computation data. The data is output to one of the first computing units 122-0 to 122-3 of the processing module.
In this case, the second computing unit 123-0 performs filtering processing such as 4-neighbor interpolation using the read texture data and the (u, v) address using the decimal part obtained at the time of calculation.
Further, the second arithmetic unit 123-0 receives the pixel level processing result supplied from the first arithmetic unit 122-0, and passes the pixel data that has passed various tests in the pixel level processing to the memory module 124-. Draw at 0.
[0038]
The DDA circuit 121-1 in the processing module 12-1 is based on the information from the setup circuit 11, specifically DDA parameters such as slopes of various data (Z, texture coordinates, color, etc.) necessary for rasterization. Calculate the parameters.
Further, the DDA circuit 121-1 determines, for example, whether or not the triangle is an area in charge of the triangle based on the parameter data. If the triangle is the area in charge, the DDA circuit 121-1 performs rasterization.
Specifically, it is determined whether or not the triangle belongs to an area that the user is in charge of, for example, an area interleaved in units of a rectangular area of 4 × 4 pixels. Rasterize texture coordinates, color, etc.) In this case, the generation unit is 2 × 2 pixels in one cycle per local module.
Next, the DDA circuit 121-1 performs a perspective collection of texture coordinates (Perspective Collection). Further, this processing stage includes calculation of a mipmap level by LOD calculation and calculation of (u, v) address for texture access.
[0039]
Then, for example, as shown in FIG. 6, the DDA circuit 121-1 performs texture processing such as texture coordinates and address information for texture access by the texture DDA unit 1211, and obtains information about the texture as the first information. The result is output to the second arithmetic unit 123-1 via the arithmetic unit 122-1 and the crossbar circuit 13.
On the other hand, the DDA circuit 121-1 performs processing of colors other than the texture in the other DDA unit 1212 and outputs it to the first calculator 122-1.
[0040]
The first arithmetic unit 122-1 receives data other than the texture information supplied from the DDA circuit 121-1 and the second of each processing module 12-0 to 12-3 received via the crossbar circuit 13. Pixel level processing is performed in which arithmetic units 123-0 to 123-3 receive partial arithmetic data after texture filtering processing, and perform arithmetic processing to obtain final filtered texture values by adding the partial arithmetic data. The result is output to the second arithmetic unit 123-1 via the crossbar circuit 13.
In the pixel level processing, calculation in units of pixels is performed using the texture data after filtering and various data after rasterization. The processing performed here is so-called Pixel, such as lighting at the pixel level.
Corresponds to Shader.
[0041]
The second arithmetic unit 123-1 receives coordinate data and address data related to the texture supplied from the DDA circuit 121-1, reads the texture data from the memory module 124-1, and performs texture filtering.
At this time, the second arithmetic unit 123-1 performs only the partial calculation of the filter value of only the texel in charge, and the filtered partial calculation data has a frame buffer corresponding to the stamp via the crossbar circuit 13. The data is output to any one of the first computing units 122-0 to 122-3 of the processing module.
In this case, the second computing unit 123-1 performs filtering processing such as 4-neighbor interpolation using the read texture data and the (u, v) address using the decimal part obtained at the time of calculation.
In addition, the second arithmetic unit 123-1 receives the pixel level processing result supplied from the first arithmetic unit 122-1, and outputs pixel data that has passed various tests in the pixel level processing to the memory module 124-. Draw to 1.
[0042]
The DDA circuit 121-2 in the processing module 12-2 is based on the information from the setup circuit 11, and specifically, DDA parameters such as slopes of various data (Z, texture coordinates, color, etc.) necessary for rasterization. Calculate the parameters.
Further, the DDA circuit 121-2 determines, for example, whether or not a triangle is an area in charge of the triangle based on the parameter data.
Specifically, it is determined whether or not the triangle belongs to an area that the user is in charge of, for example, an area interleaved in units of a rectangular area of 4 × 4 pixels. Rasterize texture coordinates, color, etc.) In this case, the generation unit is 2 × 2 pixels in one cycle per local module.
Next, the DDA circuit 121-2 performs a perspective collection of texture coordinates (Perspective Collection). Further, this processing stage includes calculation of a mipmap level by LOD calculation and calculation of (u, v) address for texture access.
[0043]
Then, for example, as shown in FIG. 6, the DDA circuit 121-2 performs texture processing such as texture coordinates and address information for texture access by the texture DDA unit 1211, and obtains information about the texture as the first information. The result is output to the second calculator 123-2 via the calculator 122-2 and the crossbar circuit 13.
On the other hand, the DDA circuit 121-2 performs processing such as color other than texture in the other DDA unit 1212 and outputs the result to the first computing unit 122-2.
[0044]
The first arithmetic unit 122-2 receives the data other than the texture information supplied from the DDA circuit 121-2 and the second processing modules 12-0 to 12-3 received via the crossbar circuit 13. Pixel level processing is performed in which arithmetic units 123-0 to 123-3 receive partial arithmetic data after texture filtering processing, and perform arithmetic processing to obtain final filtered texture values by adding the partial arithmetic data. The result is output to the second arithmetic unit 123-2 via the crossbar circuit 13.
In the pixel level processing, calculation in units of pixels is performed using the texture data after filtering and various data after rasterization. The processing performed here is so-called Pixel, such as lighting at the pixel level.
Corresponds to Shader.
[0045]
The second computing unit 123-2 receives coordinate data and address data related to the texture supplied from the DDA circuit 121-2, reads the texture data from the memory module 124-2, and performs texture filtering.
At this time, the second arithmetic unit 123-2 performs only the partial calculation of the filter value of only the texel in charge, and has a frame buffer corresponding to the stamp through the crossbar circuit 13 for the partial calculation data after filtering. The data is output to any one of the first computing units 122-0 to 122-3 of the processing module.
In this case, the second computing unit 123-2 performs filtering processing such as 4-neighbor interpolation using the read texture data and the (u, v) address using the decimal part obtained at the time of calculation.
Further, the second computing unit 123-2 receives the pixel level processing result supplied from the first computing unit 122-2, and passes the pixel data that has passed various tests in the pixel level processing to the memory module 124-. Draw in 2.
[0046]
The DDA circuit 121-3 in the processing module 12-3 is a DDA parameter based on information from the setup circuit 11, specifically, a DDA such as a gradient of various data (Z, texture coordinates, color, etc.) necessary for rasterization. Calculate the parameters.
Further, the DDA circuit 121-3 determines, for example, whether or not the triangle is an area in charge of the triangle based on the parameter data. If the triangle is in the area in charge, the DDA circuit 121-3 performs rasterization.
Specifically, it is determined whether or not the triangle belongs to an area that the user is in charge of, for example, an area interleaved in units of a rectangular area of 4 × 4 pixels. Rasterize texture coordinates, color, etc.) In this case, the generation unit is 2 × 2 pixels in one cycle per local module.
Next, the DDA circuit 121-3 performs perspective correction of the texture coordinates (Perspective Correction). Further, this processing stage includes calculation of a mipmap level by LOD calculation and calculation of (u, v) address for texture access.
[0047]
Then, for example, as shown in FIG. 6, the DDA circuit 121-3 performs texture processing such as texture coordinates and address information for texture access by the texture DDA unit 1211, and obtains information about the texture as the first information. The result is output to the second calculator 123-3 via the calculator 122-3 and the crossbar circuit 13.
On the other hand, the DDA circuit 121-3 performs other processing such as color other than the texture in the other DDA unit 1212 and outputs it to the first computing unit 122-3.
[0048]
The first computing unit 122-3 receives the data other than the texture information supplied from the DDA circuit 121-3 and the second processing modules 12-0 to 12-3 received via the crossbar circuit 13. Pixel level processing is performed in which arithmetic units 123-0 to 123-3 receive partial arithmetic data after texture filtering processing, and perform arithmetic processing to obtain final filtered texture values by adding the partial arithmetic data. The result is output to the second arithmetic unit 123-3 via the crossbar circuit 13.
In the pixel level processing, calculation in units of pixels is performed using the texture data after filtering and various data after rasterization. The processing performed here is so-called Pixel, such as lighting at the pixel level.
Corresponds to Shader.
[0049]
The second arithmetic unit 123-3 receives coordinate data and address data related to the texture supplied from the DDA circuit 121-3, reads the texture data from the memory module 124-3, and performs texture filtering.
At this time, the second arithmetic unit 123-3 performs only the partial calculation of the filter value of only the texel in charge, and has a frame buffer corresponding to the stamp through the crossbar circuit 13 for the partial calculation data after filtering. The data is output to any one of the first computing units 122-0 to 122-3 of the processing module.
In this case, the second arithmetic unit 123-3 performs a filtering process such as 4-neighbor interpolation using the read texture data and the (u, v) address using the decimal part obtained at the time of calculation.
Further, the second arithmetic unit 123-3 receives the pixel level processing result supplied from the first arithmetic unit 122-3, and passes the pixel data that has passed various tests in the pixel level processing to the memory module 124-. Draw in 3.
[0050]
FIG. 7 is a diagram illustrating a configuration example of the global bus system of the crossbar circuit according to the present embodiment.
As shown in FIG. 7, the crossbar circuit 13 includes four texture lines as one group and four groups of first to fourth wiring groups GRP0 to GRP3.
The first wiring group GRP0 has four wirings tex00 to tex03, the second wiring group GRP1 has four wirings tex10 to tex13, and the third wiring group GRP2 has four wirings tex20 to tex23. The fourth wiring group GRP3 includes four wirings tex30 to tex33.
The terminals of the second computing unit 123-0 of the processing module 12-0 are the wiring tex00 of the first wiring group GRP0, the wiring tex10 of the second wiring group GRP1, the wiring tex20 of the third wiring group GRP2, It is connected to the wiring tex30 of the fourth wiring group GRP3.
Similarly, the terminals of the second arithmetic unit 123-1 of the processing module 12-1 are connected to the wiring tex01 of the first wiring group GRP0, the wiring tex11 of the second wiring group GRP1, and the wiring tex21 of the third wiring group GRP2. It is connected to the wiring tex31 of the fourth wiring group GRP3.
The terminals of the second computing unit 123-2 of the processing module 12-2 are the wiring tex02 of the first wiring group GRP0, the wiring tex12 of the second wiring group GRP1, the wiring tex22 of the third wiring group GRP2, and the fourth. It is connected to the wiring tex32 of the wiring group GRP3.
The terminals of the second arithmetic unit 123-3 of the processing module 12-3 are the wiring tex03 of the first wiring group GRP0, the wiring tex13 of the second wiring group GRP1, the wiring tex23 of the third wiring group GRP2, and the fourth. It is connected to the wiring tex33 of the wiring group GRP3.
[0051]
The four wirings tex00 to tex03 of the first wiring group GRP0 are connected to the respective terminals of the first computing unit 122-0 of the processing module 12-0.
Similarly, the four wirings tex10 to tex13 of the second wiring group GRP1 are connected to the respective terminals of the first computing unit 122-1 of the processing module 12-1.
Four wirings tex20 to tex23 of the third wiring group GRP2 are connected to the respective terminals of the first computing unit 122-2 of the processing module 12-2.
Four wirings tex30 to tex33 of the fourth wiring group GRP3 are connected to each terminal of the first computing unit 122-3 of the processing module 12-3.
[0052]
Next, the operation of the configuration of FIG. 4 will be described with reference to FIG.
[0053]
First, the setup circuit 11 performs an operation on the vertex data, sets up one primitive, and outputs setup information for the assigned texture to each processing module 12-0 to 12-3.
[0054]
In the DDA circuits 121-0 to 121-3 in the processing modules 12-0 to 12-3, DDA parameters based on information from the setup circuit 11, specifically, various data (Z, texture coordinates required for rasterization) DDA parameters such as the slope of the color, etc.) are calculated.
In addition, the DDA circuits 121-0 to 121-3 determine, for example, whether or not a triangle is an area in charge of the triangle based on the parameter data. If the triangle is an area in charge, rasterization is performed.
Further, the DDA circuits 121-0 to 121-3 perform calculation of mipmap levels by LOD calculation and (u, v) address calculation for texture access.
[0055]
In the DDA circuits 121-0 to 121-3, the texture coordinates obtained by the texture DDA unit 1211, the address information for accessing the texture, and the like are stored in the first arithmetic units 122-0 to 122-3. The data is output to the second computing units 123-0 to 123-3 via the bar circuit 13.
On the other hand, in the DDA circuits 121-0 to 121-3, information such as colors other than the texture obtained by the other DDA units 1212 is supplied to the first calculators 122-0 to 122-3, respectively.
[0056]
Then, the second computing units 123-0 to 123-3 of the processing modules 12-0 to 12-3 receive the coordinate data and address data related to the texture supplied from the DDA circuits 121-0 to 121-3. The texture data is read from the memory modules 124-0 to 124-3, and the read texture data and the (u, v) address are partial textures such as 4-neighbor interpolation using the decimal part obtained at the time of calculation. Filtering is performed.
That is, at this time, the second calculators 123-0 to 123-3 perform partial calculation of the filter value of only the texel in charge.
Each partial calculation data after filtering by the second calculators 123-0 to 123-3 has a frame buffer corresponding to the stamp via the crossbar circuit 13, for example, the first calculation of the processing module 12-1. Is supplied to the device 122-1.
[0057]
In the first computing unit 122-1 of the processing module 12-1, each of the processing modules 12-0 to 12-12 received via the crossbar circuit 13 and data other than the texture information supplied by the DDA circuit 121-1. -3 second arithmetic units 123-0 to 123-3 receive the partial operation data after the texture filtering process, add the respective partial operation data, and perform the operation process to obtain the final filtered texture value Pixel level processing is performed, and the result is output to the second calculator 123-1 via the crossbar circuit 13.
[0058]
Then, the second arithmetic unit 123-1 receives the pixel level processing result supplied from the first arithmetic unit 122-1, and the pixel data that has passed various tests in the pixel level processing is stored in the memory module 124-. 1 is drawn.
[0059]
The above processing is performed in parallel in each module.
[0060]
As described above, according to the present embodiment, as shown in FIG. 8, after DDA processing (ST11), texture data is read from the memory (ST12), and subword rearrangement processing is performed (ST13). (ST14), and then globally distributed to the first arithmetic units of the respective processing modules by the crossbar circuit 13 (ST15) to process the pixel level, specifically, the partial operation data after filtering. In response, each partial calculation data is added to perform calculation processing for each pixel to perform calculation processing for obtaining a final filtered texture value (ST16), and pixel data that has passed various tests in pixel level processing is Since drawing in the frame buffer on the memory module (ST17), Effect can be obtained.
[0061]
That is, since the amount of texel transfer between processing modules can be reduced, the crossbar circuit 13 as a global bus can be reduced in size.
In addition, the memory arrangement may be global. That is, since it can be arranged in the same manner as the frame buffer, the frame buffer can be used as a texture memory. Also, maps of different sizes can be arranged efficiently.
Further, since there is only one cache for a specific texel, the cache utilization efficiency is high.
In addition, when interleaving is performed in units of 4 × 4 between processing modules, processing can be performed by transferring 25/16 texels per pixel with a 2 × 2 4-neighbor interpolation filter.
In the case where the present embodiment is not used, 48/16 texels are transferred. Even if request merging is performed, 32/16 texels are transferred.
[0062]
【The invention's effect】
As described above, according to the present invention, when a plurality of processing devices share processing data and perform parallel processing, the number of wires of the crossbar circuit can be reduced and the size can be reduced. As a result, there is an advantage that an image processing apparatus that can be easily designed and can reduce wiring cost and wiring delay can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram conceptually illustrating parallel processing at a primitive level.
FIG. 2 is a diagram conceptually illustrating a parallel processing at a primitive level based on a parallel processing technique at a pixel level.
FIG. 3 is a diagram for explaining a processing procedure including texture filtering of a conventional image processing apparatus.
FIG. 4 is a block configuration diagram showing an embodiment of an image processing apparatus according to the present invention.
FIG. 5 is a diagram illustrating a basic architecture and a processing flow of an image processing apparatus according to the present embodiment.
FIG. 6 is a diagram illustrating a configuration example of a main part of a DDA circuit according to the present embodiment.
FIG. 7 is a diagram showing a specific configuration example of a crossbar circuit according to the present embodiment.
FIG. 8 is a diagram illustrating a conceptual processing flow of the image processing apparatus according to the present embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Image processing apparatus, 11 ... Setup circuit, 12-0 to 12-3 ... Processing module, 121-0 to 121-3 ... DDA circuit, 122-0 to 122-3 ... First computing unit, 123-0 ˜123-3, a second computing unit, 124-0 to 124-3, a memory module, and 13 a crossbar circuit.

Claims (7)

An image processing apparatus in which a plurality of processing modules share processing data and perform parallel processing,
The plurality of processing modules are
A memory module storing at least data related to the filtering process;
A processing circuit for obtaining texture data for filtering processing and performing processing in charge determined in advance by corresponding memory interleaving based on the processing data;
When the own processing module takes charge of the pixel, it receives the processing data in charge obtained in the processing circuit and the partial calculation data of the filter value of only the texel in charge in each processing module, and adds each partial calculation data A first arithmetic unit that performs arithmetic processing to obtain a final texture value after filtering;
Based on the filtering processing data handled by the processing module obtained in the processing circuit and the data related to the filtering processing stored in the memory module, partial calculation of the filter value of only the texel in charge is performed, and the first A plurality of second arithmetic units which receive arithmetic processing data from the arithmetic units and draw the data on the memory module;
Have
Furthermore, a global bus interconnecting the plurality of first arithmetic units and the plurality of second arithmetic units of each processing module, wherein the filtering processing data obtained by the processing circuit in each processing module Supplying the second arithmetic unit of the same processing module to the partial arithmetic data after filtering by the second arithmetic unit of each processing module, the first arithmetic unit of the processing module responsible for the pixel, An image processing apparatus having a crossbar circuit for supplying arithmetic processing data by a first arithmetic unit to a second arithmetic unit. The image processing apparatus according to claim 1, wherein both the frame buffer and the texture buffer are interleaved in all memory modules. The image processing apparatus according to claim 1, further comprising: a setup circuit that performs an operation on the vertex data of the primitive, sets up one primitive, and outputs data assigned to the processing circuit of each processing module. 4. The image processing apparatus according to claim 3, wherein the setup circuit distributes all texture information to the processing circuit of each processing module. An image processing method in which a plurality of processing modules share processing data and perform parallel processing,
In each processing module, the texture data for filtering processing is obtained, and the processing in charge determined by the corresponding memory interleave based on the processing data is performed.
In each processing module, perform a partial calculation of the filter value of only the texel in charge based on the data for filtering processing in charge of the own processing module and the data related to the filtering processing stored in the memory module,
The above partial calculation data in each processing module is aggregated in a processing module in charge of pixels via a global bus,
In the processing module in which the partial calculation data is aggregated, each partial calculation data is added to obtain a final filtered texture value,
An image processing method for drawing the final arithmetic processing data on the memory module. 6. The image processing method according to claim 5, wherein both the frame buffer and the texture buffer are interleaved in all memory modules. 6. The image processing method according to claim 5, wherein all the texture information is distributed to each processing module.

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