JP4088595B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a MOS transistor with excellent driving power and a method for manufacturing the same.

  In recent years, in the development of highly integrated semiconductor devices, so-called VLSIs, there has been a demand for further miniaturization of MOS transistors which are constituent elements of VLSIs. In MOS transistors, the size of each generation of devices is reduced according to the scaling law. To cope with this, increasing the substrate concentration improves the device characteristics while suppressing the so-called short channel effect. I am trying.

  However, it is difficult to reduce the depth of the impurity layer serving as the source or drain among the various dimensions of the device. Therefore, a structure of a MOS transistor for suppressing the short channel effect has been proposed.

  Hereinafter, as conventional examples, for example, MOS transistors shown in GG Shahidi et al, “High-Performance Devices for a 0.15 μm CMOS Technology”, IEEE Electron Device Letters, vol. 14, no. 10, Octber 1993 ( Hereinafter, the structure and manufacturing method of the conventional MOS transistor will be described with reference to FIG.

As shown in FIG. 20, a conventional MOS transistor includes a p ⁻ type well region 2 formed inside a semiconductor substrate 1, a p type channel region 3 formed on the surface of the semiconductor substrate 1, and a channel region. A source / drain composed of a gate electrode 5 formed on the substrate 3 via a gate insulating film 4 and n ⁺ -type impurity layers respectively formed in regions on both sides of the gate electrode 5 on the surface portion of the semiconductor substrate 1 A region 9, an extension region 6 made of an n ⁺ -type impurity layer formed inside the source / drain region 9 in the surface portion of the semiconductor substrate 1, an extension region 6 covering the surface portion of the semiconductor substrate 1 and an upper end portion Includes a p ⁺ -type pocket region 7 formed so as to extend to the gate insulating film 4.

According to the conventional MOS transistor, the p ⁺ -type pocket region 7 is formed so as to cover the n ⁺ -type extension region 6, and the pocket region 7 includes the n ⁺ -type extension region 6 and the source / drain. Since the situation where the depletion layer extends from the region 9 is suppressed, the short channel effect can be suppressed.

  Even when the depth of the extension region 6 or the source / drain region 9 cannot be reduced in accordance with the scaling law, the short channel effect can be suppressed by increasing the impurity concentration of the pocket region 7.

  However, the conventional MOS transistor has the following problems.

(First problem)
When the impurity concentration of the p ⁺ type pocket region is increased to further suppress the short channel effect, the impurity concentration in the extension region is offset and lowered because the pocket region covers the n ⁺ type extension region. . For this reason, since the resistance of the extension region is increased, there is a problem that the driving capability of the MOS transistor is reduced. Further, when the impurity concentration of the p ⁺ -type pocket region is increased, the impurity concentration in the vicinity of the extension region in the channel region is increased, so that carrier impurity scattering is increased and the carrier mobility is decreased. The driving force is further reduced. Further, when the impurity concentration in the vicinity of the extension region in the channel region is increased, a so-called reverse short channel effect is generated, which causes a problem that the threshold voltage of the transistor greatly depends on the channel length of the transistor.

(Second problem)
By the way, the sidewall is formed by implanting n-type impurity ions to form extension regions and implanting p-type impurity ions to form pocket regions, and then insulating films over the entire surface of the semiconductor substrate. Is deposited at a low temperature of 600 ° C. to 850 ° C. over several tens of minutes to several hours, and then anisotropic etching is performed on the insulating film. The pores and interstitial silicon) cause significant enhanced diffusion of impurities (Transient Enhanced Diffusion). For this reason, since the impurity concentration in the pocket region is increased, the resistance of the extension region is increased and the carrier mobility is lowered, thereby reducing the driving force of the MOS transistor. In addition, interstitial silicon generated during ion implantation for forming the extension region and the pocket region is diffused and distributed toward the gate insulating film during low-temperature heat treatment (for example, when an insulating film serving as a sidewall is deposited). Since a gradient is generated in the channel region, the impurity at the end of the gate electrode in the channel region moves toward the substrate surface, so that the impurity concentration of the surface region at the end of the gate electrode in the channel region increases. For this reason, a so-called reverse short channel effect occurs, and there is a problem that the threshold voltage changes. This phenomenon becomes prominent when boron ions are implanted to form a pocket region.

(Third problem)
In a conventional method for manufacturing a MOS transistor, in order to make the distribution of arsenic ions in the n ⁺ -type extension region steep, indium ions are implanted into the p ⁺ -type pocket region to make the pocket region amorphous.

  However, we have a point in the vicinity of the pn junction formed between the extension region and the pocket region and inside the pocket region (that is, outside the extension region) by the heat treatment performed after the amorphization process. I found a new defect. When a point defect occurs inside the pocket region, a junction leakage current is generated. When such a VLSI having a MOS transistor is incorporated into a mobile communication device portable device, there is a problem that power consumption during standby increases due to junction leakage current.

  In view of the above, an object of the present invention is to improve the driving capability of a MOS transistor.

  To achieve the above object, a first semiconductor device according to the present invention includes a gate electrode formed on a semiconductor substrate via a gate insulating film, and a region immediately below the gate electrode in the surface portion of the semiconductor substrate. A channel region formed of the first conductivity type semiconductor layer, a source region and a drain region formed of impurity layers of the second conductivity type formed in regions on both sides of the gate electrode in the surface portion of the semiconductor substrate, and a channel An extension region of a second conductivity type formed so as to be in contact with the source region or the drain region, and a lower region of the channel region, the source region and the drain region. A first conductivity type pocket formed in contact with the source region or the drain region and spaced apart from the gate insulating film. And a region.

  According to the first semiconductor device, the first region formed between the channel region and the lower regions of the source region and the drain region is in contact with the source region or the drain region and spaced from the gate insulating film. Since the pocket region of the conductive type is provided, even if the impurity concentration in the pocket region is increased to suppress the short channel effect, the impurity concentration in the extension region does not decrease and the impurity concentration in the vicinity of the extension region in the channel region is It will not be high.

  Therefore, since the impurity concentration in the extension region does not decrease, the resistance in the extension region does not increase, and this can suppress a decrease in driving force of the MOS transistor. Further, since the impurity concentration in the channel region in the vicinity of the extension region does not increase, it is possible to prevent a decrease in carrier mobility due to carrier impurity scattering, thereby preventing a reduction in driving force of the MOS transistor. Can do.

  For this reason, according to the first semiconductor device, it is possible to prevent a reduction in the driving power of the MOS transistor while suppressing the short channel effect.

  In the first semiconductor device, a first-conductivity-type low-concentration channel region that is formed on both sides of the channel region so as to be in contact with the extension region and has a lower concentration of activating impurities than the central portion of the channel region Is preferably further provided.

  In this case, the regions on both sides of the channel region are provided with the low concentration channel region that is in contact with the extension region and has a lower concentration of activating impurities than the central portion of the channel region. The concentration of the activated impurity in the region is low concentration-high concentration-low concentration from the source side to the drain side or from the drain side to the source side. That is, the concentration of the activation impurity in the region in the channel region that is in contact with the extension region is low.

  Accordingly, since the resistance of the extension region is further reduced, it is possible to further prevent a reduction in the driving capability of the MOS transistor.

  A second semiconductor device according to the present invention includes a gate electrode formed on a semiconductor substrate via a gate insulating film and a region immediately below the gate electrode in the surface portion of the semiconductor substrate, doped with indium ions. A channel region made of a first conductivity type semiconductor layer, a source region and a drain region made of a second conductivity type impurity layer formed in regions on both sides of the gate electrode in the surface portion of the semiconductor substrate, a channel region, A second conductivity type extension region formed so as to be in contact with the source region or the drain region between each of the upper regions of the source region and the drain region, and a region on both sides of the channel region so as to be in contact with the extension region And a first conductivity type low-concentration chip having a lower concentration of activating impurities than the central portion of the channel region. And a channel region.

  According to the second semiconductor device, the channel region is provided with the low-concentration channel region that is in contact with the extension region and has a lower concentration of activating impurities than the central portion of the channel region. The concentration of the activation impurity in the upper region of the region is low concentration-high concentration-low concentration from the source side to the drain side or from the drain side to the source side. That is, the concentration of the activation impurity in the region in the channel region that is in contact with the extension region is low. For this reason, since the resistance of the extension region becomes low, it is possible to prevent the driving force of the MOS transistor from being lowered.

  A first semiconductor device manufacturing method according to the present invention includes a step of ion-implanting first conductivity type impurity ions into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer serving as a channel region; Forming a gate electrode on the semiconductor substrate via a gate insulating film; and implanting second conductivity type impurity ions into the semiconductor layer using the gate electrode as a mask to form a second conductivity type in an upper region of the semiconductor layer Forming a first impurity layer, implanting indium ions into the semiconductor layer using a gate electrode as a mask to form a first conductivity type impurity layer in a lower region of the semiconductor layer, and forming a semiconductor substrate on the semiconductor substrate On the other hand, a step of performing a short-time heat treatment at a temperature of about 950 ° C. to about 1050 ° C., a step of forming a sidewall on the side surface of the gate electrode, a first conductivity type first impurity layer, and a first conductivity type impurities In addition, second conductivity type impurity ions are ion-implanted using the gate electrode and the sidewall as a mask, and the second conductivity type first impurity layer and the first conductivity type impurity layer are formed in regions on both sides of the gate electrode. A source region and a drain region composed of a second impurity layer of the second conductivity type are formed, and an extension of the second conductivity type is formed inside each upper region of the source region or the drain region in the first impurity layer of the second conductivity type. Forming a region, and forming a pocket region of the first conductivity type inside each lower region of the source region or drain region in the impurity layer of the first conductivity type.

  According to the first method for manufacturing a semiconductor device, indium ions having an atomic mass larger than that of boron ions are ion-implanted to form a first conductivity type impurity layer serving as a pocket region. The peak position of the distribution can be made shallow, and the range in which the pocket region expands can be suppressed. In addition, since the diffusion coefficient of indium ions is smaller than the diffusion coefficient of boron ions, expansion of the pocket region due to thermal diffusion can be suppressed.

  By the way, indium ions, like boron ions, may cause accelerated diffusion due to point defects generated during ion implantation. However, in the first method of manufacturing a semiconductor device, after indium ions are ion-implanted to form a first conductivity type impurity layer that becomes a pocket region, a short-time heat treatment is performed at a temperature of about 950 ° C. to about 1050 ° C. Therefore, the occurrence of accelerated diffusion due to point defects can be suppressed.

  Therefore, according to the first method for manufacturing a semiconductor device, the first semiconductor device having a pocket region spaced from the gate insulating film can be reliably manufactured.

In the first method for fabricating a semiconductor device, the dose of indium ions in the step of forming the first conductivity type impurity layer is preferably 5 × 10 ¹³ cm ⁻² or less.

  In this way, in the first conductivity type impurity layer serving as the pocket region, the silicon crystal does not become amorphous, and EOR point defects such as a transition loop do not occur, so that the occurrence of junction leakage current can be prevented.

  The second method for manufacturing a semiconductor device according to the present invention includes a step of ion-implanting first conductivity type impurity ions into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer serving as a channel region; Forming a gate electrode on a semiconductor substrate through a gate insulating film; and implanting ions of atoms belonging to Group IV into the semiconductor layer using the gate electrode as a mask to form a first conductivity type in an upper region of the semiconductor layer Forming an amorphous layer, and implanting a second conductivity type impurity ion into the amorphous layer by using the gate electrode as a mask, and implanting the second conductivity type first impurity layer into the amorphous layer. Forming a first conductivity type impurity layer in a lower region of the semiconductor layer by implanting indium ions into the semiconductor layer using the gate electrode as a mask, and about 950 ° C. to about 950 ° C. Short at a temperature of 1050 ° C A step of performing a heat treatment in between, a step of forming a sidewall on the side surface of the gate electrode, a first impurity layer of the second conductivity type and an impurity layer of the first conductivity type using the gate electrode and the sidewall as a mask. Two-conductivity type impurity ions are ion-implanted, and the second conductivity-type second impurity layer is implanted into regions on both sides of the gate electrode in the second conductivity-type first impurity layer and the first conductivity-type impurity layer. A source region and a drain region are formed, a second conductivity type extension region is formed inside each upper region of the source region or the drain region in the second conductivity type first impurity layer, and the first conductivity type Forming a pocket region of the first conductivity type inside each lower region of the source region or drain region in the impurity layer.

  According to the second semiconductor device manufacturing method, as in the first semiconductor device manufacturing method, indium ions having a large atomic mass and a small diffusion coefficient compared to boron ions are ion-implanted to form a pocket region. Since the impurity layer of one conductivity type is formed, the peak position of the impurity concentration distribution in the pocket region can be shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. Therefore, the first semiconductor device having the pocket region spaced from the gate insulating film can be reliably manufactured.

  In particular, in the second method for manufacturing a semiconductor device, an amorphous layer is formed in the upper region of the first conductivity type semiconductor layer, and then the second conductivity type impurity ions are ion-implanted to extend the extension. Since the first impurity layer of the second conductivity type serving as the region is formed, the distribution of the impurity concentration in the first impurity layer of the second conductivity type becomes steep, so that the resistance of the extension region can be reduced, As a result, the driving capability of the MOS transistor can be improved.

In the second method for fabricating a semiconductor device, the dose of indium ions in the step of forming the first conductivity type impurity layer is preferably 5 × 10 ¹³ cm ⁻² or less.

  In this way, in the first conductivity type impurity layer serving as the pocket region, the silicon crystal does not become amorphous, and EOR point defects such as a transition loop do not occur, so that the occurrence of junction leakage current can be prevented.

  A third method for manufacturing a semiconductor device according to the present invention includes a step of ion-implanting indium ions into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer serving as a channel region; A step of forming a gate electrode through the gate insulating film; and ion implantation of second conductivity type impurity ions into the semiconductor layer using the gate electrode as a mask to form a second conductivity type first impurity in an upper region of the semiconductor layer Forming a layer, and depositing an insulating film over the entire surface of the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C. to form a first impurity layer of the second conductivity type in the upper region of the semiconductor layer. Forming a first-conductivity-type low-concentration channel region having an impurity concentration lower than that of the semiconductor layer on the inner side, and performing anisotropic etching on the insulating film to form a sidewall on the side surface of the gate electrode And second The second conductivity type first impurity layer and the semiconductor layer are ion-implanted into the first conductivity type impurity layer and the semiconductor layer by using the gate electrode and the sidewall as a mask, and the gate electrode in the second conductivity type first impurity layer and the semiconductor layer. Forming a source region and a drain region made of a second impurity layer of the second conductivity type in regions on both sides of the first region, and inside each upper region of the source region or the drain region in the first impurity layer of the second conductivity type And a step of forming an extension region of the second conductivity type.

  According to the third method for manufacturing a semiconductor device, indium ions are ion-implanted to form a first conductivity type semiconductor layer to be a channel region, and second conductivity type impurity ions are ion-implanted to form an extension region. Forming a second impurity layer of the second conductivity type, and performing a low-temperature long-time heat treatment when depositing the insulating film at a temperature of about 600 ° C. to about 850 ° C. Interstitial silicon atoms generated when the first impurity layer of the second conductivity type serving as the extension region is formed by ion implantation move toward the gate insulating film by the low-temperature and long-time heat treatment. The indium ions are deactivated by combining with indium ions existing in the lower regions of both sides of the gate insulating film in the first conductivity type semiconductor layer. For this reason, in the lower region on both sides of the gate insulating film in the first conductivity type semiconductor layer to be the channel region, that is, the region inside the second conductivity type first impurity layer in the first conductivity type semiconductor layer, A low-concentration channel region having a lower concentration of activating impurities than the semiconductor layer of the first conductivity type is formed.

  Therefore, according to the third method for manufacturing a semiconductor device, the second semiconductor device having a low-concentration channel region in which the concentration of the activation impurity is lower than that in the central portion of the channel region is reliably provided in the regions on both sides of the channel region. Can be manufactured.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: injecting indium ions into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer serving as a channel region; Forming a gate electrode through the gate insulating film; and implanting ions of atoms belonging to Group IV into the semiconductor layer using the gate electrode as a mask to form an amorphous layer of the first conductivity type in the upper region of the semiconductor layer Forming a second conductive type first impurity layer in an amorphous state by ion-implanting second conductive type impurity ions into the amorphous layer using the gate electrode as a mask, and a semiconductor An insulating film is deposited on the entire surface of the substrate at a temperature of about 600 ° C. to about 850 ° C. so that the impurity is more inside the first impurity layer of the second conductivity type in the upper region of the semiconductor layer than the semiconductor layer. Low-concentration first conductivity type Forming a channel region, performing anisotropic etching on the insulating film to form sidewalls on side surfaces of the gate electrode, and forming a gate on the first impurity layer and the semiconductor layer of the second conductivity type The second conductivity type impurity ions are ion-implanted using the electrode and the sidewall as a mask, and the second conductivity type second impurity is implanted into regions on both sides of the gate electrode in the second conductivity type first impurity layer and the semiconductor layer. Forming a source region and a drain region made of an impurity layer, and forming an extension region of the second conductivity type inside each upper region of the source region or the drain region in the first impurity layer of the second conductivity type. I have.

  According to the fourth semiconductor device manufacturing method, as in the third semiconductor device manufacturing method, indium ions are ion-implanted to form a first conductivity type semiconductor layer serving as a channel region, and the second conductivity type. After the first impurity layer of the second conductivity type that becomes the extension region is formed by ion implantation of the impurity ions, a low-temperature long-time heat treatment is performed when the insulating film is deposited at a temperature of about 600 ° C. to about 850 ° C. The interstitial silicon atoms move in the direction of the gate insulating film, so that indium present in the lower regions of both sides of the gate insulating film in the semiconductor layer of the first conductivity type. Since the indium ions are deactivated by combining with the ions, the first conductivity type semiconductor layer is more active than the first conductivity type semiconductor layer in the region inside the second conductivity type first impurity layer. Impurities Degrees it is possible to form a low low concentration channel region.

  In particular, in the fourth method of manufacturing a semiconductor device, the IV group is formed before the step of forming the second conductivity type first impurity layer to be the extension region by ion implantation of the second conductivity type impurity ions. The step of forming an amorphous layer in the upper region of the first conductivity type semiconductor layer by ion implantation of ions of atoms belonging to As the number of silicon atoms increases, the number of indium ions deactivated by bonding with interstitial silicon atoms also increases. Therefore, it is possible to efficiently form a low-concentration channel region in which the concentration of the activation impurity is lower than that of the first conductivity type semiconductor layer.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: injecting indium ions into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer serving as a channel region; A step of forming a gate electrode through the gate insulating film; and ion implantation of second conductivity type impurity ions into the semiconductor layer using the gate electrode as a mask to form a second conductivity type first impurity in an upper region of the semiconductor layer Forming a layer, and subjecting the semiconductor substrate to a first heat treatment for a long time at a temperature of about 600 ° C. to about 850 ° C. to form a first impurity layer of the second conductivity type in the upper region of the semiconductor layer. A step of forming a low-concentration channel region of a first conductivity type having an impurity concentration lower than that of the semiconductor layer on the inner side, indium ions are ion-implanted into the semiconductor layer using the gate electrode as a mask, and a first region is formed in the lower region of the semiconductor layer A step of forming a conductive impurity layer, a step of subjecting the semiconductor substrate to a second heat treatment for a short time at a temperature of about 950 ° C. to about 1050 ° C., and a step of forming a sidewall on the side surface of the gate electrode Then, second conductivity type impurity ions are implanted into the second conductivity type first impurity layer and the first conductivity type impurity layer using the gate electrode and the side wall as a mask, so that the second conductivity type first impurity is implanted. A source region and a drain region made of a second conductivity type second impurity layer are formed in regions on both sides of the gate electrode in the impurity layer and the first conductivity type impurity layer, and the second conductivity type first impurity layer is formed. A second conductive type extension region is formed inside each upper region of the source region or drain region in the first region, and a second conductive type extension region is formed inside each lower region of the source region or drain region of the first conductive type impurity layer. And a step of forming a pocket region of conductivity type.

  According to the fifth method of manufacturing a semiconductor device, indium ions are ion-implanted to form a first conductivity type semiconductor layer serving as a channel region, and second conductivity type impurity ions are ion-implanted to form an extension region. And a step of performing a low-temperature long-time heat treatment performed at a temperature of about 600 ° C. to about 850 ° C. after forming the first impurity layer of the second conductivity type. Similar to the method, when the interstitial silicon atoms move toward the gate insulating film, the interstitial silicon atoms combine with indium ions existing in the lower regions on both sides of the gate insulating film in the semiconductor layer of the first conductivity type. Since the ions are inactivated, the concentration of the activation impurity in the region inside the first conductivity type semiconductor layer in the first conductivity type semiconductor layer is lower than that in the first conductivity type semiconductor layer. concentration It can be formed Yaneru region. Therefore, it is possible to reliably manufacture a semiconductor device having low-concentration channel regions in which the concentration of activating impurities is lower in the regions on both sides of the channel region than in the central portion of the channel region.

  In addition, since a first conductivity type impurity layer serving as a pocket region is formed by ion implantation of indium ions, a process for performing a high-temperature and short-time heat treatment performed at a temperature of about 950 ° C. to about 1050 ° C. is provided. As in the first method for manufacturing a semiconductor device, the peak position of the impurity concentration distribution in the pocket region can be made shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. . Accordingly, a semiconductor device having a pocket region spaced from the gate insulating film can be reliably manufactured.

A sixth method for manufacturing a semiconductor device according to the present invention includes a step of ion-implanting first conductivity type impurity ions into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer serving as a channel region; Forming a gate electrode on a semiconductor substrate through a gate insulating film; and implanting ions of atoms belonging to Group IV into the semiconductor layer using the gate electrode as a mask to form a first conductivity type in an upper region of the semiconductor layer Forming an amorphous layer, and implanting a second conductivity type impurity ion into the amorphous layer by using the gate electrode as a mask, and implanting the second conductivity type first impurity layer into the amorphous layer. And forming an insulating film over the entire surface of the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C., and inside the first impurity layer of the second conductivity type in the upper region of the semiconductor layer. First conductivity type having a lower impurity concentration than the semiconductor layer A step of forming a low-concentration channel region, a step of anisotropically etching the insulating film to form a sidewall on a side surface of the gate electrode, a first impurity layer of the second conductivity type, and a semiconductor layer; Then, the second conductivity type impurity ions are ion-implanted using the gate electrode and the side wall as a mask, and the second conductivity type is formed in regions on both sides of the gate electrode in the lower region of the second conductivity type first impurity layer and the semiconductor layer. Forming a source region and a drain region composed of a second impurity layer of the type, and extending an extension region of the second conductivity type inside each upper region of the source region or the drain region in the first impurity layer of the second conductivity type. Each forming step;
After removing the sidewalls, indium ions are ion-implanted into the semiconductor layer using the gate electrode as a mask to form a pocket region of the first conductivity type inside each lower region of the source region or drain region in the lower region of the semiconductor layer. And a process of performing.

  According to the sixth method for manufacturing a semiconductor device, a step of forming a first conductivity type semiconductor layer to be a channel region by ion implantation of indium ions, and ion implantation of ions of atoms belonging to Group IV are performed. A step of forming an amorphous layer in the upper region of the conductive type semiconductor layer, and forming a second conductive type first impurity layer to be an extension region by ion implantation of second conductive type impurity ions; And a step of performing a low-temperature long-time heat treatment performed at a temperature of about 600 ° C. to about 850 ° C., so that the second conductivity type in the semiconductor layer of the first conductivity type is the same as in the fourth method of manufacturing a semiconductor device. In the region inside the first impurity layer, a low-concentration channel region in which the concentration of the activation impurity is lower than that of the first conductivity type semiconductor layer can be efficiently formed.

  In addition, since a first conductivity type impurity layer serving as a pocket region is formed by ion implantation of indium ions, a process for performing a high-temperature and short-time heat treatment performed at a temperature of about 950 ° C. to about 1050 ° C. is provided. As in the first method for manufacturing a semiconductor device, the peak position of the impurity concentration distribution in the pocket region can be made shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. . Accordingly, a semiconductor device having a pocket region spaced from the gate insulating film can be reliably manufactured.

  Further, after forming an amorphous layer in the upper region of the first conductivity type semiconductor layer, the second conductivity type impurity ions are ion-implanted to form the second conductivity type first to be the extension region. Since the step of forming the impurity layer is provided, the distribution of the impurity concentration in the first impurity layer of the second conductivity type can be made steep as in the second method for manufacturing the semiconductor device, so that the resistance of the extension region can be reduced. Can be realized.

  A seventh method for manufacturing a semiconductor device according to the present invention includes a step of injecting indium ions into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer serving as a channel region; A step of forming a gate electrode through the gate insulating film, and ions of atoms belonging to group IV are ion-implanted into the semiconductor layer using the gate electrode as a mask to form a group IV atom ion-implanted layer in the upper region of the semiconductor layer A first heat treatment is performed on the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C. to activate the group IV atom ion implantation layer and the upper region of the semiconductor layer as compared with the semiconductor layer A step of forming a low-concentration impurity layer of a first conductivity type having a low impurity concentration, and injecting indium ions into the semiconductor layer using a gate electrode as a mask, and an impurity layer of the first conductivity type in a lower region of the semiconductor layer Forming a second conductivity type impurity ion in the upper region of the semiconductor layer by implanting ions of the second conductivity type into the semiconductor layer using the gate electrode as a mask. Forming a low-concentration channel region comprising a first-conductivity-type low-concentration impurity layer inside the first impurity layer of the type, and a short time at a temperature of about 950 ° C. to about 1050 ° C. And a step of forming a sidewall on the side surface of the gate electrode, and a second conductivity type first impurity layer and a first conductivity type impurity layer using the gate electrode and the sidewall as a mask. Two-conductivity type impurity ions are ion-implanted, and the second conductivity-type second impurity layer is implanted into regions on both sides of the gate electrode in the second conductivity-type first impurity layer and the first conductivity-type impurity layer. Source region and An in region is formed, a second conductivity type extension region is formed inside each upper region of the source region or drain region in the second conductivity type first impurity layer, and the source in the first conductivity type impurity layer is formed Forming a pocket region of the first conductivity type inside each lower region of the region or drain region.

  According to the seventh method for fabricating a semiconductor device, a step of forming a first conductivity type semiconductor layer to be a channel region by ion implantation of indium ions, and ion implantation of ions of atoms belonging to group IV to form group IV atoms The method includes a step of forming an ion implantation layer and a step of performing a first heat treatment for a long time at a temperature of about 600 ° C. to about 850 ° C. on the semiconductor substrate. A low-concentration channel region in which the concentration of the activation impurity is lower than that of the first conductivity type semiconductor layer can be efficiently formed in the inner region of the two conductivity type first impurity layer.

  In addition, since a first conductivity type impurity layer serving as a pocket region is formed by ion implantation of indium ions, a process for performing a high-temperature and short-time heat treatment performed at a temperature of about 950 ° C. to about 1050 ° C. is provided. In addition, the peak position of the impurity concentration distribution in the pocket region can be made shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. Accordingly, a semiconductor device having a pocket region spaced from the gate insulating film can be reliably manufactured.

  Also, after indium ions are ion-implanted to form a first conductivity type impurity layer to be a pocket region, second conductivity type impurity ions are ion-implanted to form a second conductivity type first impurity to be an extension region. Since the layer is formed, the channeling phenomenon of the second conductivity type impurity ions in the second conductivity type first impurity layer is suppressed. For this reason, since the impurity concentration distribution in the extension region composed of the first impurity layer of the second conductivity type becomes steep, the parasitic resistance value of the extension region is reduced and the short channel effect can be suppressed.

  According to the first semiconductor device, since the pocket region formed so as to be spaced from the gate insulating film is provided, it is possible to prevent a reduction in the driving power of the MOS transistor while suppressing the short channel effect. Is possible.

  According to the second semiconductor device, the low concentration channel region in which the concentration of the activation impurity is lower than that in the central portion of the channel region is provided in the regions on both sides of the channel region, so that the resistance of the extension region is reduced. Therefore, it is possible to prevent a reduction in driving power of the MOS transistor.

  According to the first or second method for manufacturing a semiconductor device, indium ions are ion-implanted to form a first conductivity type impurity layer that becomes a pocket region. Therefore, a pocket region spaced from the gate insulating film is formed. The first semiconductor device can be reliably manufactured.

  In particular, according to the method for manufacturing the second semiconductor device, after an amorphous layer is formed in the upper region of the first conductivity type semiconductor layer, the second conductivity type impurity ions are ion-implanted, and the extension is performed. Since the first impurity layer of the second conductivity type that forms the region is formed, the resistance of the extension region can be reduced, so that the driving capability of the MOS transistor can be improved.

  According to the third or fourth method of manufacturing a semiconductor device, indium ions are ion-implanted to form a first conductivity type semiconductor layer to be a channel region, and second conductivity type impurity ions are ion-implanted. And forming a second conductivity type first impurity layer serving as an extension region, followed by a low-temperature long-time heat treatment at a temperature of about 600 ° C. to about 850 ° C. A second semiconductor device having a low-concentration channel region in which the concentration of the activation impurity is lower than that in the central portion of the channel region can be reliably manufactured.

  In particular, according to the fourth method for fabricating a semiconductor device, before the step of forming the second impurity layer of the second conductivity type that becomes the extension region, ions of atoms belonging to Group IV are ion-implanted. Since the step of forming a porous layer is provided, the number of indium ions to be deactivated by bonding with interstitial silicon atoms increases, so that the concentration of activated impurities is lower than that of the first conductivity type semiconductor layer. A low concentration channel region can be formed efficiently.

  According to the fifth, sixth, or seventh method of manufacturing a semiconductor device, the gate insulating layer has a low concentration channel region having a lower concentration of the activated impurity than the central portion of the channel region in the regions on both sides of the channel region. A semiconductor device having a pocket region spaced from the film can be reliably manufactured.

  In particular, according to the sixth method for manufacturing a semiconductor device, the distribution of the impurity concentration in the first impurity layer of the second conductivity type can be made steep, so that the resistance of the extension region can be reduced.

  In particular, according to the seventh semiconductor device manufacturing method, the parasitic resistance value of the extension region can be reduced and the short channel effect can be suppressed.

(First embodiment)
A semiconductor device according to the first embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 1, a p ⁻ type well region 101 doped with a p type impurity such as boron ion is formed in a semiconductor substrate 100 made of a p type silicon substrate. Further, a gate electrode 104 made of a polysilicon film is formed on the semiconductor substrate 100 via a gate insulating film 103 made of, for example, a silicon oxide film. A side surface of the gate electrode 104 has, for example, a silicon oxide film A sidewall 107 made of is formed.

A p-type channel region 102 doped with a p-type impurity such as boron ion is formed in a region immediately below the gate electrode 104 in the surface portion of the semiconductor substrate 100, and the gate in the surface portion of the semiconductor substrate 100 is formed. In regions on both sides of the electrode 104, source or drain regions 108 made of an n ⁺ -type impurity active layer doped with an n-type impurity such as arsenic ions are formed.

An n ⁺ -type extension region 105 is formed between the channel region 102 and each upper region of the source or drain region 108 so as to be in contact with the source or drain region 108.

A p ⁺ -type pocket region 106 for punch-through suppression is formed between the channel region 102 and each lower region of the source or drain region 108 so as to be in contact with the source or drain region 108.

  As a feature of the first embodiment, the pocket region 106 is formed by doping with indium ions, and is formed so as to be spaced from the gate insulating film 103.

According to the first embodiment, the depletion layer extending from the n ⁺ -type extension region 105 is generated from the lower end portion of the extension region 105, but the p ⁺ -type pocket region 106 is formed below the extension region 105. Since it is formed, a depletion layer extending from the n ⁺ -type extension region 105 can be suppressed, so that the short channel effect can be suppressed.

Further, the p ⁺ type pocket region 106 is formed so as to be in contact with each lower region of the source or drain region 108 and to be spaced from the gate insulating film 103, that is, inside the extension region 105. Therefore, even if the impurity concentration of the pocket region 106 is increased to suppress the short channel effect, the impurity concentration of the extension region 105 does not decrease. For this reason, since the resistance of the extension region 105 does not increase, it is possible to suppress a decrease in driving force of the MOS transistor.

Since the p ⁺ type pocket region 106 is formed below the n ⁺ type extension region 105, that is, not in contact with the upper region of the channel region 102, the impurity concentration of the pocket region 106 is increased. However, the impurity concentration in the vicinity of the extension region 105 in the channel region 102 does not increase. For this reason, since it is possible to prevent the carrier mobility from being lowered due to carrier impurity scattering, it is possible to prevent a reduction in the driving power of the MOS transistor and to prevent the occurrence of the reverse short channel effect. .

(Second Embodiment)
A semiconductor device according to the second embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 2, a p ⁻ type well region 201 doped with a p type impurity such as boron ion is formed on a semiconductor substrate 200 made of a p type silicon substrate. A gate electrode 204 made of a polysilicon film is formed on the semiconductor substrate 200 via a gate insulating film 203 made of, for example, a silicon oxide film, and a side surface of the gate electrode 204 has, for example, a silicon oxide film A side wall 207 is formed.

A p-type channel region 202 doped with indium ions which are p-type impurities is formed in a region immediately below the gate electrode 204 in the surface portion of the semiconductor substrate 200, and in the surface portion of the semiconductor substrate 200. In regions on both sides of the gate electrode 204, a source or drain region 208 made of an n ⁺ -type impurity active layer doped with an n-type impurity such as arsenic ions is formed.

An n ⁺ -type extension region 205 is formed between the channel region 202 and each upper region of the source or drain region 208 so as to be in contact with the source or drain region 208.

As a feature of the second embodiment, p-type in the upper region on both sides in the channel region 202 of the low concentration of activated impurities in comparison with the central portion of the channel region 202 with is in contact with the extension regions 205 p ^- A low-concentration channel region 206 of the mold is formed.

Therefore, according to the second embodiment, the concentration of the activated impurity in the upper region of the channel region 202 is low concentration-high concentration-low concentration from the source side to the drain side or from the drain side to the source side. It has become. As described above, since the concentration of the activated impurity in the region in contact with the n ⁺ -type extension region 205 in the channel region 202 is low, the resistance of the extension region 205 is reduced, and thus the reduction in driving force of the MOS transistor can be prevented. it can.

(Third embodiment)
A semiconductor device according to the third embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 3, a p ⁻ type well region 301 doped with a p type impurity such as boron ion is formed in a semiconductor substrate 300 made of a p type silicon substrate. A gate electrode 304 made of a polysilicon film is formed on the semiconductor substrate 300 via a gate insulating film 303 made of, for example, a silicon oxide film, and a side surface of the gate electrode 304 has, for example, a silicon oxide film A side wall 308 made of is formed.

A p-type channel region 302 doped with indium ions which are p-type impurities is formed in a region immediately below the gate electrode 304 in the surface portion of the semiconductor substrate 300, and in the surface portion of the semiconductor substrate 300. In regions on both sides of the gate electrode 304, a source or drain region 309 made of an n ⁺ -type impurity active layer doped with an n-type impurity such as arsenic ions is formed.

An n ⁺ -type extension region 305 is formed between the channel region 302 and each upper region of the source or drain region 309 so as to be in contact with the source or drain region 309.

Third As a feature of the embodiment of, in the region of both side portions of the p-type channel region 302, the concentration of activated impurities in comparison with the central portion of the channel region 302 with is in contact with the extension regions 305 is lower p ^- type Each of the low concentration channel regions 306 is formed.

A p ⁺ -type pocket region 307 for punch-through suppression is formed between the channel region 302 and each lower region of the source or drain region 309 so as to be in contact with the source or drain region 309.

  As a feature of the third embodiment, the pocket region 307 is formed by doping with indium ions, and is formed so as to be spaced from the gate insulating film 303.

According to the third embodiment, since the p ⁺ type pocket region 307 is formed below the extension region 305 as in the first embodiment, the p ⁺ type pocket region 307 allows the n ⁺ type pocket region 307 to be formed. Since the depletion layer extending from the extension region 305 is suppressed, the short channel effect can be suppressed.

The p ⁺ -type pocket region 307 is formed so as to be in contact with each lower region of the region 309 to be a source or drain and to be spaced from the gate insulating film 303, that is, inside the extension region 305. Therefore, even if the impurity concentration of the pocket region 307 is increased to suppress the short channel effect, the impurity concentration of the extension region 305 does not decrease. For this reason, since the resistance of the extension region 305 does not increase, it is possible to suppress a decrease in the driving power of the MOS transistor.

Since the p ⁺ type pocket region 307 is formed below the n ⁺ type extension region 305, that is, not in contact with the upper region of the channel region 302, the impurity concentration of the pocket region 307 is increased. However, the impurity concentration in the vicinity of the extension region 305 in the channel region 302 does not increase. For this reason, since the carrier mobility is low due to the impurity scattering of the carriers, it is possible to prevent the situation, and it is possible to prevent the decrease in the driving power of the MOS transistor and the occurrence of the reverse short channel effect.

Further, according to the third embodiment, as in the second embodiment, the p-type channel region 302 has p-type channel regions 302 having a lower concentration of activation impurities in the upper region on both sides than the central portion of the channel region 302. ^{Since the −} type low concentration channel region 306 is formed, the impurity concentration in the upper region of the channel region 302 is low concentration—high concentration—from the source side to the drain side and from the drain side to the source type. The concentration is low. As described above, since the concentration of the activation impurity in the region in contact with the n ⁺ -type extension region 305 in the channel region 302 is low, the resistance of the extension region 305 can be reduced, so that a reduction in driving power of the MOS transistor can be prevented. it can.

(Fourth embodiment)
Hereinafter, a method for fabricating a semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. 4 (a) to 4 (c) and FIGS. 5 (a) to 5 (c). The fourth embodiment is a first method for manufacturing a semiconductor device according to the first embodiment.

First, as shown in FIG. 4A, a p-type impurity such as boron ion is implanted into a semiconductor substrate 100 made of a p-type silicon substrate at an energy of 300 keV to 2000 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. After the p ⁻ type well region 101 is formed by ion implantation with a dose of cm ⁻² , p type impurities such as boron ions are applied to the surface portion of the semiconductor substrate 100 at 20 keV to 60 keV and 4 × 10 ¹² cm ^−2. A p-type impurity layer 102A is formed on the well region 101 by ion implantation at a dose of ˜1 × 10 ¹³ cm ⁻² . Note that the p-type impurity layer 102 </ b> A may be formed on the surface portion of the semiconductor substrate 100 by implanting indium ions instead of boron ions as p-type impurities.

  Next, as shown in FIG. 4B, the surface of the semiconductor substrate 100 is oxidized to form a first silicon oxide film 103A having a thickness of 2 nm to 5 nm.

  Next, after depositing a polysilicon film having a thickness of 200 nm to 300 nm over the entire surface of the first silicon oxide film 103A, the polysilicon film and the first silicon oxide film 103A are patterned. As shown in FIG. 4C, the gate insulating film 103 and the gate electrode 104 are formed.

Next, as shown in FIG. 5A, n-type impurities such as arsenic ions, for example, with an implantation energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to the p-type impurity layer 102A using the gate electrode 104 as a mask. By ion implantation with a dose of 1 × 10 ¹⁵ cm ⁻² , an n ⁺ -type impurity layer 105A is formed in the upper region of the p-type impurity layer 102A.

Next, indium ions are implanted into the p-type impurity layer 102A using the gate electrode 104 as a mask with an implantation energy of 50 to 150 keV and a dose of 1 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ^−2. Thus, the p ⁺ -type impurity layer 106A is formed in the lower region of the p-type impurity layer 102A. Thereafter, the semiconductor substrate 100 is subjected to a heat treatment for 10 seconds at a temperature of, for example, 1000 ° C., that is, a first heat treatment for a short time at a high temperature in an inert gas atmosphere.

  Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 100, anisotropic etching is performed on the second silicon oxide film, as shown in FIG. As described above, the sidewall 107 is formed on the side surface of the gate electrode 104.

Next, after implanting n-type impurities such as arsenic ions into the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 106A, heat treatment is performed to activate the arsenic ions, and then the crystal point defects are recovered. In order to achieve this, a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a second heat treatment at a high temperature for a short time is performed.

As a result, as shown in FIG. 5C, the n ⁺ -type impurity active layers are formed in the regions on both sides of the gate electrode 104 in the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 106A. source or region 108 of the drain is formed, on the inside of the respective upper regions of the source and the drain regions 108 in the n ⁺ -type impurity layers 105A, together with the extension regions 105 composed of n ⁺ -type impurity layer 105A is formed, the source or the p ⁺ -type impurity layer 106A on the inner side of the lower region of the drain region 108, the pocket region 106 made of p ⁺ -type impurity layer 106A is formed.

According to the fourth embodiment, indium ions having an atomic mass larger than that of boron ions are ion-implanted to form the p ⁺ -type impurity layer 106A that becomes the p ⁺ -type pocket region 106. The peak position of the impurity concentration distribution can be made shallow, and the range in which the pocket region 106 expands can be suppressed. Further, at the time of thermal equilibrium, since the diffusion coefficient of indium ions is about half of the diffusion coefficient of boron ions, the diffusion of impurity ions due to thermal diffusion can be suppressed compared to the case where boron ions are implanted.

  By the way, although the diffusion coefficient of indium ions at the time of thermal equilibrium is smaller than that of boron ions, indium ions are as large as boron ions in terms of accelerated diffusion caused by point defects generated during ion implantation.

Therefore, in the fourth embodiment, immediately after the indium ions are ion-implanted to form the p ⁺ -type impurity layer 106A, the first heat treatment is performed at a high temperature for a short time, and the enhanced diffusion caused by point defects is performed. Occurrence is suppressed. Therefore, the expansion of the pocket region 106 made of the p ⁺ -type impurity layer 106A can be suppressed.

  Therefore, according to the fourth embodiment, the pocket region 106 can be formed so as to be in contact with each lower region of the source or drain region 108 and to be spaced from the gate insulating film 103. The semiconductor device according to the embodiment can be reliably manufactured.

  In the fourth embodiment, the first heat treatment for a short time at a high temperature is performed at a temperature of 1000 ° C. for 10 seconds. However, the present invention is not limited to this, and a temperature range of about 950 ° C. to about 1050 ° C. and about 0 In the time range of 1 second to about 30 seconds, the effect of suppressing the expansion of the pocket region 106 can be obtained. When the temperature of the first high-temperature short-time heat treatment is lower than about 950 ° C., point defects are generated, so that accelerated diffusion of indium ions occurs and the temperature of the first high-temperature short-time heat treatment is about When the temperature is higher than 1050 ° C., enhanced diffusion due to point defects does not occur, but indium ions themselves diffuse. Therefore, the temperature range of 950 ° C. to about 1050 ° C. is preferable for the first heat treatment at high temperature and short time.

By the way, in the ion implantation process for forming the p ⁺ -type impurity layer 106A to be the pocket region 106, when indium ions are ion-implanted with a dose amount larger than 5 × 10 ¹³ cm ⁻² , the silicon crystal becomes amorphous. Therefore, when heat treatment is performed after ion implantation, as shown in FIG. 6A, an EOR (End of Range) point defect 109 such as a transition loop is generated in the p ⁺ -type impurity layer 106A. End up. The EOR point defect 109 is generated almost independently of the temperature or time of the heat treatment after ion implantation, and once it is generated, it is difficult to completely disappear even if the heat treatment is performed thereafter. Therefore, as shown in FIG. 6B, even after the final MOS transistor is obtained, the EOR point defect 109 remains without disappearing.

  By the way, when a bias voltage is applied to the extension region 105 to operate the MOS transistor, the depletion layer expands from the extension region 105 toward the pocket region 106, but when the EOR point defect 109 exists in the pocket region 106, the depletion layer Reaches the EOR point defect 109, thereby generating a junction leakage current. If such a VLSI chip having a MOS transistor is incorporated in a mobile communication device, it is not preferable because power consumption during standby increases due to junction leakage current.

However, in the fourth embodiment, in the ion implantation process for forming the p ⁺ -type impurity layer 106A to be the pocket region 106, indium ions are implanted at a dose of 5 × 10 ¹³ cm ⁻² or less. Therefore, p ⁺ -type silicon crystal does not amorphization in impurity layer 106A of, since EOR point defects 109 in the impurity layer 106A of p ⁺ -type is not generated, the junction leakage current is less likely to occur.

(Fifth embodiment)
A semiconductor device manufacturing method according to the fifth embodiment of the present invention will be described below with reference to FIGS. 7 (a) to (c) and FIGS. 8 (a) to (c). The fifth embodiment is a second manufacturing method of the semiconductor device according to the first embodiment.

First, as shown in FIG. 6A, a p-type impurity such as boron ion is implanted into a semiconductor substrate 100 made of a p-type silicon substrate at an energy of 300 keV to 2000 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. After the p ⁻ type well region 101 is formed by ion implantation with a dose of cm ⁻² , p type impurities such as boron ions are applied to the surface portion of the semiconductor substrate 100 at 20 keV to 60 keV and 4 × 10 ¹² cm ^−2. A p-type impurity layer 102A is formed on the well region 101 by ion implantation at a dose of ˜1 × 10 ¹³ cm ⁻² .

  Next, as shown in FIG. 7B, the surface of the semiconductor substrate 100 is oxidized to form a first silicon oxide film 103A having a thickness of 2 nm to 5 nm.

  Next, after depositing a polysilicon film having a thickness of 200 nm to 300 nm over the entire surface of the first silicon oxide film 103A, the polysilicon film and the first silicon oxide film 103A are patterned. As shown in FIG. 7C, the gate insulating film 103 and the gate electrode 104 are formed.

Next, using the gate electrode 104 as a mask in the p-type impurity layer 102A, ions of atoms belonging to group IV, for example germanium ions, are implanted at an energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ^{−. 2} is ion-implanted to form a p-type amorphous layer 110 in the upper region of the p-type impurity layer 102A.

Next, as shown in FIG. 8A, an n-type impurity, for example, arsenic ions are implanted into the p-type amorphous layer 110 with a gate electrode 104 as a mask at an implantation energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ^−2. By ion implantation at a dose of ˜1 × 10 ¹⁵ cm ⁻² , an n ⁺ -type impurity layer 105A is formed in the amorphous layer 110.

Next, indium ions are implanted into the p-type impurity layer 102A using the gate electrode 104 as a mask with an implantation energy of 50 to 150 keV and a dose of 1 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ^−2. Thus, the p ⁺ -type impurity layer 106A is formed in the lower region of the p-type impurity layer 102A. Thereafter, the semiconductor substrate 100 is subjected to a heat treatment for 10 seconds at a temperature of, for example, 1000 ° C., that is, a first heat treatment for a short time at a high temperature in an inert gas atmosphere.

  Next, after a second silicon oxide film is deposited over the entire surface of the semiconductor substrate 100, anisotropic etching is performed on the second silicon oxide film, as shown in FIG. As described above, the sidewall 107 is formed on the side surface of the gate electrode 104.

Next, after implanting n-type impurities such as arsenic ions into the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 106A, heat treatment is performed to activate the arsenic ions, and then the crystal point defects are recovered. In order to achieve this, a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a second heat treatment at a high temperature for a short time is performed.

In this manner, as shown in FIG. 8C, the n ⁺ -type impurity active layer is formed in the regions on both sides of the gate electrode 104 in the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 106A. source or region 108 of the drain is formed, on the inside of the respective upper regions of the source and the drain regions 108 in the n ⁺ -type impurity layers 105A, together with the extension regions 105 composed of n ⁺ -type impurity layer 105A is formed, the source or the p ⁺ -type impurity layer 106A on the inner side of the lower region of the drain region 108, the pocket region 106 made of p ⁺ -type impurity layer 106A is formed.

According to the fifth embodiment, similarly to the fourth embodiment, indium ions atomic mass greater than the boron ions are implanted, the impurity layer 106A of p ⁺ -type which is a p ⁺ -type pocket regions 106 In addition, since the first heat treatment is performed for a short time at a high temperature after the indium ions are implanted, expansion of the pocket region 106 can be suppressed. Therefore, the p ⁺ -type impurity layer 106A to be the pocket region 106 can be formed so as to be spaced from the gate insulating film 103.

In the fifth embodiment, as in the fourth embodiment, indium ions are implanted at 5 × 10 ¹³ cm ^{−2 in} the ion implantation step for forming the p ⁺ -type impurity layer 106A that becomes the pocket region 106. to the following ion implanted at a dose, p ⁺ -type silicon crystal does not amorphization in impurity layer 106A of, since EOR point defects 109 in the impurity layer 106A of p ⁺ -type is not generated, the junction leakage current is generated It is hard to do.

However, distribution of the impurity concentration in the n ⁺ -type impurity layers 105A serving as extension region 105 is formed n ⁺ -type by ion implantation of arsenic ions hardly becomes steep.

Therefore, in the fifth embodiment, to form the n ⁺ -type impurity layers 105A germanium ions are implanted from left to form an amorphous layer 110. The arsenic ions are implanted, n ⁺ In the extension region 105 made of the type impurity layer 105A, the distribution of the impurity concentration becomes steep, so that the resistance of the extension region 105 can be reduced.

The germanium ion implantation position is shallower than the arsenic ion implantation position for forming the n ⁺ -type impurity layer 105A to be the extension region 105, so that the amorphous layer 110 becomes the n ⁺ -type impurity layer 105A. It is preferable not to expand below. In this case, as shown in FIG. 9A, the EOR point defect 109 generated by the subsequent heat treatment does not expand below the n ⁺ -type impurity layer 105A, that is, FIG. 9B. As shown in FIG. 5, the EOR point defect 109 does not occur in the pocket region 106.

  For this reason, when a bias voltage is applied to the extension region 105, even if the depletion layer expands from the extension region 105 toward the pocket region 106, the depletion layer reaches an EOR point defect and a junction leakage current occurs. Can be prevented.

  In the fifth embodiment, germanium ions are used as the ions for forming the amorphous layer 110. Instead, other ions belonging to the IV group such as silicon ions or carbon ions are used. The same effect can be obtained by using ions of these atoms.

(Sixth embodiment)
A semiconductor device manufacturing method according to the sixth embodiment of the present invention will be described below with reference to FIGS. 10 (a) to 10 (c) and FIGS. 11 (a) and 11 (b). The sixth embodiment is a first method for manufacturing a semiconductor device according to the second embodiment.

First, as shown in FIG. 10A, a p-type impurity such as boron ion is implanted into a semiconductor substrate 200 made of a p-type silicon substrate at an energy of 300 keV to 2000 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. After p ⁻ type well region 201 is formed by ion implantation at a dose of cm ⁻² , indium ions are implanted into the surface portion of semiconductor substrate 200 at 50 keV to 150 keV and 5 × 10 ¹² cm ⁻² to 1 × 10 ^14. A p-type impurity layer 202A is formed on the well region 201 by ion implantation with a dose of cm ⁻² .

  Next, after oxidizing the surface of the semiconductor substrate 200 to form a first silicon oxide film having a thickness of 2 nm to 5 nm, a thickness of 200 nm to 300 nm is formed on the entire surface of the first silicon oxide film. A polysilicon film having a thickness is deposited, and then the polysilicon film and the first silicon oxide film are patterned to form a gate insulating film 203 and a gate electrode 204 as shown in FIG.

Next, as shown in FIG. 10C, n-type impurities such as arsenic ions are implanted into the p-type impurity layer 202A using the gate electrode 204 as a mask and an implantation energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² . By ion implantation with a dose of 1 × 10 ¹⁵ cm ⁻² , an n ⁺ -type impurity layer 205A is formed in the upper region of the p-type impurity layer 202A.

Next, a second silicon oxide film is deposited over the entire surface of the semiconductor substrate 200 at a temperature of about 600 ° C. to about 850 ° C. for about 10 minutes to about 200 minutes, and then the second silicon oxide film is deposited. The oxide film is subjected to anisotropic etching to form a side wall 207 made of a second silicon oxide film on the side surface of the gate electrode 204 as shown in FIG. In this case, in the step of depositing the second silicon oxide film, the semiconductor substrate 200 has been subjected to the first heat treatment for a long time at a low temperature, and therefore in the upper region of the p-type impurity layer 202A. Inside the n ⁺ -type impurity layer 205A, a p ⁻ -type low-concentration channel region 206 having an activation impurity concentration lower than that of the p-type impurity layer 202A is formed.

Next, after implanting n-type impurities such as arsenic ions into the n ⁺ -type impurity layer 205A and the p-type impurity layer 202A, heat treatment is performed to activate the arsenic ions, and then crystal point defects are recovered. Therefore, a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a second heat treatment for a short time at high temperature is performed.

As a result, as shown in FIG. 11C, a source made of an n ⁺ -type impurity active layer is formed on both sides of the gate electrode 204 in the n ⁺ -type impurity layer 205A and the p-type impurity layer 202A. or with region 208 of the drain is formed, the source and the n ⁺ -type impurity layers 205A of the inside of the upper region of the drain region 208, the extension regions 205 composed of n ⁺ -type impurity layer 205A is formed.

According to the sixth embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A on the well region 201, and after the n ⁺ -type impurity layer 205A is formed, the semiconductor substrate 200 is cooled at a low temperature. since the subjected to long-time heat treatment, the inside of the p-type n ⁺ -type impurity layers 205A of the upper region of the impurity layer 202A of the concentration of the activated impurity than the impurity layer 202A of p-type low p ^- type The low-concentration channel region 206 can be formed. Hereinafter, a mechanism for forming the p ⁻ -type low concentration channel region 206 will be described.

  Indium ions are known to bind to and deactivate interstitial silicon (see, for example, P. Bouillonet al., “Anomalus short channel effects in Indium implanted nMOSFETs”, Digest of Tech. Report of IEDM, pp. -, 1997).

The interstitial silicon atoms generated inside the p-type impurity layer 202A when the n ⁺ -type impurity layer 205A is formed by ion implantation of arsenic ions are converted into a gate insulating film by a low-temperature and long-time heat treatment performed thereafter. Move toward 203.

According to the sixth embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A, and therefore, the lower regions (in contact with the extension regions 205) on both sides of the gate insulating film 203 in the p-type impurity layer 202A. Indium ions existing in the region) are inactivated by being bonded to interstitial silicon atoms that have moved from the n ⁺ -type impurity layer 205A toward the gate insulating film 203, so that the gate insulation in the p-type impurity layer 202A is inactivated. The concentration of the activation impurity is lower in the lower region on both sides of the film 203, that is, in the region inside the n ⁺ -type impurity layer 205A in the upper region of the p-type impurity layer 202A than in the p-type impurity layer 202A. A p ⁻ -type low-concentration channel region 206 is formed.

  In the sixth embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A to be the channel region 202. For the reason described below, carrier movement in the channel region 202 is performed. Degradation can be prevented. That is, indium ions have a larger atomic mass than boron ions, and therefore have a concentration distribution peak in the lower region of the p-type impurity layer 202A, so that a so-called retrograde channel whose concentration decreases toward the surface is formed. can do. For this reason, since the mobility of carriers in the channel region is unlikely to decrease, the driving capability of the MOS transistor can be improved.

(Seventh embodiment)
A semiconductor device manufacturing method according to the seventh embodiment of the present invention will be described below with reference to FIGS. 12 (a) to 12 (c) and FIGS. 13 (a) to 13 (c). The seventh embodiment is a second method for manufacturing a semiconductor device according to the second embodiment.

First, as shown in FIG. 12A, a p-type impurity such as boron ion is implanted into a semiconductor substrate 200 made of a p-type silicon substrate at an energy of 300 keV to 2000 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. After p ⁻ type well region 201 is formed by ion implantation at a dose of cm ⁻² , indium ions are implanted into the surface portion of semiconductor substrate 200 at 50 keV to 150 keV and 5 × 10 ¹² cm ⁻² to 1 × 10 ^14. A p-type impurity layer 202A is formed on the well region 201 by ion implantation with a dose of cm ⁻² .

  Next, after oxidizing the surface of the semiconductor substrate 200 to form a first silicon oxide film having a thickness of 2 nm to 5 nm, a thickness of 200 nm to 300 nm is formed on the entire surface of the first silicon oxide film. A polysilicon film having a thickness is deposited, and then the polysilicon film and the first silicon oxide film are patterned, thereby forming a gate insulating film 203 and a gate electrode 204 as shown in FIG.

Next, as shown in FIG. 12C, with the gate electrode 204 as a mask in the p-type impurity layer 202A, ions of atoms belonging to group IV, such as germanium ions, are implanted at an energy of 5 keV to 10 keV and 5 × 10 ^14. Ions are implanted at cm ⁻² to 1 × 10 ¹⁵ cm ⁻² to form a p-type amorphous layer 210 in the upper region of the p-type impurity layer 102A.

Next, as shown in FIG. 13A, an n-type impurity such as arsenic ions is implanted into the p-type amorphous layer 210 using the gate electrode 204 as a mask at an implantation energy of 5 to 10 keV and 5 × 10 ¹⁴ cm ^−2. By ion implantation with a dose of ˜1 × 10 ¹⁵ cm ⁻² , an n ⁺ -type impurity layer 205 A is formed in the amorphous layer 210.

Next, a second silicon oxide film is deposited over the entire surface of the semiconductor substrate 200 at a temperature of about 600 ° C. to about 850 ° C. for about 10 minutes to about 200 minutes, and then the second silicon oxide film is deposited. The oxide film is anisotropically etched to form a side wall 207 made of a second silicon oxide film on the side surface of the gate electrode 204 as shown in FIG. In this case, in the step of depositing the second silicon oxide film, the semiconductor substrate 200 has been subjected to the first heat treatment for a long time at a low temperature, and therefore in the upper region of the p-type impurity layer 202A. Inside the n ⁺ -type impurity layer 205A, a p ⁻ -type low-concentration channel region 206 having an activation impurity concentration lower than that of the p-type impurity layer 202A is formed.

Next, after implanting n-type impurities such as arsenic ions into the n ⁺ -type impurity layer 205A and the p-type impurity layer 202A, heat treatment is performed to activate the arsenic ions, and then crystal point defects are recovered. Therefore, a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a second heat treatment at a high temperature for a short time is performed.

As a result, as shown in FIG. 13C, a source made of an n ⁺ -type impurity active layer is formed in regions on both sides of the gate electrode 204 in the n ⁺ -type impurity layer 205A and the p-type impurity layer 202A. or with region 208 of the drain is formed, the source and the n ⁺ -type impurity layers 205A of the inside of the upper region of the drain region 208, the extension regions 205 composed of n ⁺ -type impurity layer 205A is formed.

According to the seventh embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A, and after the n ⁺ -type impurity layer 205A is formed, the semiconductor substrate 200 is subjected to a low-temperature long-time heat treatment. Therefore, the p ⁻ -type low-concentration channel region 206, which has a lower concentration of activation impurities than the p-type impurity layer 202 A, is located inside the n ⁺ -type impurity layer 205 A in the upper region of the p-type impurity layer 202 A. Is formed. The mechanism by which the p ⁻ -type low concentration channel region 206 is formed is the same as in the sixth embodiment.

In the seventh embodiment, arsenic ions are ion-implanted to form the n ⁺ -type impurity layer 205A, and germanium ions are ion-implanted to form the amorphous layer 210. Since the number of interstitial silicon atoms generated inside the p-type impurity layer 202A is increased as compared to the case of the sixth embodiment (when germanium ions are not implanted), the p-type impurity layer 202A is increased. The bond between indium ions existing in the lower region of both sides of the gate insulating film 203 and interstitial silicon atoms is increased as compared with the case of the sixth embodiment. Therefore, one layer of indium ions is present in the lower region of both sides of the gate insulating film 203 in the p-type impurity layer 202A, that is, in the region inside the n ⁺ -type impurity layer 205A in the upper region of the p-type impurity layer 202A. Since it is inactivated, the p ⁻ -type low concentration channel region 206 can be formed more efficiently.

In the seventh embodiment, germanium ions are ion-implanted to form the amorphous layer 210, and then arsenic ions are ion-implanted to form the n ⁺ -type impurity layer 205A. Since the extension region 205 including the ⁺ -type impurity layer 205A is steep, the resistance of the extension region 205 can be reduced.

  Furthermore, in the seventh embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A that becomes the channel region 202, so that a so-called retrograde channel is formed as in the sixth embodiment. Therefore, a decrease in carrier mobility in the channel region 202 can be prevented.

(Eighth embodiment)
A semiconductor device manufacturing method according to the eighth embodiment of the present invention will be described below with reference to FIGS. 14 (a) to 14 (c) and FIGS. 15 (a) to 15 (c). The eighth embodiment is a first method for manufacturing a semiconductor device according to the third embodiment.

First, as shown in FIG. 14A, a p-type impurity such as boron ion is implanted into a semiconductor substrate 300 made of a p-type silicon substrate at an energy of 300 keV to 2000 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. After the p ⁻ type well region 301 is formed by ion implantation with a dose of cm ⁻² , indium ions are implanted into the surface portion of the semiconductor substrate 300 at 50 keV to 150 keV and 5 × 10 ¹² cm ⁻² to 1 × 10 ^14. By implanting ions with a dose of cm ⁻² , a p-type impurity layer 302 A is formed on the well region 301.

  Next, after oxidizing the surface of the semiconductor substrate 300 to form a first silicon oxide film having a thickness of 2 nm to 5 nm, a thickness of 200 nm to 300 nm is formed on the entire surface of the first silicon oxide film. A polysilicon film having a thickness is deposited, and then the polysilicon film and the first silicon oxide film are patterned, thereby forming a gate insulating film 303 and a gate electrode 304 as shown in FIG.

Next, as shown in FIG. 14C, n-type impurities such as arsenic ions, for example, with an implantation energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to the p-type impurity layer 302A using the gate electrode 304 as a mask. By ion implantation at a dose of 1 × 10 ¹⁵ cm ⁻² , an n ⁺ -type impurity layer 305A is formed in the upper region of the p-type impurity layer 302A.

Next, the semiconductor substrate 300 is subjected to a heat treatment at a temperature of about 600 ° C. to about 850 ° C. for a time of about 10 minutes to about 200 minutes, that is, a first heat treatment at a low temperature and a long time, whereby FIG. As shown, a p ⁻ type low concentration channel region 306 having an impurity concentration lower than that of the p type impurity layer 302A is formed inside the n ⁺ type impurity layer 305A in the upper region of the p type impurity layer 302A.

Next, indium ions are implanted into the p-type impurity layer 302A using the gate electrode 304 as a mask at an implantation energy of 50 to 150 keV and a dose of 5 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ^−2. As a result, ap ⁺ -type impurity layer 307A is formed in the lower region of the p-type impurity layer 302A. Thereafter, the semiconductor substrate 300 is subjected to a heat treatment for 10 seconds at a temperature of, for example, 1000 ° C., that is, a second heat treatment at a high temperature and a short time in an inert gas atmosphere.

  Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 300, anisotropic etching is performed on the second silicon oxide film, whereby the structure shown in FIG. Thus, the sidewall 308 is formed on the side surface of the gate electrode 304.

Next, after implanting n-type impurities such as arsenic ions into the n ⁺ -type impurity layer 305A and the p ⁺ -type impurity layer 307A, heat treatment is performed to activate the arsenic ions, and then the crystal point defects are recovered. In order to achieve this, a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a third heat treatment for a short time at a high temperature is performed.

As a result, as shown in FIG. 15C, the n ⁺ -type impurity active layers are formed in regions on both sides of the gate electrode 304 in the n ⁺ -type impurity layer 305A and the p ⁺ -type impurity layer 306A. source or region 309 of the drain is formed, on the inside of the respective upper regions of the n ⁺ -type drain region 308 is the source or in the impurity layer 305A of, together with the extension regions 305 consisting of the impurity layer 305A of n ⁺ -type are formed, the source or the p ⁺ -type impurity layer 307A of the inside of the lower region of the drain region 308, the pocket region 307 consisting of the impurity layer 307A of p ⁺ -type are formed.

According to the eighth embodiment, indium ions are ion-implanted to form the p-type impurity layer 302A, and the semiconductor substrate 300 is subjected to low-temperature and long-time heat treatment after the n ⁺ -type impurity layer 305A is formed. applying for and a process, the inside of the impurity layer 305A of the n ⁺ -type in the upper region of the p-type impurity layer 302A, the p-type concentration of activated impurities in comparison with the impurity layer 302A low p of ^- type A lightly doped channel region 306 can be formed. The mechanism for forming the p ⁻ -type low concentration channel region 306 is the same as that in the sixth embodiment.

Further, according to the eighth embodiment, in the same manner as in the fourth embodiment, indium ions having an atomic mass larger than that of boron ions are ion-implanted to form a p ⁺ -type impurity layer 307A that becomes a pocket region 307. Since the second heat treatment at a high temperature for a short time is performed later, the generation of accelerated diffusion due to point defects is suppressed, so that the expansion of the pocket region 307 made of the p ⁺ -type impurity layer 307A can be suppressed. it can. Accordingly, the p ⁺ -type impurity layer 307A to be the pocket region 307 can be formed so as to be spaced from the gate insulating film 303.

  In the eighth embodiment, the first high-temperature and short-time heat treatment is performed at a temperature of 1000 ° C. for 10 seconds. However, the present invention is not limited to this, and the temperature range is about 950 ° C. to about 1050 ° C. and about 0 In the time range of 1 second to about 30 seconds, the effect of suppressing the expansion of the pocket region 307 can be obtained.

  Furthermore, in the eighth embodiment, indium ions are ion-implanted to form the p-type impurity layer 302A that becomes the channel region 302, so that a so-called retrograde channel is formed as in the sixth embodiment. Thus, a decrease in carrier mobility in the channel region 302 can be prevented.

(Ninth embodiment)
A semiconductor device manufacturing method according to the ninth embodiment of the present invention will be described below with reference to FIGS. 16 (a) to 16 (c) and FIGS. 17 (a) to 17 (c). The ninth embodiment is a second method for manufacturing a semiconductor device according to the third embodiment.

First, as shown in FIG. 16A, a p-type impurity such as boron ion is implanted into a semiconductor substrate 300 made of a p-type silicon substrate at an energy of 300 keV to 2000 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. After the p ⁻ type well region 301 is formed by ion implantation with a dose of cm ⁻² , indium ions are implanted into the surface portion of the semiconductor substrate 300 at 20 keV to 200 keV and 4 × 10 ¹² cm ⁻² to 1 × 10 ^13. By implanting ions with a dose of cm ⁻² , a p-type impurity layer 302 A is formed on the well region 301.

  Next, after oxidizing the surface of the semiconductor substrate 300 to form a first silicon oxide film having a thickness of 2 nm to 5 nm, a thickness of 200 nm to 300 nm is formed on the entire surface of the first silicon oxide film. A polysilicon film having a thickness is deposited, and then the polysilicon film and the first silicon oxide film are patterned to form a gate insulating film 303 and a gate electrode 304 as shown in FIG.

Next, using the gate electrode 304 as a mask on the p-type impurity layer 302A, ions of atoms belonging to group IV, for example germanium ions, are implanted at an energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ^{−. 2} is ion-implanted to form a p-type amorphous layer 310 in the upper region of the p-type impurity layer 302A.

Next, as shown in FIG. 16C, an n-type impurity such as arsenic ions is implanted with an energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to 1 with the gate electrode 304 as a mask in the amorphous layer 310. By ion implantation at a dose of × 10 ¹⁵ cm ⁻² , an n ⁺ -type impurity layer 305 A is formed in the amorphous layer 310.

Next, a second silicon oxide film is deposited over the entire surface of the semiconductor substrate 300 at a temperature of about 600 ° C. to about 850 ° C. for about 10 minutes to about 200 minutes, and then the second silicon oxide film is deposited. The oxide film is anisotropically etched to form a sidewall 308 made of a second silicon oxide film on the side surface of the gate electrode 304 as shown in FIG. In this way, in the step of depositing the second silicon oxide film, the semiconductor substrate 300 has been subjected to the first heat treatment for a long time at a low temperature, and therefore in the upper region of the p-type impurity layer 302A. Inside the n ⁺ -type impurity layer 305A, a p ⁻ -type low-concentration channel region 306 having a lower concentration of activation impurities than the p-type impurity layer 302A is formed.

Next, as shown in FIG. 17B, n-type impurities such as arsenic ions are ion-implanted into the n ⁺ -type impurity layer 305A and the p-type impurity layer 302A, so that the n ⁺ -type impurity layers 305A and p on both sides of the region of the gate electrode 304 in the mold of the impurity layer 302A, also a source consisting of n ⁺ -type impurity layer to form a region 309 of the drain, n ⁺ -type source or drain region 309 in impurity layer 305A of An extension region 305 composed of an n ⁺ -type impurity layer 305A is formed inside each upper region.

Next, as shown in FIG. 17C, after the sidewall 308 is removed, indium ions are implanted into the p-type impurity layer 302A as a mask with an implantation energy of 100 to 200 keV and 1 × 10 ¹³ cm. By ion implantation at a dose of ⁻² to 4 × 10 ¹³ cm ⁻² , a p ⁺ type is formed below the extension region 305 and inside the source or drain region 309 in the lower region of the p type impurity layer 302A. The pocket region 307 is formed.

  Next, the semiconductor substrate 300 is subjected to, for example, a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a second heat treatment for a short time at a high temperature to activate the arsenic ions in the source or drain region 309 and Recover defects.

In the ninth embodiment, a step of implanting indium ions to form a p-type impurity layer 302A, a step of implanting germanium ions to form an amorphous layer 310, and an n ⁺ -type impurity And after the formation of the layer 305A, the semiconductor substrate 300 is subjected to a low-temperature and long-time heat treatment. Therefore, as in the seventh embodiment, the n ⁺ -type impurity in the upper region of the p-type impurity layer 302A is provided. A p ⁻ -type low concentration channel region 306 having a lower concentration of activation impurities than the p-type impurity layer 302A can be efficiently formed inside the layer 305A.

According to the ninth embodiment, germanium ions are implanted to form the amorphous layer 310 and then arsenic ions are implanted to form the n ⁺ -type impurity layer 305A. ^{Since the} impurity concentration distribution in the extension region 305 including the ⁺ -type impurity layer 305A becomes steep, the resistance of the extension region 305 can be reduced.

In addition, according to the ninth embodiment, as in the fourth embodiment, indium ions having an atomic mass larger than that of boron ions are ion-implanted to form the p ⁺ type pocket region 307 for a short time at a high temperature. Since the second heat treatment is performed, the expansion of the pocket region 307 can be suppressed. Accordingly, the p ⁺ -type impurity layer 307A to be the pocket region 307 can be formed so as to be spaced from the gate insulating film 303.

  Furthermore, in the ninth embodiment, indium ions are ion-implanted to form the p-type impurity layer 302A that becomes the channel region 302, so that a so-called retrograde channel is formed as in the sixth embodiment. Thus, a decrease in carrier mobility in the channel region 302 can be prevented.

(Tenth embodiment)
A semiconductor device manufacturing method according to the tenth embodiment of the present invention will be described below with reference to FIGS. 18 (a) to 18 (c) and FIGS. 19 (a) to 19 (c). The tenth embodiment is a third method for manufacturing a semiconductor device according to the third embodiment.

First, as shown in FIG. 18A, a p-type impurity such as boron ion is implanted into a semiconductor substrate 300 made of a p-type silicon substrate at an energy of 300 keV to 2000 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. After the p ⁻ type well region 301 is formed by ion implantation with a dose of cm ⁻² , indium ions are implanted into the surface portion of the semiconductor substrate 300 at 20 keV to 200 keV and 4 × 10 ¹² cm ⁻² to 1 × 10 ^13. By implanting ions with a dose of cm ⁻² , a p-type impurity layer 302 A is formed on the well region 301.

  Next, after oxidizing the surface of the semiconductor substrate 300 to form a first silicon oxide film having a thickness of 2 nm to 5 nm, a thickness of 200 nm to 300 nm is formed on the entire surface of the first silicon oxide film. A polysilicon film having a thickness is deposited, and then the polysilicon film and the first silicon oxide film are patterned to form a gate insulating film 303 and a gate electrode 304 as shown in FIG.

Next, using the gate electrode 304 as a mask on the p-type impurity layer 302A, ions of atoms belonging to group IV, such as silicon ions, are implanted at an energy of 5 keV to 10 keV and 1 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁴ cm ^{−. 2} is ion-implanted to form a silicon implantation layer 311 in the upper region of the p-type impurity layer 302A.

Next, by subjecting the semiconductor substrate 300 to a heat treatment at a temperature of about 600 ° C. to about 850 ° C. for about 10 minutes to about 200 minutes, that is, a first heat treatment at a low temperature and a long time, FIG. As shown, a p ⁻ -type low-concentration impurity layer 306A having a lower concentration of activation impurities than the p-type impurity layer 302A is formed across the upper region of the silicon implantation layer 311 and the upper region of the p-type impurity layer 302A. Form.

Next, as shown in FIG. 19B, with the gate electrode 304 as a mask in the p-type impurity layer 302A, indium ions are implanted with an energy of 50 to 200 keV and 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm. By implanting ions at a dose of ^−2, a p ⁺ -type impurity layer 307A is formed in the lower region of the p-type impurity layer 302A.

Next, using the gate electrode 304 as a mask in the p ⁻ type low-concentration impurity layer 306A and the p type impurity layer 302A, an n type impurity such as arsenic ions is implanted at 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to 5 × 10 ¹⁴ cm ⁻² . By ion implantation with a dose of 1 × 10 ¹⁵ cm ⁻² , an n ⁺ -type impurity layer 305A is formed in the upper region of the p ⁻ -type low concentration impurity layer 306A and the p-type impurity layer 302A, and then For example, the semiconductor substrate 300 is subjected to a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a second heat treatment for a short time at a high temperature.

  Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 300, anisotropic etching is performed on the second silicon oxide film, as shown in FIG. Thus, the sidewall 308 is formed on the side surface of the gate electrode 304.

Next, after implanting n-type impurities such as arsenic ions into the n ⁺ -type impurity layer 305A and the p ⁺ -type impurity layer 307A, heat treatment is performed to activate the arsenic ions, and then the crystal point defects are recovered. In order to achieve this, a heat treatment for 10 seconds at a temperature of 1000 ° C., that is, a third heat treatment for a short time at a high temperature is performed.

As a result, as shown in FIG. 8C, the n ⁺ -type impurity active layer is formed in the regions on both sides of the gate electrode 304 in the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 307A. source or region 309 of the drain is formed, on the inside of the respective upper regions of the n ⁺ -type drain region 309 is the source or in the impurity layer 305A of, together with the extension regions 305 consisting of the impurity layer 305A of n ⁺ -type are formed, the source or the p ⁺ -type impurity layer 307A of the inside of the lower region of the drain region 309, the pocket region 307 consisting of the impurity layer 307A of p ⁺ -type are formed.

According to the tenth embodiment, indium ions are ion-implanted to form a p-type impurity layer 302A, silicon ions are ion-implanted to form a silicon implanted layer 311; And a step of performing a first heat treatment at a low temperature for a long time. Therefore, a p ⁻ -type low concentration in the upper region of the p-type impurity layer 302A is lower than that of the p-type impurity layer 302A. The concentration impurity layer 306A can be formed efficiently. The mechanism for forming the p ⁻ -type low-concentration impurity layer 306A is the same as that in the sixth embodiment.

Further, according to the tenth embodiment, indium ions having an atomic mass larger than that of boron ions are ion-implanted to form the p ⁺ -type impurity layer 307A that becomes the pocket region 307, immediately after the second high-temperature second time. Therefore, the expansion of the p ⁺ -type impurity layer 307A that becomes the pocket region 307 can be suppressed. Accordingly, the p ⁺ -type impurity layer 307A to be the pocket region 307 can be formed so as to be spaced from the gate insulating film 303.

In the tenth embodiment, indium ions are ion-implanted to form a p ⁺ -type impurity layer 307A to be a pocket region 307, and then arsenic ions are ion-implanted to form an n ⁺ -type impurity region 305. Since the impurity layer 305A is formed, the channeling phenomenon of arsenic ions in the n ⁺ -type impurity layer 305A is suppressed. For this reason, since the impurity concentration distribution in the extension region 305 made of the n ⁺ -type impurity layer 305A becomes steep, the parasitic resistance value of the extension region 305 is reduced and the short channel effect can be suppressed.

  Further, in the tenth embodiment, indium ions are ion-implanted to form the p-type impurity layer 302A that becomes the channel region 302, so that a so-called retrograde channel is formed as in the sixth embodiment. Thus, a decrease in carrier mobility in the channel region 302 can be prevented.

  According to the first or second semiconductor device, the driving power of the MOS transistor can be improved.

  According to the first or second method for manufacturing a semiconductor device, a semiconductor device having an improved MOS transistor driving capability can be reliably manufactured.

  According to the third or fourth method for manufacturing a semiconductor device, a semiconductor device having a low-concentration channel region in which the concentration of the activation impurity is lower than that in the central portion of the channel region is reliably manufactured in both sides of the channel region. can do.

  According to the fifth, sixth, or seventh method of manufacturing a semiconductor device, the gate insulating layer has a low concentration channel region having a lower concentration of the activated impurity than the central portion of the channel region in the regions on both sides of the channel region. A semiconductor device having a pocket region spaced from the film can be reliably manufactured.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. (A), (b) is sectional drawing explaining the trouble of the manufacturing method of the conventional semiconductor device. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 5th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 5th Embodiment of this invention. (A), (b) is sectional drawing explaining the effect of the manufacturing method of the semiconductor device which concerns on the 5th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 6th Embodiment of this invention. (A), (b) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 6th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 7th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 7th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 8th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 8th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 9th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 9th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 10th Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 10th Embodiment of this invention. It is sectional drawing which shows the conventional semiconductor device.

Explanation of symbols

100 semiconductor substrate 101 well region 102A p-type impurity layer 102 channel region 103 gate insulating film 103A first silicon oxide film 104 gate electrode 105A n ⁺ type impurity layer 105 extension region 106A p ⁺ type impurity layer 106 pocket region 107 Side wall 108 Source or drain region 109 EOR defect 110 Amorphous layer 200 Semiconductor substrate 201 Well region 202 Channel region 202A p-type impurity layer 203 Gate insulating film 204 Gate electrode 205A n ⁺ type impurity layer 205 Extension region 206 Low Concentration channel region 207 Side wall 208 Source or drain region 210 Amorphous layer 300 Semiconductor substrate 301 Well region 302 Channel region 302A p-type impurity layer 30 The gate insulating film 304 gate electrode 305A n ⁺ -type impurity layer 305 extension region 306 the low concentration channel region 307A p ⁺ -type impurity layer 307 pocket regions 308 sidewall 309 source or drain region 310 amorphous layer 311 silicon implanted layer of the

Claims (13)

A gate electrode formed on a semiconductor substrate made of silicon crystal via a gate insulating film;
A channel region made of a first impurity layer of a first conductivity type formed in a region immediately below the gate electrode in the surface portion of the semiconductor substrate;
A source region and a drain region made of a second impurity layer of a second conductivity type formed in regions on both sides of the gate electrode in the surface portion of the semiconductor substrate;
An extension region composed of a third impurity layer of the second conductivity type formed between the channel region and each upper region of the source region and the drain region so as to be in contact with the source region or the drain region; ,
The formed by implanted indium ions in the semiconductor substrate on the lower side of the extension region, between the channel region and the source region and the lower region of the drain region, and in contact with the source region or the drain region and a pocket region a fourth impurity layer of the first conductivity type formed so as spaced between the gate insulating film,
The third impurity layer is in contact with an upper region of the first impurity layer;
The semiconductor device, wherein the fourth impurity layer is in contact with a lower region of the first impurity layer. The semiconductor device according to claim 1, wherein a dose amount of indium ions in the pocket region is 5 × 10 ¹³ cm ⁻² or less. 2. The semiconductor device according to claim 1, wherein a dose amount of indium ions in the pocket region is 1 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ⁻² . 4. The semiconductor device according to claim 1, wherein a dose amount of impurity ions in the channel region is 4 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ^−2. . The semiconductor device according to claim 1, wherein the first impurity layer is doped with boron ions. A first conductivity type well region formed on the semiconductor substrate;
6. The channel region according to claim 1, wherein the channel region is formed in a surface portion of the semiconductor substrate on the well region and has a higher impurity ion concentration than the well region. A semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the channel region is made of boron ions or indium ions. A step (a) of forming a first conductivity type first impurity layer serving as a channel region by implanting first conductivity type impurity ions into a surface portion of a semiconductor substrate made of silicon crystal;
After the step (a), a step (b) of forming a gate electrode on the semiconductor substrate via a gate insulating film;
A step of forming a second conductivity type third impurity layer in an upper region of the first impurity layer by ion-implanting second conductivity type impurity ions into the first impurity layer using the gate electrode as a mask. (C),
After the step (c), indium ions are ion-implanted into the first impurity layer using the gate electrode as a mask, and a first conductivity type fourth impurity layer is formed in a lower region of the first impurity layer. Forming (d);
After the step (d), a step (e) of performing a short heat treatment on the semiconductor substrate at a temperature of about 950 ° C. to about 1050 ° C .;
After the step (e), a step (f) of forming a sidewall on the side surface of the gate electrode;
The third impurity layer and the fourth impurity layer are ion-implanted into the third impurity layer and the fourth impurity layer using the gate electrode and the sidewalls as a mask, so that the third impurity layer and the fourth impurity layer are implanted. Forming a source region and a drain region made of a second impurity layer of a second conductivity type in regions on both sides of the gate electrode in the layer, contacting the inner side of each upper region of the source region or the drain region; A second conductivity type extension region comprising three impurity layers, and a fourth impurity layer comprising the fourth impurity layer in contact with the inside of each lower region of the source region or the drain region below the extension region . Forming a pocket region of one conductivity type (g),
The third impurity layer is formed in contact with an upper region of the first impurity layer;
The method of manufacturing a semiconductor device, wherein the fourth impurity layer is formed in contact with a lower region of the first impurity layer. The method for manufacturing a semiconductor device according to claim 8 , wherein a dose of the indium ions in the step (d) is 5 × 10 ¹³ cm ⁻² or less. 9. The method of manufacturing a semiconductor device according to claim 8 , wherein a dose amount of the indium ions in the step (d) is 1 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ⁻² . Dose of the impurity ions in the step (a), according to any one of claims 8-10, which is a ^{4 × 10 12 cm -2 ~1 ×} 10 13 cm -2 Semiconductor device manufacturing method. The method for manufacturing a semiconductor device according to claim 8, wherein the impurity ions in the step (a) are boron ions. A step (a) of implanting a first conductivity type impurity ion into a surface portion of a semiconductor substrate to form a first conductivity type first impurity layer serving as the channel region;
After the step (a), a step (b) of forming a gate electrode on the semiconductor substrate via a gate insulating film;
A step of implanting ions of atoms belonging to Group IV into the first impurity layer using the gate electrode as a mask to form an amorphous layer of a first conductivity type in an upper region of the first impurity layer ( c) and
(D) forming a second conductivity type third impurity layer in the amorphous layer by ion-implanting second conductivity type impurity ions into the amorphous layer using the gate electrode as a mask;
Indium ions having a dose amount of 5 × 10 ¹³ cm ⁻² or less are ion-implanted into the first impurity layer using the gate electrode as a mask, and a first conductivity type fourth region is formed in a lower region of the first impurity layer. A step (e) of forming an impurity layer of
After the step (e), a step (f) of performing a short heat treatment on the semiconductor substrate at a temperature of about 950 ° C. to about 1050 ° C .;
After the step (f), a step (g) of forming a sidewall on the side surface of the gate electrode;
The third impurity layer and the fourth impurity layer are ion-implanted into the third impurity layer and the fourth impurity layer using the gate electrode and the sidewalls as a mask, so that the third impurity layer and the fourth impurity layer are implanted. Forming a source region and a drain region made of a second impurity layer of the second conductivity type in regions on both sides of the gate electrode in the layer, and forming the third region inside each upper region of the source region or the drain region. Forming a second conductivity type extension region made of an impurity layer and forming a first conductivity type pocket region made of the fourth impurity layer inside each lower region of the source region or the drain region ( h), and
The third impurity layer is formed in contact with an upper region of the first impurity layer;
The method of manufacturing a semiconductor device, wherein the fourth impurity layer is formed in contact with a lower region of the first impurity layer.

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