JP4080658B2 - Encoding / decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an encoding / decoding device suitable for a device using image data compression or a device for compressing / decompressing image data, such as a facsimile device, a scanner device, a digital camera, and an image data filing device, and more particularly, a plurality of encoders. The present invention relates to an encoding / decoding device that includes a decoder and can simultaneously execute encoding / decoding processing of image information in a plurality of channels.
[0002]
[Prior art]
Conventionally, when a system requiring compression encoding such as a facsimile system is realized by hardware, the encoding method is realized by hardware and connected to a common I / O of the system.
[0003]
For example, a wide variety of general-purpose encoding methods used in facsimiles are provided as LSIs, and the LSI-based encoding circuit is connected to a data bus, and the CPU inputs and outputs data. Alternatively, the data is input / output by DMA.
[0004]
In recent years, for the purpose of reducing the cost of the system and improving the performance, there has been an increased opportunity to integrate the coding system that has been supplied as an LSI together with other circuits to make most of the system into one chip.
[0005]
With the advancement of semiconductor technology, the number of semiconductors integrated in the same area has been steadily increasing due to the application of finer processing technology, but still realizes a system that handles images like a facsimile system. In the chip, there is a problem that the memory occupies much of the chip area.
[0006]
Among the coding methods used in facsimile, the MR (Modified Relative Element Address Designate) method and the MMR (Modified MR) method (ITU-T T.4) are called two-dimensional coding. Therefore, it is necessary to retain the data one line before the encoded line for reference. Furthermore, when using the JBIG (Joint Bi-level Image experts Group: ITU-T T.82, ISO / IEC 11544, JIS X 4311) system for facsimiles, it is necessary to retain data up to two lines before. .
[0007]
That is, when encoding is performed, a reference line is required. Conventionally, a memory is attached to each coding LSI, or a memory is built in the LSI itself, and an image of a reference line is recorded there, or a reference line by DMA from the system or by CPU access. Was supplying.
[0008]
When a memory (generally a semiconductor memory) is used to hold a reference line, the required size is determined by the number of pixels in the main scan of the image to be encoded. If the normal resolution of the facsimile is A4 size, the number of main scanning pixels is 1728, so the reference memory in MR or MMR requires 1728 bits as a minimum.
[0009]
When the reference line is supplied by DMA or CPU access, it is not necessary to have memory means on the encoder side because the system side memory is used, and the amount of data input from the system side is small although the amount of hardware is small Is doubled (current line image and reference line image), which increases the bus load and lowers the system performance. Therefore, it is advantageous to have a memory on the encoder side to improve performance. It becomes.
[0010]
Since the image data actually processed in the system has various sizes, the required memory amount varies from time to time. Further, since it becomes necessary to select (encode) (or decode) an encoding method according to the function of the other party during communication, it is necessary to selectively use a plurality of types of encoding methods. Furthermore, in situations where a plurality of encoders are used at the same time, for example, when a picture is read, encoded and compressed and stored in a memory during communication involving an encoding process or a decoding process, a plurality of encoders are used. Alternatively, the decoder operates simultaneously (including time division).
[0011]
[Problems to be solved by the invention]
In such a system that needs to support a plurality of encoding processes or / and decoding processes simultaneously, there are various combinations of encoding and decoding processing methods and image sizes to be encoded that are required at the same time. The required memory size changes variously.
[0012]
Therefore, for example, assuming that the maximum main scanning size processed by one encoder is 2432 pixels (A3 size of normal facsimile resolution), when processing an A4 size original document with 1728 pixels, it is stored in the reference memory. The part which is not used will arise.
[0013]
Even when the same facsimile is transmitted, the combination of encoders or decoders that need to be operated differs depending on whether the other party can receive MMR or JBIG.
[0014]
That is, even in the same transmission operation, some encoders or decoders are not operating (for example, in the above example, if the other party can receive MMR, use it even if you have JBIG) If the other party is JBIG, it will not be used even if it has MMR), and in the configuration in which each encoder or decoder has its own memory, memory is wasted. was there.
[0015]
The present invention has been made to solve the above-described problems, and provides an encoding / decoding device capable of performing necessary encoding / decoding operations with as little memory as possible while eliminating waste of memory. The purpose is to do.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, an encoding / decoding device according to claim 1 is provided with a plurality of encoders / decoders, and is capable of simultaneously performing encoding / decoding processing of image information in a plurality of channels. A decoding device comprising a memory means for storing information necessary for encoding / decoding processing, including a reference line image, and assigning the memory means to each encoder / decoder, and data in the memory means Memory control means for controlling transmission / reception of data, and address storage means for storing address information in use in the memory means, wherein the memory control means has a main scanning size of an image to be encoded / decoded. Memo of the memory means according to the address information Re Calculate each memory space to be allocated to the encoder or decoder in the space, and allocate the calculated memory space to the encoder or decoder At the same time, based on the memory release request, the memory address information of the memory space specified by the memory release request is deleted. It is characterized by that.
[0018]
Claim 2 The encoding / decoding apparatus according to claim 1, wherein the address setting for memory control in the memory control means is performed by software setting from an external address setting means. Features.
[0021]
Claim 3 The encoding / decoding device according to claim 1, wherein the memory control unit and each of the encoders / decoders are connected by a DMA interface in the encoding / decoding device according to claim 1. The encoding / decoding device according to 1.
[0022]
Claim 4 The encoding / decoding device according to the first aspect is characterized in that, in the encoding / decoding device according to claim 1, the memory control means and each of the encoders / decoders are connected by a CPU interface.
[0023]
Claim 5 In the encoding / decoding device according to claim 1, the encoding / decoding device according to claim 1, wherein the memory control unit requires that each of the encoders / decoders refer to a plurality of lines at a time. It is characterized in that a reference line is continuously passed without transferring control to another coding channel.
[0024]
Claim 6 The encoding / decoding device according to claim 1, wherein the memory control unit assigns the memory unit according to a priority order of encoding / decoding channels, and Data transfer is performed according to the priority order to the encoder / decoder.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0026]
First, FIG. 1 shows a block diagram of a facsimile apparatus 1 as an example of an apparatus to which an encoding / decoding apparatus is applied.
[0027]
In the figure, an operation display unit 101 is a part that performs a man-machine interface, and has functions such as command input from outside and status display. The scanner unit 102 reads a document and supplies it to the system as image data. The read image data is compression-encoded by the encoding / decoding device 106 or the encoding / decoding device 111 and temporarily stored in the memory 105. The code data is modulated by the modem 114 via the communication control unit 113 and sent to the line under the control of the network control device 115. A system control unit 104 controls the entire apparatus. System data is exchanged via the bus 116.
[0028]
At the time of reception, the signal input from the line is demodulated by the modem 114 under the control of the network control device 115 and received by the system via the communication control unit 113. The received data is temporarily stored in the memory 105, decoded by the encoding / decoding device 106 or the encoding / decoding device 111, and recorded and discharged by the plotter unit 103.
[0029]
In such a facsimile system, conventionally, for example, the encoding / decoding device 106 and the encoding / decoding device 111 are configured by a single LSI.
[0030]
In the encoding / decoding device 106, the reference memory 107 described above is configured by an external RAM with respect to the encoding / decoding device 106 configured by a single LSI. The local bus 118 is interfaced with the network 107. An interface 117 between the encoding / decoding device 106 and the system is interfaced by a DMA or CPU access method.
[0031]
On the other hand, in the encoding / decoding device 111, the reference memory 109 has a built-in form inside the LSI. The LSI incorporates an encoder 108 and a decoder 110 as modules, and each is connected to an internal bus 112. Both the encoder 108 and the decoder 110 use the internal reference memory 109, and processing is performed by using the built-in memory of the LSI during the encoding operation or the decoding operation.
[0032]
An encoding / decoding device 201 shown in FIG. 2 can be applied to the facsimile machine 1 in place of the conventional encoding / decoding devices 106 and 111.
[0033]
In FIG. 2, the encoding / decoding device 201 is an example of an apparatus that can simultaneously perform encoding / decoding of two channels.
[0034]
The encoding / decoding device 201 has a built-in memory means 202 for storing information necessary for the encoder or the decoder. Than, The reading / writing is performed.
[0035]
The memory control means 203 performs memory control and data transfer so that two of the four modules of the first encoder 206, the second encoder 207, the first decoder 208, and the second decoder 209 operate simultaneously. . The external interface is performed by the first channel I / O 204 and the second channel I / O 205.
[0036]
There are three types of combinations of two-channel simultaneous operations: two encoders moving simultaneously, one encoder and decoder moving simultaneously, and two decoders moving simultaneously. Actually, since four encoders / decoders are built in, it is possible to operate four channels simultaneously, but the problem in the present invention is that there is no need for such simultaneous operations. If only two need to operate at the same time, the memory for the two encoders / decoders should be built in as a memory. Compared to the case where each encoder / decoder has a memory. Thus, the amount of memory required is halved. Furthermore, when simultaneous operation of a plurality of encoders / decoders is not required, the memory can be fully used by one encoder or decoder, so that it is possible to process image data having a double main scanning size.
[0037]
FIG. 3 specifically shows an internal configuration of the memory control unit 203 in the encoding / decoding device 201 shown in FIG. 2 and also shows a data exchange relationship between the memory control unit 203 and another configuration.
[0038]
In FIG. 3, the entire operation of the memory control unit 301 is controlled by the control unit 302. The addresses used in the memory unit 202 are stored in the address storage unit 304, and the address of the free memory can be acquired based on the contents. When the processing is started, the control unit 302 reads setting registers (not shown) of the encoders or decoders 206, 207, 208, and 209, and acquires the main scanning size of the image to be processed.
[0039]
The control means 302 calculates the memory space allocated to this encoder or decoder 206, 207, 208, 209 from the acquired main scanning size and the currently used memory address information stored in the address storage means 304. . Depending on the result, the memory access control means 306 controls the address generation means 305 to generate a necessary address, further generates a signal necessary for memory access, and controls writing to or reading from the memory means 308. To do. The I / O control unit 302 controls data exchange with the encoders or decoders 206, 207, 208, and 209. In this example, data is exchanged via the data bus 307.
[0040]
The memory space allocation in the memory control means 203 is to dynamically allocate the memory space according to the operation of the encoder or decoder 206, 207, 208, 209, and without generating a useless area of the memory. , Processing can proceed.
[0041]
FIG. 4 shows a memory allocation processing procedure in the memory control means 203 shown in FIG. In the processing procedure shown in FIG. 4, when a processing start command is issued by the encoder or decoder 206, 207, 208, 209, a new memory acquisition request is generated, and a processing stop command or hardware It is assumed that a memory release request is generated when processing ends (for example, when document reading ends).
[0042]
In the figure, the memory control means 203 constantly monitors whether there is a new memory acquisition request or a memory release request (No in decision 1001, no loop in decision 1002).
[0043]
If there is a new memory acquisition request (Yes in decision 1001), the main scanning size is acquired from the encoder or decoder (process 1003), and a free memory address is searched from the contents of the address storage means 305 (process). 1004), a memory address to be used is determined according to the main scanning size acquired in the processing 1003 (processing 1005), and the processing returns to the determination 1001.
[0044]
If there is a memory release request (Yes in decision 1002), the memory address requested to be released is erased from the contents of the address storage means 305 (process 1006), and the process returns to decision 1001.
[0045]
FIG. 5 shows a second embodiment. Pertaining to A conceptual diagram of a memory block is shown. The memory means 202 is managed in units of blocks 1 to n.
[0046]
In the encoding / decoding device 201 according to the first embodiment of FIG. 2, when a memory address is allocated, a memory having a required size is cut out from a continuous memory space, and the address is calculated by adding or subtracting in hardware. Therefore, the circuit scale increases. On the other hand, the memory is handled in units of blocks as in the second embodiment, so that when one block is insufficient, another block is used, and detailed address calculation is not required. Therefore, the scale of the control circuit is reduced.
[0047]
Further, the size of the memory block of each unit shown in FIG. 5 is set to the main scanning size (the number of pixels in the main scanning direction) that must be minimized by the encoder or decoder 206, 207, 208, or 209. For example, when encoding / decoding for facsimile is performed, A4-200 dpi is required, and 1728 bits must be provided as a minimum in the system.
[0048]
Therefore, if 1728 bits are taken as one block, for example, when A4-600 dpi reading occurs for copying, it can be easily obtained that three blocks should be used. Since the main scanning size of the image in the system generally has only a few patterns, the circuit is further simplified if the required number of blocks corresponding to the main scanning size is tabulated.
[0049]
In addition, when a plurality of encoders / decoders 206, 207, 208, and 209 are using a memory, when encoding or decoding in various sizes and systems starts or ends, allocation is performed. The memory to be used becomes discontinuous and the control of the memory control means 203 becomes complicated. In this respect as well, in the case of block allocation, the continuity of the address can be maintained for at least A4-200 dpi (in this example).
[0050]
FIG. 6 shows a memory allocation processing procedure in units of blocks, which is a modification of the memory allocation processing procedure shown in FIG.
[0051]
In the figure, the memory control means 203 constantly monitors whether there is a new memory acquisition request or a memory release request (No in decision 2001, no loop in decision 2002).
[0052]
If there is a new memory acquisition request (Yes in decision 2001), the main scanning size is acquired from the encoder or decoder (processing 2003), and an empty memory block is searched from the contents of the address storage means 305 (processing). 2004), a memory block to be used is determined according to the main scanning size acquired in the process 2003 (process 2005), and the process returns to the determination 2001.
[0053]
If there is a memory release request (Yes in decision 2002), the memory block requested to be released is erased from the contents of the address storage unit 305 (process 2006), and the process returns to decision 2001.
[0054]
FIG. 7 shows a modified example of the configuration of the memory control unit 203 of the encoding / decoding device 201 shown in FIGS.
[0055]
In the modification shown in FIG. 7, the address setting to the memory access control means for the memory control of the memory control means 203 is performed according to the conditions in the memory control means 203 by the address storage means 304 and the control means 302. Instead of setting the address, the address is set by memory access by software control from the external control means 308 outside the encoding / decoding device 201. The external control unit 308 can be, for example, the system control unit 14 of the facsimile machine 1.
[0056]
By doing so, it is possible to realize a system in which memory allocation is performed by an algorithm more suitable for the system without using a memory address allocation algorithm fixed by hardware. Further, since hardware for the memory allocation algorithm is not required, the cost can be reduced.
[0057]
In the encoding / decoding apparatus 201 shown in FIG. 2, the interfaces 210, 211, 212, and 213 of the built-in encoders or decoders 206, 207, 208, and 209 can be DMA interfaces.
[0058]
That is, the interfaces 210, 211, 212, and 213 of the decoders 206, 207, 208, and 209 can be DMA interfaces configured with control signals such as Request, Acknowledge, and Strobe, for example.
[0059]
By doing so, when the built-in encoder and decoder are considered as components, each can be directly connected to a CPU interface in another system, and the application range as IP (Intellectual Property) is expanded. .
[0060]
In the encoding / decoding device 201 shown in FIG. 2, the interfaces 210, 211, 212, and 213 of the built-in encoders or decoders 206, 207, 208, and 209 can be used as CPU interfaces.
[0061]
That is, the interfaces 210, 211, 212, and 213 of the decoders 206, 207, 208, and 209 can be CPU interfaces whose control signals are, for example, Address, Chip Select, and Strobe.
[0062]
By doing so, when the built-in encoder and decoder are considered as components, each can be directly connected to a CPU interface in another system, and the application range as IP (Intellectual Property) is expanded. .
[0063]
FIG. 8 shows an example of memory access scheduling in the encoding / decoding device 201 shown in FIGS.
[0064]
The timing chart of the memory access scheduling shown in FIG. 6A shows a case where the first encoder 206 and the second encoder 207 perform memory access alternately and evenly. It should be noted that the period indicated by “1” indicates the access period by the first encoder 206, and the period indicated by “2” indicates the access period by the second encoder 207, which is shown in FIG. ) And FIG. 9 described later.
[0065]
In the encoding / decoding device 201, for example, in the case of a coder such as JBIG that refers to up to two lines before the current encoding line, when a plurality of channels are operating simultaneously, FIG. When the reference memory is alternately transferred once each as shown in a), JBIG processing is half the speed of encoding or decoding processing that requires only one line of reference memory. However, the necessary information will not be obtained, and the processing speed of JBIG will decrease.
[0066]
Therefore, when it is necessary to transfer the reference memory for two lines as shown in FIG. 8B, it is possible to reduce the variation in the operation of the entire system by continuously transferring the reference image. As a result, the system performance can be improved.
[0067]
For example, in the case of facsimile memory transmission, an image once encoded and stored in the memory is decoded once at the time of transmission, and further converted into an encoding method that can be received by the transmission destination and transmitted. If there is a difference between the processing speed of the encoding method and the encoding method used at the time of transmission, the buffer memory in the middle will increase or it will be necessary to wait for the slower one that is faster. This is because it is determined by the processing speed.
[0068]
FIG. 9 shows another example of memory access scheduling in the encoding / decoding device 201 shown in FIGS.
[0069]
For example, when the communication resolution and the reading and storage resolution are different on the system (the reading resolution is higher), the main scanning size is different even when the same compression encoding is performed. For example, when reading is A4-600 dpi and transmission is A4-200 dpi, the data amount of one line is tripled. If this is encoded with the same scheduling as shown in FIG. 9 (a), the processing time for one page is naturally shorter for 200 dpi and longer for 600 dpi, resulting in an imbalance.
[0070]
Therefore, as shown in FIG. 9B or FIG. 9C, by increasing the chances of giving data to a higher-resolution image (here, the image processed by the first encoder 206), the entire processing is performed. The balance of progress will be balanced. That is, in such a case, it is only necessary to increase the priority of a task in which an image with a high resolution flows and increase the number of transfers there. Needless to say, the priority may be assigned not only according to the resolution but also according to other conditions necessary for system operation.
[0071]
In the embodiment described above, the encoding / decoding apparatus according to the present invention is applied to a facsimile apparatus. However, the present invention is not limited to this, and various applications such as a scanner apparatus, a digital camera, and an image data filing apparatus can be used. Applicable.
[0072]
【The invention's effect】
According to the first aspect of the present invention, the memory control means converts the memory means to each encoder decoding according to the main scanning size and the number of simultaneous operations of the image to be processed by each of the operating encoder or decoder. Assign to vessel At the same time, based on the memory release request, the memory address information of the memory space specified by the memory release request is deleted. As a result, the memory to be used is not wasted, and as a result, the encoding / decoding operation can be realized with a small amount of memory, and a low-cost encoding / decoding device with a reduced amount of hardware is realized. The effect which becomes possible is acquired.
[0074]
Claim 2 According to the invention, in addition to the same effect as in the first aspect, since the memory control address setting algorithm is realized by software, it is possible to flexibly deal with changes in allocation conditions, etc., rather than using hardware in memory control. In addition, the hardware can be reduced and the cost can be reduced.
[0077]
Claim 3 In addition to the same effects as in the first aspect, since the exchange of data between the memory control means and each encoder / decoder is performed via the DMA interface, each encoder / Considering the decoder as an IP (Intellectual Property), there is an advantage that each built-in encoder or decoder can be connected to the system via the DMA interface.
[0078]
Claim 4 In addition to the same effects as in the first aspect of the present invention, since data exchange between the memory control means and each encoder / decoder is performed via the CPU interface, each encoder / When the decoder is considered as IP (Intellectual Property), there is an advantage that each built-in encoder or decoder can be connected to the system via the CPU interface even if it is a single unit.
[0079]
Claim 5 According to the invention, in addition to the same effect as in the first aspect, since control is performed so that reference lines are continuously passed to an encoder or decoder module that requires reference to a plurality of lines. When multiple encoders and decoders are operating at the same time, it is possible to reduce the waiting time for transfer of reference lines in an encoder or decoder that requires multiple reference lines. As a whole, the effect that the processing speed can be improved is obtained.
[0080]
Claim 6 According to the invention, in addition to the same effect as in the first aspect, when a large amount of data transfer occurs such as when processing a large image, such an encoder or decoder is provided. On the other hand, since data transfer is preferentially performed, it is possible to improve the processing speed of the entire system.
[Brief description of the drawings]
FIG. 1 is a diagram showing a block configuration of a facsimile apparatus to which an encoding / decoding apparatus according to an embodiment of the present invention is applied.
FIG. 2 is a diagram showing a block configuration of an encoding / decoding device according to an embodiment of the present invention.
FIG. 3 is a diagram showing a block configuration and the like of memory control means of the encoding / decoding device according to the embodiment of the present invention.
FIG. 4 is a flowchart showing a memory allocation processing procedure in the memory control means of the encoding / decoding apparatus according to the embodiment of the present invention.
FIG. 5 is a diagram showing a memory block configuration.
FIG. 6 is a flowchart showing a memory allocation processing procedure in units of blocks in the memory control means of the encoding / decoding apparatus according to the embodiment of the present invention.
FIG. 7 is a diagram different from FIG. 3 showing the block configuration and the like of the memory control means of the encoding / decoding device according to the embodiment of the present invention.
FIG. 8 is a schematic diagram showing memory access scheduling in the encoding / decoding device according to the embodiment of the present invention.
FIG. 9 is a schematic diagram different from FIG. 8 illustrating the memory access scheduling in the encoding / decoding device according to the embodiment of the present invention.
[Explanation of symbols]
1 Facsimile device
101 Operation display section
102 Scanner section
103 Plotter section
104 System control unit
105 memory
106 Coding / decoding device
107 Reference memory
108 Encoder
109 Reference memory
110 Decoder
111 Coding / decoding device
112 Internal bus
113 Communication control unit
114 modem
115 Network control unit
116 Bus
117 interface
118 Local bus
201 Coding / decoding device
202 Memory means
203 Memory control means
204 1st channel I / O
205 Second channel I / O
206 First encoder
207 Second encoder
208 first decoder
209 Second decoder
210, 211, 212, 213 interface
302 Control means
303 I / O control means
304 Address storage means
305 Address generation means
306 Memory access control means
307 Data bus
308 External control means

Claims (6)

An encoding / decoding device comprising a plurality of encoders / decoders and capable of simultaneously executing encoding / decoding processing of image information in a plurality of channels,
Memory means for storing information necessary for the encoding / decoding process, including a reference line image;
Memory control means for allocating the memory means to the encoders / decoders and controlling the data transfer of the memory means;
Address storage means for storing address information in use in the memory means,
It said memory control means includes a main scanning size of the image to be encoded decoding by said address information, and calculates the individual memory space to be allocated to the encoder or decoder of the memory space of the memory means An encoding / decoding device characterized by allocating the calculated memory space to the encoder or decoder and erasing the memory address information of the memory space designated by the memory release request based on the memory release request .   2. The encoding / decoding apparatus according to claim 1, wherein address setting for memory control in the memory control means is performed by software setting from an external address setting means.   The encoding / decoding apparatus according to claim 1, wherein the memory control unit and each of the encoders / decoders are connected by a DMA interface.   The encoding / decoding apparatus according to claim 1, wherein the memory control unit and each of the encoders / decoders are connected by a CPU interface.   The memory control means, when each of the encoders / decoders needs to refer to a plurality of lines at a time, passes the reference lines continuously without transferring control to another encoding channel. The encoding / decoding apparatus according to claim 1.   The memory control means allocates the memory means in accordance with the priority order of coding and decoding channels, and performs data transfer according to the priority order to the respective encoders / decoders. The encoding / decoding apparatus according to claim 1.

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