JP4059065B2 - Memory circuit and data erasing and writing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory circuit and a data erasing and writing method, and more particularly to a memory circuit and a data erasing and writing method for erasing and writing data in an EEPROM.
[0002]
[Prior art]
A conventional EEPROM data erasing method will be described below for the NAND type (for example, see Non-Patent Document 1 or Non-Patent Document 2).
[0003]
FIG. 8 shows a circuit configuration of the NAND type EEPROM.
[0004]
Transistors are connected in series vertically from the source line VS through the selection gate SG2. Then, it is connected to the bit lines BL1 and BL2 through the selection gate SG1.
[0005]
For the selective erase block A to be erased, the selection gates SG1 and SG2 are set to 20V, the word line is set to 0V, and the source line VS is set to open. For the non-erased block B that is not erased, the select gates SG1 and SG2, the word line WL are set to 20V, and the source line VS is set to open. The p-well is set to 20 V for both the selective erase block A and the non-erasable block B.
[0006]
In the conventional method, as shown in FIG. 9, the CMOS logic is used to suddenly charge from 0 V to 20 V and to discharge rapidly. By erasing, the threshold voltages of the memory cells all become negative values as shown in FIG.
[0007]
FIG. 11A shows the state of the Fowler-Nordheim current (FN current) in the erased state. It can be seen that electrons move from the floating gate toward the substrate.
[0008]
FIG. 12 shows a configuration of a memory circuit at the time of writing in a conventional NAND flash. The bit line BL1 that performs writing is set to 0V, and the bit line BL2 that prohibits writing is set to 7V. The selection gate SG1 is 10V, the unselected word line is 10V, the selected word line (WL2 in the example of FIG. 12) is 20V, and the selection gate SG2 and the source line VS are 0V. Moreover, p-well is 0V. At this time, writing is performed to the selected cell designated by the bit line BL1 and the word line WL2. The voltage change with time is, for example, as shown in FIG. At this time, the threshold voltages of the memory cells are all positive values as shown in FIG. FIG. 11B shows the state of the Fowler-Nordheim current (FN current) in the written state. It can be seen that electrons move from the substrate to the floating gate.
[0009]
[Non-Patent Document 1]
Flash memory technology handbook, Fujio Tsujioka, Science Forum, 1993.
[Non-Patent Document 2]
Low power consumption, high-speed LSI technology, Takayasu Sakurai, Realize, 1998.
[0010]
[Problems to be solved by the invention]
However, the above conventional technique has a problem that power consumption cannot be reduced due to charging / discharging of a word line and a bit line having a large load capacity.
[0011]
The present invention has been made in view of the above points, and an object thereof is to provide a memory circuit and a data erasing and writing method capable of reducing power consumption when charging / discharging a word line and a bit line. To do.
[0012]
[Means for Solving the Problems]
The present invention includes a source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate. A memory circuit of an EEPROM comprising a plurality of storage elements connected to the bit line through, a word line connected to each storage element, a non-erasable block having a p-well and an erase block,
A selection circuit for selecting a power clock or 0 V output from the charge recycle power source connected to the word line;
The selection circuit connected to the word line of the erase block has means for selecting 0V and outputting it to the word line,
The selection circuit connected to the word line of the non-erased block has means for selecting a power clock from the charge recycle power source and outputting it to the word line, and charging and discharging the p-well with the power clock. .
[0013]
The present invention includes a source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate. An EEPROM memory circuit having a plurality of storage elements connected to the bit line through the word line, a word line connected to each storage element, and a p-well,
A selection circuit for selecting a power clock or 0 V, which is an output from a charge recycling type power supply, connected to a word line;
At the time of data writing, the power clock is selected by the selection circuit, the voltage of the bit line not to be written is boosted adiabatically to a predetermined voltage, and then the word line voltage is increased to the predetermined voltage by the power clock. Boosting means for adiabatically boosting and then adiabatically boosting the voltage of the word line to be written next to a predetermined higher voltage;
After boosting, the power clock is selected by the selection means, the voltage of the word line to be written is lowered adiabatically to a predetermined voltage, and then the voltage of the word line is simultaneously increased to the predetermined voltage using the power clock. And a step-down means for adiabatically dropping the voltage of the bit line not to be written to a predetermined voltage by using a power clock.
[0014]
The present invention includes a source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate. In a data erasing method in an EEPROM memory circuit comprising a plurality of memory elements connected to the bit line through the word line, a word line connected to each memory element, and a non-erasable block having a p-well and an erase block,
When erasing data, the voltage of the word line and p-well is boosted from 0V to the voltage necessary for erasing, and a power clock from the charge reusable power supply is output to the word line to adiabatically charge. And
When the voltage is lowered from the voltage necessary for erasing to 0 V, the power clock is output to the word line and the p-well to reduce adiabatically.
[0015]
The present invention includes a source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate. In a data write method in an EEPROM memory circuit having a plurality of storage elements connected to the bit line through the word lines, word lines connected to the storage elements, and p-well,
At the time of data writing, the bit line not to be written is adiabatically boosted to a predetermined voltage by a power clock from the charge reusable power supply ,
When the voltage is lowered from the boosted predetermined voltage to 0 V, the power clock is output to the bit line to which no writing is performed, and is lowered adiabatically .
[0016]
The present invention includes a source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate. In a data write method in an EEPROM memory circuit having a plurality of storage elements connected to the bit line through the word lines, word lines connected to the storage elements, and p-well,
At the time of data writing, each of the word line for writing and the word line for which writing is not performed is adiabatically boosted to a predetermined voltage by the power clock from the charge reusable power source ,
When the voltage is lowered from the boosted predetermined voltage to 0 V, the power clock is output to the word line where writing is performed and the word line where writing is not performed, and is lowered adiabatically .
[0017]
The present invention includes a source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate. In a data writing method in an EEPROM memory circuit having a plurality of storage elements connected to the bit line through the word line, a word line connected to each storage element, and a p-well,
At the time of data writing, the voltage of the bit line not to be written is adiabatically boosted to a predetermined voltage by the power clock from the charge reusable power source,
With the power clock, the voltage of the word line is boosted adiabatically to a predetermined voltage,
With the power clock, the voltage of the word line for writing is boosted adiabatically to a predetermined higher voltage,
With the power clock, the voltage of the word line to be written is lowered adiabatically to a predetermined voltage,
With the power clock, the voltage of the word line is lowered adiabatically to a predetermined voltage all at once.
By the power clock, the voltage of the bit line not to be written is lowered adiabatically to a predetermined voltage.
[0018]
As described above, according to the present invention, the word line and the bit line can be connected to the word line and the bit line by connecting the charge recycle power source (power clock (PCK)) having a gradually rising / falling waveform to the word line and the bit line. By using this PCK for charging / discharging, data can be erased and written, and power consumption required for charging / discharging can be reduced.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
[First Embodiment]
In this embodiment, a case where data is erased will be described.
[0021]
FIG. 1 shows a configuration of a memory circuit at the time of block erase of a NAND flash according to the first embodiment of the present invention. The circuit configuration itself of the memory circuit shown in the figure is the same as that of the conventional circuit shown in FIG. 8, but a power clock by a charge recycle type power supply is used when raising / lowering the voltage. For this purpose, a selector circuit (SEL) is connected to each of the selection gate SG1, the word lines WL1 to WL4, and the selection gate SG2, and a power clock (PCK) or 0V from a charge reusable power source is selected. Is configured to do. In addition, as a charge recycle type power source, [Japanese Patent Application No. 11-33953 “Multi-phase charge recycling stepped power source circuit”], [Shunji Nakata, el al., A low power multiplier using adiabatic charging bainary decision diagram circuit, Jpan. J. Appl. Phys. 39, 2305 (2000)].
[0022]
In the selective erase block A to be erased, 0V is selected in the selector circuit (SEL) of the word line. In the non-erased block B that is not erased, the power clock (PCK1 to PCK6) is selected in the selector circuit (SEL).
[0023]
FIG. 2 shows the time change of the voltage in the first embodiment of the present invention. Specifically, it is a staircase waveform when a switched capacitor is used, and a trigonometric sine waveform when an LC circuit is used.
[0024]
FIG. 3 shows the configuration of the selector circuit according to the first embodiment of the present invention. FIG. 3A shows that either PCK or 0V is output to OUT in response to the input signal S. Further, as shown in (b), a specific circuit selects and outputs PCK when S = 1, and selects and outputs 0 V when S = 0.
[0025]
[Second Embodiment]
In this embodiment, a case of writing data is described.
[0026]
FIG. 4 shows a configuration of a memory circuit at the time of writing to the NAND flash according to the second embodiment of the present invention. The circuit configuration itself of the memory circuit shown in the figure is the same as that of the conventional circuit shown in FIG. 12, but a power clock by a charge recycle type power supply is used when raising or lowering the voltage. For this purpose, a selector circuit (SEL) is connected to each of the selection gate SG1, the word lines WL1 to WL4, and the selection gate SG2 so as to select a power clock (PCK) or 0V from the charge reusable power source. It is configured.
[0027]
FIG. 5 shows an example of a voltage change by the charge recycle type power supply in the second embodiment of the present invention, and FIG. 6 is a flowchart showing an operation in the second embodiment of the present invention.
[0028]
When writing data, the bit line BL1 to which data is written is set to 0V, and the bit line BL2 to which data is not written is boosted adiabatically to 7V using PCK (step 101). Next, the word line WL1 is adiabatically boosted to 10V using PCK (step 102), and only the word line WL2 to be written next is further adiabatically boosted to the write voltage 20V using PCK (step 103). ). Next, the voltage of the word line WL2 to be written is adiabatically lowered to 10 V using PCK by a completely reverse method. That is, only the word line WL2 is lowered from 20V to 10V (step 104). Next, the word lines WL1, WL2 are lowered adiabatically from 10V to 0V using PCK (step 105).
[0029]
Then, the bit line BL2 on which writing is not performed is lowered adiabatically to 0 V using PCK (step 106).
[0030]
The operation of the bit line and the word line shown here is an example, and the present invention is not limited to this, and other operation methods can be performed.
[0031]
Moreover, by using this PCK, as shown in FIG. 7, it becomes possible to reduce the energy at the time of charging / discharging to about 1/10 or less.
[0032]
The present invention is not limited to the above-described embodiment, and various modifications and applications can be made within the scope of the claims.
[0033]
【The invention's effect】
In the conventional method, since charging / discharging of the word line and the bit line is performed by CMOS logic, there is a problem that the power consumption of charging / discharging is large. As described above, according to the present invention, By connecting the power clock (PCK), which is the output from the charge recycle type power supply with a gently rising / falling waveform, to the word line and bit line, the power consumption due to charging / discharging can be reduced to the conventional constant voltage. This can be reduced compared to a configuration in which the power supply is precharged.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a memory circuit at the time of block erase of a NAND flash according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a time change of voltage in the first embodiment of the present invention.
FIG. 3 is a configuration diagram of a selector circuit in the first embodiment of the invention.
FIG. 4 is a configuration diagram of a memory circuit at the time of writing in a NAND flash according to a second embodiment of the present invention.
FIG. 5 is a diagram showing a time change of voltage in the second embodiment of the present invention.
FIG. 6 is a flowchart of the operation in the second embodiment of the present invention.
FIG. 7 is a diagram showing the effect of the present invention.
FIG. 8 is a configuration diagram of a memory circuit at the time of block erase of a conventional NAND flash.
FIG. 9 is a diagram showing a time change of a conventional voltage.
FIG. 10 is a diagram illustrating threshold voltage values in an erased state and a written state.
FIG. 11 is a diagram illustrating a state of a tunnel current in an erase state and a write state.
FIG. 12 is a configuration diagram of a memory circuit at the time of conventional NAND flash writing.
FIG. 13 is a diagram showing a time change of a conventional voltage.
[Explanation of symbols]
PCK1-PCK6 power clock lines SG1, SG2 select gates WL1-WL4 word lines BL1, BL2 bit line VS source line SEL selector circuit

Claims (6)

A source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate, and the bit line through the second selection gate A memory circuit of an EEPROM comprising a plurality of storage elements connected to each other, a word line connected to each storage element, a non-erasable block having a p-well and an erase block,
A power clock which is an output from the charge reusable power supply connected to the word line, or a selection circuit for selecting 0V;
The selection circuit connected to the word line of the erase block has means for selecting 0V and outputting it to the word line;
The selection circuit connected to the word line of the non-erased block has means for selecting a power clock from the charge recycle power supply and outputting it to the word line. The p-well is also charged with the power clock. A memory circuit characterized by discharging. A source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate, and the bit line through the second selection gate A plurality of storage elements connected to each other, a word line connected to each storage element, and an EEPROM memory circuit having a p-well,
A selection circuit for selecting a power clock or 0V output from a charge recycle power source connected to the word line;
At the time of writing data, the selection circuit selects the power clock, and the voltage of the bit line not to be written is boosted adiabatically to a predetermined voltage, and then the voltage of the word line is determined by the power clock. Boosting means for adiabatically boosting the voltage of the word line to be written to, and then adiabatically boosting the voltage of the word line to be written to a predetermined higher voltage by the power clock;
After boosting, the power clock is selected by the selection means, and the voltage of the word line to be written is lowered adiabatically to a predetermined voltage. Next, the voltage of the word line is simultaneously A memory circuit comprising: a step-down means for adiabatically dropping to a voltage and adiabaticly dropping the voltage of the bit line not to be written to a predetermined voltage by the power clock. A source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate, and the bit line through the second selection gate In a data erasing method in an EEPROM memory circuit composed of a plurality of memory elements connected to each other, a word line connected to each memory element, a non-erasable block having a p-well and an erase block,
When erasing data, when the voltage of the word line and the p-well is boosted from 0 V to a voltage necessary for erasing, a power clock from a charge reusable power supply is output to the word line for heat insulation. Recharge the battery,
A data erasing method, wherein when the voltage is lowered from a voltage necessary for erasing to 0 V, the power clock is output to the word line and the p-well to reduce adiabatically. A source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate, and the bit line through the second selection gate In a data writing method in an EEPROM memory circuit having a plurality of storage elements connected to each other, a word line connected to each storage element, and a p-well,
At the time of data writing, the bit line not to be written is adiabatically boosted to a predetermined voltage by a power clock from the charge reusable power supply ,
A data writing method characterized in that, when the voltage is lowered from the boosted predetermined voltage to 0 V, the power clock is output to the bit line not to be written and lowered adiabatically . A source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate, and the bit line through the second selection gate In a data writing method in an EEPROM memory circuit having a plurality of storage elements connected to each other, a word line connected to each storage element, and a p-well,
At the time of data writing, each of the word line for writing and the word line for which writing is not performed is adiabatically boosted to a predetermined voltage by the power clock from the charge reusable power source ,
When the voltage is lowered from the boosted predetermined voltage to 0 V, the power clock is output to the word line that performs the writing and the word line that does not perform the writing, and is lowered adiabatically. To write data. A source line, a bit line, a first selection gate, a second selection gate, and a serial connection in series through the source line and the first selection gate, and the bit line through the second selection gate In a data writing method in an EEPROM memory circuit having a plurality of storage elements connected to each other, a word line connected to each storage element, and a p-well,
At the time of data writing, the voltage of the bit line not to be written is adiabatically boosted to a predetermined voltage by the power clock from the charge reusable power source,
By the power clock, the voltage of the word line is boosted adiabatically to a predetermined voltage,
By the power clock, the voltage of the word line to be written is boosted adiabatically to a predetermined higher voltage,
By the power clock, the voltage of the word line to be written is lowered adiabatically to a predetermined voltage,
By the power clock, the voltage of the word lines is lowered adiabatically to a predetermined voltage all at once,
A data writing method, wherein the voltage of the bit line not to be written is lowered adiabatically to a predetermined voltage by the power clock.

Images