JP3935021B2 - Packet processing method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a packet processing method and apparatus for mounting a newly generated header on a transmission packet in accordance with a header mounted on a received packet, and more particularly to a network for processing header analysis of packets corresponding to a plurality of protocols at high speed. The present invention relates to a packet processing method and apparatus suitable for use in a LAN switch.
[0002]
[Prior art]
In the field of digital communication, packet communication is widely used for transferring information. At the head of the packet, a header indicating information on the transmission destination, the type of information, and the like is mounted, and has a different header for each type of packet (protocol).
[0003]
Examples of packets that have been widely used recently are shown in FIGS. Packets by type
(A) DIX packet described in RFC194,
(B) RAW packet as described in IEEE 802.3,
(C) an LLC packet carrying LLC information 405 described in IEEE 802.2;
(D) LLC + SNAP packet
And VLAN information 407 described in IEEE 802.1Q is mounted on the above four types of packets.
(E) DIX + VLAN packet,
(F) RAW + VLAN packet,
(G) LLC + VLAN packet,
(H) LLC + SNAP + VLAN packet
There are a total of eight types, and packet processing apparatuses are required to process these eight types of packets accurately and promptly.
[0004]
The Layer 2 header (hereinafter referred to as L2 header) of each packet is MAC-DA information (destination MAC address) 401, MAC-SA information (source MAC address) 402, Type information 403, Length information 404, LLC information 405, SNAP. The information 406 and the VLAN information 407 are mounted, and the L2 header is configured by a combination of each information. Therefore, the length of the L2 header is different for each packet type. In FIG. 14, these pieces of information are simply displayed as “MAC-DA”, “Type”, or the like.
[0005]
The packet has an L2 header followed by a payload 408. In the case of an IPv4 packet, as shown in FIG. 15, the version information 701, the header length information 702, the TOS information 703, the total length information 704, the identification number in order from the top. Layer 3 header (hereinafter referred to as L3 header) including information 705, fragment information 706, TTL information 707, protocol number information 708, header checksum information 709, transmission source IP address information 710, transmission destination IP address information 711, and option information 712 is included. It is installed.
[0006]
In the case of a packet processing device having an IPv4 routing function, it is necessary to newly generate a transmission packet header in which the above-described MAC-DA information 401, MAC-SA information 402, TTL information 707, and header checksum information 709 are rewritten. The newly generated MAC-DA information 401 needs to have a value corresponding to the destination IP address information 711.
[0007]
Conventionally, as this type of device, a device such as a packet processing device described in Japanese Patent Application Laid-Open No. 11-317783 shown in FIG. 13 has been used. In the figure, a register 350 is a memory for storing information on the head portion of a packet including a lower layer header and an upper layer header of the packet. The CPU 354 analyzes the received packet header stored in the register 350 and receives the received packet. Information necessary for transmission packet header generation included in the header is extracted and stored in the register 351, and the CPU 355 refers to the table 357 and stores a value corresponding to the information stored in the register 351 in the register 352. The CPU 356 newly generates a transmission packet header according to the value stored in 352 and stores it in the register 353. In order to transfer data between the registers 350, 351, and 352, the start of each program is determined while checking a flag register indicating whether data can be written or read.
[0008]
[Problems to be solved by the invention]
As described above, since the lengths of the L2 header and the upper layer header differ depending on the type of each packet, the conventional packet processing apparatus extracts the destination IP address information 711 from the received packet and stores it in the register 351. The CPU 354
A processing step for reading the L2 header;
A processing step for determining the length of the read L2 header;
A processing step of detecting the position of the destination IP address information 711 according to the obtained length of the L2 header;
A processing step of reading destination IP address information 711 from the detected position;
A processing step of storing the read destination IP address information 711 in the register 351;
Need to run. Further, in the processing step of reading the L2 header, it is necessary to divide the L2 header into the amount of data that the CPU 354 can read at one time, and repeatedly read it in several times.
[0009]
That is, the time taken to detect the position of the destination IP address information 711 on the received packet depends on the amount of data that the CPU 354 can read at one time and the number of times it can be read per unit time. Since a packet processing device requires a CPU 354 with higher performance, the cost of the product is increased. Similarly, the time taken to write the transmission packet header to the register 353 depends on the amount of data that the CPU 356 can write at a time and the number of times that the data can be written per unit time. Since the CPU 356 is required, the cost of the product is also increased (first problem).
[0010]
In addition, between the CPUs 354, 355, and 356, notification and detection of whether or not the flag register information mounted for each of the registers 350, 351, 352, and 353 can be used has a fixed period. For this reason, it is determined that the registers 350, 351, 352, and 353 are read and an extra processing step other than the packet analysis is required, and the program size including the packet analysis is increased, that is, the program storage memory is also increased. Incurs high costs (second problem).
[0011]
In the conventional apparatus, the register 351 and 352 that can be connected to the table 357 is changed by the processing load, for example, because the register 351 and 352 that can be connected to the table 350 and the register 353 that is used at the time of transmission are fixed. You can't change it if you want. Therefore, there is a need for a packet processing apparatus that can process not only the IPv4 header described above but also various types of headers typified by IPv6 header and MPLS, and new protocols are defined every day. Therefore, a packet processing device that can be easily modified and changed in the future and has a high degree of flexibility in design change is desired (third problem).
[0012]
Therefore, in view of the first problem described above, the present invention particularly provides a high-performance CPU for each of the extraction processing of information necessary for generating a new transmission packet header and the generation processing of the transmission packet header. An object of the present invention is to provide a packet processing apparatus that is not necessary.
Another object of the present invention is to provide a packet processing apparatus having a memory size necessary only for received packet analysis in view of the second problem described above.
In addition, in view of the third problem described above, the present invention makes it easy to make corrections and future function changes not only for IPv4 headers but also for received packets equipped with various types of headers typified by IPv6 headers and MPLS. An object of the present invention is to provide a packet processing apparatus that is flexible in design change.
[0013]
[Means for Solving the Problems]
  Claim1The described invention
  Stores search data for converting received packet headers to transmitted packet headers in a search tableSearch data storage step to,
  Stores comparison information for determining the type of the received packetComparison information storage step to,
  Detects data breaks in the received packet and separates the header-equivalent data part and the payload-equivalent data partReceive packet separation step,
  Number according to the type of the received packet and / or the packet analysis content assigned in advancesoPipeline configurationIs, With a fixed periodReceiveThe header equivalent data portion separated in the packet separation step and the comparison information stored in the comparison information storage step are compared to determine the type of the received packet, and the search table is searched as necessary. The header equivalent data is updated and output to the next stage, and the analysis result is passed to the next stage when the next stage uses it.One or more packet analysis steps,
  Header equivalent data from the last stage of the one or more packet analysis steps, andReceiveData portion corresponding to the payload separated by the packet separation stepTieOutput as a send packetAn update packet transmission step,
Prepared,
Each of the packet analysis steps includes:
  A header data storage step of storing the header equivalent data portion separated by the received packet separation step and outputting a packet analysis start timing signal after completion of the storage;
  A header editing storage step for extracting and storing different information in the header data storage step according to a packet analysis program, and for storing the comparison information and temporary data generated during execution of the packet analysis program; ,
  A header analysis result storage step for storing a packet analysis result obtained by executing the packet analysis program;
  Using a general-purpose register, a general-purpose calculation step for starting execution of a packet analysis program triggered by a packet analysis start timing signal output from the header data storage unit;
  Based on a special operation instruction included in the packet analysis program, the data of the result of the header data storage step, the header edit storage step, the header analysis result storage step or the comparison information storage step is directly read and read. A logical operation for packet analysis is performed on the data, and the result is stored as the result data of the header data storage step, the header edit storage step, the header analysis result storage step or the comparison information storage step. A calculation step,
  A packet processing method.
The invention according to claim 2
A search table for storing search data for converting the header of the received packet into the header of the transmitted packet;
A comparison information storage unit for storing comparison information for determining the type of the received packet;
A received packet separator that detects a data delimiter of the received packet and separates a header equivalent data portion and a payload equivalent data portion;
The pipeline is configured with a number corresponding to the type of the received packet and / or the packet analysis content allocated in advance, and is received by the received packet separation unit at a fixed period.
The separated header equivalent data part and the comparison information stored in the comparison information storage unit are compared to determine the type of the received packet, and the search table is searched for the header equivalent data as necessary. One or more packet analysis elements that are passed on to the next stage when the next stage uses the analysis result,
Header equivalent data from the last stage of the one or more packet analysis elements and the reception parameter. An update packet transmitter that combines the payload-corresponding data parts separated by the packet separator and outputs them as transmission packets,
  Each of the packet analysis elements includes:
  A header data storage unit that stores a header equivalent data portion sent from the received packet separation unit and outputs a packet analysis start timing signal after the storage is completed;
  A header editing storage unit for extracting and storing different information from the header data storage unit according to a packet analysis program, and for storing the comparison information and temporary data generated during execution of the packet analysis program; ,
  A header analysis result storage unit for storing a packet analysis result obtained by executing the packet analysis program;
  A general-purpose arithmetic unit having a general-purpose register and starting execution of a packet analysis program triggered by a packet analysis start timing signal output from the header data storage unit;
  Based on a special operation instruction included in the packet analysis program, the header data storage unit, the header edit storage unit, the header analysis result storage unit, or the comparison information storage unit is directly read and read. A special operation that performs a logical operation for packet analysis on data and directly writes a result to the header data storage unit, the header edit storage unit, the header analysis result storage unit, or the comparison information storage unit With the calculator
  A packet processing apparatus.
  According to the first and second aspects of the invention, processing such as identification of each field in the received packet header, extraction of search key information, and generation of a transmission packet header after receiving the search result is performed according to the type of received packet. Therefore, it is not necessary to prepare a high-performance CPU because it is possible to select the number of packet analysis elements to be processed and the type of processing to be performed by each packet analysis element.
[0014]
  In the packet processing device according to claim 3, each of the packet analysis elements includes,
ThisA memo that stores a packet analysis program executed by the packet analysis elementLiPrepared,
  After the fixed period, the execution of the packet analysis program is completed, and a packet analysis completion timing signal is output to the next stage element or update packet transmitter.
  According to the configuration of claim 3, since the transfer of information between the packet analysis elements of the pipeline configuration is also performed with a predetermined timing signal, no special flag (register) and processing are required. All can be assigned to individual packet analysis processing.
[0015]
  According to a fourth aspect of the present invention, each of the packet analysis elements further includes,
in frontThe header analysis result is stored in synchronization with the packet analysis completion timing signal.PartStores the header analysis result of the packet analysis element in the subsequent stage of the data stored inPartOutput.
  According to the configuration of claim 4, when configured with one or more packet analysis elements, the information extracted and analyzed by the packet analysis element in the previous stage is not processed redundantly. Distribution can be flexibly handled, and all memory sizes for storing programs can be assigned to individual packet analysis processes.
[0016]
According to a fifth aspect of the present invention, the header analysis result storage circuit comprises:
While analyzing the current header, the next packet is received and the analysis result of the current header is not overwritten with the analysis result of the next header, and each surface is provided for each packet analysis completion timing signal. It was set as the structure which switches to and memorize | stores alternately.
According to the configuration of the fifth aspect, since the analysis result information of the current packet can be held even during reception of the next packet, the packet analysis result information can be transmitted to the subsequent packet analysis element without lowering the throughput.
[0018]
  Claim6According to the invention described in (1), the special arithmetic unit further performs an immediate logical operation included in the packet analysis program.
  Claim6According to the configuration described in (1), design change and function addition can be realized.
[0019]
  Claim7In the invention described in (2), the special operation instruction is stored in the header data storage.PartAnd the header analysis result storagePartAnd the header editing memoryPartAnd the comparison information storagePartIn this configuration, an access control signal for directly reading or writing any one of the above data and various enable signals required at the time of instruction execution are used.
  Claim7According to the configuration described in the above, the header data is stored in the information necessary for executing the special operation instruction.Part, Header analysis result storagePart, Header editing memoryPartComparison information storagePartIt is possible to generate an access control signal such as an address so that the data can be directly read and written, and to generate various enable signals necessary for executing the instruction.
[0020]
  Claim8The invention described in (2), the header data storagePartThe surface written during packet reception, andGeneral-purpose computing unitAnd a header register that alternately stores the header equivalent data of each packet in a two-plane configuration of the plane being analyzed by the special arithmetic unit.
  Claim8According to the configuration described above, since the reception of the next packet can be started even during the analysis of the current packet, the header equivalent data is transmitted to the CPU in the packet analysis element and the special arithmetic unit while maintaining the wire speed. Data can be transferred to the header data storage circuit in the packet analysis element.
[0021]
  Claim9The invention described in the aboveReceiveA payload accommodating unit that accommodates each payload-corresponding data portion of the plurality of received packets separated by the packet separating unit until the processing of the last-stage element is completed, and the payload accommodating unit includes the plurality of packets. Payload equivalent data is stored in one payload data storage memory and managed by a pointer.
  Claim9According to the configuration described in FIG. 1, since only a number of pointers corresponding to the header-corresponding data under packet analysis are managed for one memory, a memory for accommodating each payload data of a plurality of received packets is required. The device can be realized at low cost.
[0022]
  Claim10According to the invention described in the above, the search key output from the one or more packet analysis elements is selected and output to the search table in order to search the search table, and output from the search table based on the search key And a search data selector for outputting the search result to the packet analysis element that has output the search key.
  Claim10According to the configuration described in, when configured with a plurality of packet analysis elements, the search data selector can receive a search key from any packet analysis element, and can transmit a search result to any packet analysis element. Therefore, even a plurality of packet analysis elements can access the search table, increasing the flexibility of program processing.
[0023]
  Claim11In the invention described in the above, the search data selector includes:
  A queue for responding to a difference in search time of each element with respect to the search table is provided, search result data output from the search table is stored in the queue, and output according to an instruction from a packet analysis element as an output destination The configuration is as follows.
  Claim11When the search data selector receives the search result data from the search table with the FIFO, the search result data is received at a timing when the packet analysis element is required even if the response time of the search table changes. it can.
[0024]
  Claim12In the invention described in the above, the update packet transmitter
  When a transmission instruction is output from the packet analysis element at the final stage, after updating the header equivalent data according to the rewrite / insertion / deletion instruction to the header data, Send it as a packet,
  When a discard instruction is output from the packet analysis element in the final stage, it is not a pointer to be read that was scheduled to be combined with the payload equivalent data instructed to be discarded via the payload read control signal to the payload accommodating unit, The pointer to be read next is selected and held until the next read instruction.
  Claim12According to the configuration described in the above, the update packet transmission unit newly generates a header and a payload accommodating unit from the header equivalent data stored via the header data storage circuit according to the analysis result in the packet analysis element. Can generate a new transmission packet from the payload equivalent data stored.
[0025]
  Claim13According to the invention described in the above, the header equivalent data stored in the header data storage circuit in the first stage element, the temporary data stored in the header edit storage circuit, and the packet stored in the header analysis result storage circuit A common sequential number is assigned to each packet of the three systems of analysis results and transferred to the last stage element, and the three systems of data of the same packet are transferred by the sequential number in the last stage element. Consistent configuration.
  Claim13According to the configuration described in the above, information extracted from one received packet for packet analysis passes through three routes, but is transmitted with a common sequential number assigned to each route. By mounting the comparison circuit to be finally detected in the packet analysis element, it is possible to improve the reliability in the packet processing device.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. 1 schematically shows a received packet separator 10 and one or more packet analysis elements (hereinafter also simply referred to as elements) 100 (100a, 100b to 100N) configured by pipelines. A received packet payload storage unit (also simply referred to as a payload storage unit) 20, a search table 40, a search data selector 30, a comparison information storage circuit 50, and an update packet transmission unit 60. Details are shown in FIGS.
[0027]
For example, as shown in FIGS. 14A to 14H, the reception packet separation unit 10 detects a data delimiter of the reception packet 1 having a different format, separates the header equivalent data 11 and the payload equivalent data 12, and each of them is the first stage. To the packet analysis element 100a and the payload accommodating unit 20.
[0028]
Each packet analysis element 100 stores the header equivalent data 11 separated by the packet separation unit 10 and the data from the previous element 100, analyzes the packet type, and updates the header. For example, when the eight types of packets shown in FIGS. 14A to 14H are determined, the first element 100a can be divided into two groups by determining the presence or absence of the VLAN information 407, etc. Next, it can be further divided into two groups by determining the presence / absence of Length information 404 and the like in the second element 100b. Next, one element is determined by determining the presence / absence of SNAP information 406 and the like in the third element 100c. Since the packet type can be specified, the element 100 may be composed of three elements. In addition, if the number of packet types to be determined increases in the future, the amount may be added to the subsequent stage of the third element 100c. Here, each element 100 is configured to execute packet analysis and header conversion processing at a fixed period, and is configured to pass the analysis result to the subsequent element 100 when the next stage uses it.
[0029]
The search table 40 stores search data for converting the header of the received packet 1 into the header of the transmission packet. For example, the correspondence between the MAC-DA information 401 and the destination IP address information 711 is stored. The search data selector 30 outputs the search key data 171a and 171b to 171N extracted from any one or more of the packet analysis elements 100a and 100b to 100N as the search key data 31 to the search table 40. Packet analysis elements 100a and 100b in which any one of the search result data 32a and 32b to 32N selected from the search result data 41 corresponding to the search key data 31 sent from the table 40 by the search data selector 30 is determined. Output to ~ 100.
[0030]
Here, FIG. 2 shows the bus configuration in each element 100 in detail, and reference numerals 111, 112, 113, 141, 142, and 132 indicate that they are transmitted on the bus. The comparison information storage circuit 50 stores, for example, comparison information for determining the packet type as shown in FIGS. 14A to 14H in advance, and the comparison information is stored in the CPUs 110a and 110b to 110N in each element 100. CPU 110a, as read data (111a, 111b-111N), (141a, 141b-141N), respectively, in accordance with access control signals 112a, 112b-112N from decoder 130 and access control signals 132a, 132b-132N from decoders 130a, 130b-130N. 110b to 110N and special arithmetic units 140a and 140b to 140N.
[0031]
The update packet transmission unit 60 includes a header-equivalent data 11 to be updated in accordance with an instruction from the packet analysis element 100N corresponding to the final stage among the one or more packet analysis elements 100a and 100b to 100N, and a transmission waiting packet output from the payload storage unit 20. Payload data 21 is sequentially combined and output.
[0032]
<Received packet separator 10>
The packet processing apparatus shown in FIG. 1 receives a variable-length received packet 1 as shown in FIG. 14, and the received packet separator 10 converts the received packet 1 into a predetermined bit width such as 8 bits (16 bits), 32 bits, or the like. It is presumed that the L2 header and the upper header as shown in FIGS. 14 and 15 are included by taking in and rearranging the data into the data delimiter units starting from the transmission destination MAC address (MAC-DA) 401 as shown in FIG. The header equivalent data 11 corresponding to a predetermined data length and the other payload equivalent data 12 are separated into two data. The header equivalent data 11 is sent to the packet analysis element 100a, and the payload equivalent data 12 is received packet payload accommodating portion. Output to 20 respectively.
[0033]
<Packet analysis element 100>
The header equivalent data 11 separated by the received packet separation unit 10 is stored in the first-stage packet analysis element 100a. The packet analysis element 100 is composed of one or more pipelines. When the packet analysis element 100 is composed of one, the packet analysis element 100a = 100N, and in the case of two or more, the header equivalent data 11 stored in each packet analysis element 100 is obtained. Is output to the subsequent packet analysis elements 100b, 100c to 100N or the update packet transmitter 60 after a predetermined fixed period.
[0034]
When the packet analysis elements 100a, 100b to 100N store the header equivalent data 11, the packet analysis start timing signal for notifying that the bit string that can be analyzed by the packet analysis program is stored in the element 100 within the header equivalent data 11. 152a and 152b to 152N are generated, and the packet analysis program is started to be executed by using the packet analysis start timing signals 152a and 152b to 152N as a trigger.
[0035]
In accordance with the access control signal from each packet analysis program, all packet analysis elements 100 are common to identify whether or not the information is required by the packet analysis program in comparison with the information extracted from the header equivalent data 11 of the received packet 1. Then, the comparison information storage circuit 50 generates comparison information necessary for the packet analysis program from the stored information, so that the data is sequentially identified and extracted from the head of the data. The analysis is advanced, the format is clarified, the execution of the packet analysis program for each packet analysis element 100 such as information extraction from the search key data 31 and the search result data 41 as will be described later is finished, and the subsequent stage is performed after a predetermined fixed period. Packet analysis elements 100a, 100b to 100N (in the case of one, the same packet analysis element 100), the analysis result and the header equivalent data 11 are taken over.
[0036]
The received packet payload accommodating unit 20 stores the payload equivalent data 12 from the received packet separating unit 10, and the header equivalent data 11 that is the other data separated from the received packet separating unit 10 is one or more pipelines The payload equivalent data 12 is held until the update packet transmission unit 60 reads through the packet analysis elements 100a and 100b to 100N having the structure.
[0037]
The transmission packet 61 loaded with a new header determines the transmission destination based on the analysis result by the packet analysis elements 100a and 100b to 100N and the search of the search table 40 as described above. At that time, the search data selector 30 outputs the search key data 31 extracted from the header equivalent data 11 by any of the packet analysis elements 100a, 100b to 100N, and outputs it to the search table 40. An entry (search result data) 41 corresponding to the key data 31 is sent to predetermined packet analysis elements 100a and 100b to 100N.
[0038]
<Update packet transmitter 60>
The update packet transmission unit 60 reads the header equivalent data 11 to be updated according to the instruction from the packet analysis element 100N corresponding to the final stage among the packet analysis elements 100a and 100b to 100N under the control of the payload accommodating unit 20, and the header equivalent data 11 When the final data is detected, the transmission waiting packet payload data 21 corresponding to the header equivalent data 11 is read so as to be sequentially combined, and the transmission packet 61 is output.
With the above-described configuration, one or more packet analysis elements 100 process various processes such as identification of each field in the header equivalent data 11, extraction of search key information, and generation of a new header after receiving a search result. In other words, each packet analysis element 100 can select what kind of processing, that is, a packet analysis program to be executed.
[0039]
<< Detailed Description of Element 100 >>
The packet analysis elements 100a and 100b to 100N shown in FIG.
Received packet separation unit 10, header data storage circuits (also simply referred to as header storage circuits) 150 a, 150 b to 150 N (shown in detail in FIG. 5) that store header equivalent data 11 sent from the preceding element 100,
-Memories 120a, 120b to 120N storing packet analysis programs;
CPU 110a which fetches, decodes and executes each instruction of the packet analysis program stored in each of the memories 120a and 120b to 120N, and outputs special operation instruction instruction signals 115a and 115b to 115N from the fetched results, 110b-110N,
Special operation instruction decode circuits (decoders) 130a and 130b to 130N (shown in detail in FIG. 4) for decoding the special operation instruction instruction signals 115a and 115b to 115N output from the CPUs 110a and 110b to 110N,
Special arithmetic units 140a and 140b to 140N (shown in detail in FIG. 3) that execute special arithmetic instructions 133a and 133b to 133N decoded by the decoders 130a and 130b to 130N, respectively.
It has.
[0040]
In the above configuration, the header data storage circuits 150a, 150b to 150N receive the packet analysis start timing signals 152a, 152b to 152N as special arithmetic units 140a, 140b when they can store a predetermined number of bits of the header equivalent data 11, respectively. Output to ~ 140N. With this as a trigger, the CPUs 110a, 110b to 110N start executing the packet analysis program, and the special arithmetic units 140a, 140b to 140N execute special arithmetic instructions (special arithmetic instruction decode signals 133a, 133b to 133N) in parallel. .
[0041]
At this time, the CPUs 110a, 110b to 110N respectively read the read data 111a, 111b to 111N, and write data 113a by the access control signals 112a, 112b to 112N output to the header data storage circuits 150a, 150b to 150N. 113b to 113N are written, and the CPU 110a and 110b to 110N repeatedly perform transfer with general purpose registers to execute various general purpose operations. The decoders 130a and 130b to 130N decode the special operation instruction instruction signals 115a and 115b to 115N output from the CPUs 110a and 110b to 110N, respectively, and convert the special operation instructions 133a and 133b to 133N into the special operation units 140a, 140b to 140N. Are output to the header data storage circuits 150a and 150b to 150N and the comparison information storage circuit 50 via the bus.
[0042]
Each of the header data storage circuits 150a and 150b to 150N extracts the header extraction information from the stored header of the received packet 1, and outputs it to the special arithmetic units 140a and 140b to 140N as read data 141a and 141b to 141N via the bus. . The comparison information storage circuit 50 extracts comparison information for comparison with the read data 141a, 141b to 141N (header extraction information), and outputs it as read data 141a, b,. The special arithmetic units 140a and 140b to 140N respectively compare the header extraction information and the comparison information, and output the status notification signals 142a and 142b to 142N, which are comparison result information, to the CPUs 110a and 110b to 110N. A packet to be transmitted to the subsequent packet analysis element 100 is determined according to the state notification signals 142a and 142b to 142N.
[0043]
Here, as shown in FIG. 14, the 19th and 20th bytes of the received packet 1 are any of the first 2 bytes of Type information, Length information, or VLAN information. As the header extraction information, the access control signal 132a is output so as to extract the 19th and 20th bytes of the received packet 1 to the header data storage circuit 150a, and the comparison information storage circuit generates 0800h indicating IPv4 as the comparison information. 50 is also output from the header data storage circuit 150a from the access control signal 132a from the decoder 130a, so that the match comparison result signal included in the status notification signal 142 indicates a match between the header extraction information and the comparison information. The received packet 1 is determined to be a DIX packet, and the subsequent packet When the DIX packet processing is started from the packet analysis element 100 and a mismatch is indicated, the 19th and 20th bytes of the received packet 1 from the next time are either Length information or the first 2 bytes of VLAN information. Therefore, a plurality of formats of the received packet 1 can be determined, and a packet process corresponding to the determined format of the received packet 1 can be performed.
[0044]
Each packet analysis element 100 has a pipeline configuration, but each has the same configuration and the same function. Therefore, by changing the packet analysis program installed in each element 100, the configuration is the same without changing hardware. Protocol header analysis can also be performed.
[0045]
Compared to the configuration of the general-purpose CPU 110 alone, each packet analysis element 100 is simply combined with the CPU 110 and the special arithmetic unit 140 to extract information from the header equivalent data 11 and transfer it to the general-purpose register built in the CPU. Since the necessary information can be directly extracted from the header data storage circuit 150 instead of the header analysis after that, the header analysis can be performed at a high speed.
[0046]
Further, each packet analysis element 100 needs to extract different information for each header data storage circuit 150 in accordance with the packet analysis program, and a location for storing comparison information for identifying information by comparison in advance and a packet analysis program Header editing storage circuits 170a and 170b to 170N are provided as locations for storing temporary data generated during execution, and header analysis result storage circuits 160a and 160b to 160N for storing packet analysis results obtained by executing the packet analysis program. To do.
[0047]
For example, when the packet analysis element 100a analyzes the L2 header and the packet analysis element 100b analyzes the IP header, the packet analysis program confirms the normality of the MAC-DA 401 and MAC-SA 402 shown in FIG. Depending on the value of the field, it is possible to identify whether the received packet 1 is in DIX format or LLC + SNAP format.
[0048]
Therefore, a value “05DC” is stored in advance in the header edit storage circuit (also simply referred to as an edit storage circuit) 170a, and a value “4” is stored in advance in the header edit storage circuit 170b. When the value “0800” is extracted from the header data storage circuit 150a, the packet analysis element 100a is compared with “05DC” stored in the header edit storage circuit 170a by a size comparison instruction described later of the special arithmetic unit 140a. If it is determined that the value of “0800” extracted from the header data storage circuit 140a is large, it can be specified that the format is the DIX format. Therefore, the header analysis result storage circuit (also simply referred to as an analysis result storage circuit) 160a is stored in the header analysis result storage circuit 160a. A value indicating that the format is “DIX” is written.
[0049]
Then, in synchronization with the packet analysis completion timing signal 153a, the information in the header analysis result storage circuit 160a is written to the header analysis result storage circuit 160b in the packet analysis element 100b in the subsequent stage. “05DC” of the header edit storage circuit 170a is used only by the packet analysis program of the packet analysis element 100a, and the special arithmetic unit 140b of the packet analysis element 100b uses “DIX” written to the header analysis result storage circuit 160b. From the format information, it is assumed that the IP header is mounted after the 15th byte, and the field of the 15th byte stores “4” stored in the header edit storage circuit 170b in order to identify some values of the version information. ”And“ Match comparison ”.
[0050]
With the above-described configuration, the information extracted and analyzed by the packet analysis element 100N-1 in the preceding stage is duplicated and the analysis processing is not performed in the packet analysis element 100N in the subsequent stage. Therefore, each packet analysis element 100 has an individual packet analysis program. System can be configured efficiently.
[0051]
Each of the header data storage circuits 150a and 150b to 150N of each element 100 shown in FIG. 1 stores the header equivalent data 11 for a predetermined fixed period, and packet analysis start timing signals 152a and 152b for the next fixed period. The CPU 110a, 110b-110N and the special arithmetic units 140a, 140b-140N execute packet analysis processing according to the respective packet analysis programs with each of .about.152N as a base point. It becomes processing.
[0052]
However, if packets can be received during the time during which packet analysis processing is performed, the number of packets that can be processed per unit time increases, resulting in improved throughput. Therefore, even when there is a possibility of receiving a packet while analyzing the header, the header data storage circuits 150a and 150b to 150N are respectively connected to the CPUs 110a and 110b to 110N and the special arithmetic units 140a and 140b to 140N. Packet analysis is received for each packet analysis completion timing signal 153a, 153b to 153N as a two-sided configuration in order not to overwrite the next analysis result newly analyzed for the received packet 1 with the current analysis result that has been analyzed or has been analyzed Switch between the plane and the packet analysis plane and select them alternately.
[0053]
With the above configuration, the header data storage circuits 150a, 150b to 150N are selected in a predetermined order for each of the packet analysis completion timing signals 153a, 153b to 153N, and the information is held. Even when the special arithmetic units 140a and 140b to 140N extract information necessary for packet analysis, the newly received information is stored without losing information including the header of the previous received packet 1 that has already been stored. Can do.
[0054]
<Detailed description of special arithmetic unit 140>
As shown in detail in FIG. 3, the special arithmetic unit 140 (140a to 140N) directly follows the special arithmetic control unit 145, the special arithmetic data control signal 141 and the special arithmetic instruction decode signal 133 from the special arithmetic instruction decode circuit 130. Arithmetic unit group 146 that performs various processes on data 141 read from the header data storage circuit 150, the header analysis result storage circuit 160, the header edit storage circuit 170, and the comparison information storage circuit 50 in a predetermined bit width unit. And a state notification unit 147 and a special calculation result data output unit 148. The arithmetic unit group 146 is an enable instruction signal 1331 for each instruction, and a one-to-many match comparison unit 1461, a magnitude comparison unit 1462, a data transfer unit 1463, a partial data transfer unit 1464, A product unit 1465, a logical sum unit 1466, an adder unit 1467, a bit shift unit 1468, a post-bit shift logical sum unit 1469, a checksum operation unit 1470, and an indirect address data transfer unit 1471 are provided.
[0055]
The one-to-many match comparison unit 1461 includes first data and second data (a header data storage circuit 150, a comparison information storage circuit 50, an analysis result storage circuit 160, a first calculation data control signal 141 (141a to 141N), Read data of the edit memory circuit 170), and the first data and the second data are headed and the continuous data are simultaneously compared. The magnitude comparison unit 1462 determines whether the first data is large or the second data is large with respect to the bit widths specified by the bit mask signal 1332 for the first data and the second data, respectively. Compare according to 1334. The data transfer unit 1463 transfers the first data extracted from any one of the storage circuits 150, 50 to the different storage circuits 50, 150, and the partial data transfer unit 1464 uses the bit mask signal 1332 of the first data. Only the designated bit width is transferred to the different storage circuits 50 and 150.
[0056]
A logical product unit 1465, a logical sum unit 1466, and an adder unit 1467 respectively perform logical sum, logical product, and addition of the first data and the second data. The bit shift unit 1468 shifts the first data by the number of bits indicated by the second data to the right or left indicated by the bit shift direction instruction signal 1333. The post-bit-shift logical sum unit 1469 performs a logical sum of the second data and the data shifted by the number of bits designated by the immediate data 1335 in the direction indicated by the bit shift direction instruction signal 1333 by the combination operation. In the checksum calculation unit 1470, the first data (first operand) represents the head pointer (starting point), and the data length specified by the second data (second operand) is added over a plurality of clocks. The indirect address data transfer unit 1471 transfers the data at the address indicated by the data output from any one of the storage circuits 150 and 50 designated with the second data as an address to the storage circuits 50 and 150 indicated by the first data.
[0057]
The status notification unit 147 notifies the CPU 110 of the comparison result executed by any one of the comparison instructions (1461, 1462) in the computing unit group 146 and the packet analysis start timing signal 152 output from the header data storage circuit 150. Generated as signal 142. The special operation result data output unit 143 generates write data 143 to be written to an address designated via the decode circuit 130 by an instruction (1463 to 1471) other than comparison in the arithmetic unit group 146, and writes this to the header storage circuit 150. .
[0058]
With the above-described configuration, the special arithmetic unit 140 is not the arithmetic unit group 146 that merely analyzes the header shown in FIG. 14 or FIG. Can be used by changing the program, and data can be extracted directly from the header data storage circuit 150, the header analysis result storage circuit 160, the header edit storage circuit 170, and the comparison information storage circuit 50 without fetching the data into the CPU 110. The program can be executed while maintaining packet processing. Further, by outputting the status notification signal 142 to the CPU 110, packet analysis can be performed by a program to be executed next using program branching or comparison result determination.
[0059]
<Detailed Description of Special Operation Instruction Decode Circuit 130>
As shown in detail in FIG. 4, in the special arithmetic instruction decoding circuit 130 constituting the decoder 130 of FIG. 1, the instruction instruction analysis unit 131 includes header data to be read access included in the special arithmetic instruction instruction signal 115 from the CPU 110. Read address generation of information to be extracted from the storage circuit 150, the header editing storage circuit 170, or the comparison information storage circuit 50, and a special operation execution result (write data) 143 are sent to the header data storage circuit 150, the header analysis result storage circuit 160, the header As write destination addresses of any one of the edit memory circuits 170, three addresses of a first address 1321, a second address 1323, and a third address 1325, and first and second addresses corresponding to the addresses 1321, 1323, and 1325, respectively. , Third write or read enable signal 13 2, 1324, 1326 including special operation data extraction access control signal 132, enable instruction signal 1331 for each instruction required when executing the special operation instruction, bit mask signal 1332, and bit shift direction instruction signal 1333 A special operation instruction decode signal 133 including a direction instruction signal 1334 and immediate data 1335 of an operand of an instruction described in the program can be output.
[0060]
With the above-described configuration, the special arithmetic unit 140 includes a plurality of arithmetic unit groups 146, but can perform a plurality of arithmetic operations using a common interface.
[0061]
<Detailed Description of Header Data Storage Circuit 150>
As shown in detail in FIG. 5, the header data storage circuit 150 includes a header register write select circuit 156, a two-sided header register 157, a packet analysis timing generation circuit 154, a header register read select circuit 158, and a header register pointer. A selection unit 159.
[0062]
The header register write select circuit 156 detects that the header equivalent data 11, the write data 113 from the packet analysis CPU 110 or the write data 143 (143 a to 143 N) from the special arithmetic unit 140 is input, and has a two-plane configuration. The write pointer 1561 is generated by selecting the write destination register side of the header register 157, and this is output to the header register 157. The header register 157 has a two-surface configuration, that is, a surface written during packet reception and a surface analyzed by the CPU 110 or the special arithmetic unit 140, and alternately stores the header equivalent data 11 by a packet analysis surface selection signal 1541 described later. .
[0063]
The packet analysis timing generation circuit 154
Only when the header equivalent data 11 is detected, the header equivalent data 11 having a predetermined number of bits is written to the header register 157 using the input data detection notification signal 1562 generated from the header register write select circuit 156 as a trigger. A packet analysis start timing signal 152 to be notified to the computing unit 140;
A packet analysis plane selection signal 1541 for selecting the plane of the received packet write side and the packet analysis (read) side of the header register 157;
A packet analysis completion timing signal 153 indicating the data takeover timing of the storage circuit 150 to the subsequent packet analysis element 100;
Generate.
[0064]
The header register read select circuit 158 generates the head register read pointer 1581 from the packet analysis completion timing signal 153 from the packet analysis timing generation circuit 154 and reads the data stored in the header register 157. . The header register pointer selection unit 159 generates pointer information and a read or write enable signal 112 for accessing the header register 157 output to generate header extraction information from the CPU 110, or header extraction information from the special arithmetic unit 140. To the header register write select circuit 156 or the header register read select circuit 158 for determining whether or not the packet analysis is in progress, the pointer information for accessing the header register 157 and the read or write enable signal 132 to be selected are selected. Output.
[0065]
The header data storage circuit 150 configured as described above will be described with reference to FIG. FIG. 11 shows an example in which there are three packet analysis elements 100 (#a, #b, #c) with respect to the packet length that can be stored only in the header data storage circuit 150. When the header equivalent data H of the received packet 1 is detected, the header register 157 is selected in order from the pointer 0 in accordance with the write pointer 1561 from the header register write select circuit 156 for the header register 157 in a predetermined bit width unit. The first header equivalent data H is stored in plane-1.
Here, in FIG. 11, only “H” is shown as the header equivalent data, but actually “H + P # x” is the header equivalent data, which is the “predetermined bit width”. Also, the fixed time (fixed period) shown in FIG. 11 is “H + P # x” + α (α: Ethernet (R) standard minimum gap between packets). In FIG. 12, the header equivalent data is “H + P # x (part)” and the payload equivalent data is “P # x (remaining)”.
[0066]
When the packet data storage in the header register 157 is completed, a packet analysis start timing signal 152 is output from the packet analysis timing generation circuit 154 to the special arithmetic unit 140, and this timing generation also indicates that a fixed time has elapsed. Thereafter, when a new packet can be received and the header register write selection circuit 156 detects the new header equivalent data H, the selection plane-2 of the header register 157 that has completed packet storage is selected first, and the second Header equivalent data H can be stored.
[0067]
Using the packet analysis start timing signal 152 for the first header equivalent data H + P # x as a trigger, the CPU 110 and the special arithmetic unit 140 in the packet analysis element perform analysis. By outputting a packet analysis completion timing signal 153 indicating that the analysis has been completed to the analysis result storage circuit 160, the packet analysis element 100 at the next stage is notified that transfer preparation has been completed. By generating the packet analysis completion timing signal 153 (153a to 153N) within a fixed time, a fixed time triggered by the packet analysis start timing signal 152 generated from the packet analysis timing generation circuit 154 is periodically repeated. Pipeline order can be properly followed.
From the packet reception to the packet analysis completion, the processing of the first header equivalent data H has selected the selection plane -1 with the packet analysis plane selection signal 1541, and the generation of the packet analysis completion timing signal 153 generates the header register selection plane. The first header equivalent data H that has been analyzed in −1 is transferred to the subsequent packet analysis element 100 as takeover data 151. At this time, the second header equivalent data H stored in the selection plane-2 is also stored, the packet analysis start timing signal 152 is output, and the above-described operation is repeated every fixed time.
[0068]
In addition, it is possible to achieve both packet reception and packet analysis while arbitrating write / read contention from the CPU 110 and the special arithmetic unit 140 during header analysis and the header equivalent data H from the received packet separation unit 10.
Although not shown in the figure, a flag indicating the end of the packet is written in the header storage circuit 150 when the header equivalent data and the payload equivalent data are stored. Thus, it is determined whether or not the payload equivalent data is read after the header equivalent data depending on whether or not the packet end flag is detected.
[0069]
<< Detailed Description of Payload Storage Unit 20 >>
As shown in detail in FIG. 6, the payload storage unit 20 includes a payload data storage memory (also simply referred to as a memory) 22 for storing payload equivalent data 12, a payload data write circuit 23, a header corresponding pointer generation circuit 24, a pointer A holding circuit 25, a read pointer generation circuit 26, and a payload data read circuit 27 are provided. The payload data writing circuit 23 generates an address and a write enable signal for writing data to the payload data storage memory 22. The header corresponding pointer generation circuit 24 generates a write end pointer for each received packet in order to store (write) the payload equivalent data 12 corresponding to the header equivalent data 11 analyzed by the packet analysis element 100 when the transmission packet is generated. .
[0070]
The pointer holding circuit 25 includes a plurality of registers (for received packets # 1 and # 2 to #Y in the figure) in order to hold pointer values for each received packet on one payload data storage memory 22. ing. Based on the payload read control signal 62 from the update packet transmission unit 60, the read pointer generation circuit 26 generates a pointer value from the pointer that has just been read from the pointer holding circuit 25 to the write end pointer. The payload data read circuit 27 generates an address and a read enable signal for reading the payload equivalent data 12 from the payload data storage memory 22 using the payload read control signal 62 from the update packet transmitter 60 as a trigger.
[0071]
The payload accommodating unit 20 having the above-described configuration will be described with reference to FIG. FIG. 12 shows an example in which there are three packet analysis elements 100 (#a, #b, #c) with respect to the packet length stored separately in the header data storage circuit 150 and the payload accommodating unit 20. Received packet 1 is separated into header-equivalent data H (actually “H + P # x (part)”) and payload-equivalent data P (actually “P # x (remaining)”) by received packet separator 10. When the payload data writing circuit 23 detects the payload equivalent data P, an address and a write enable signal are generated and written in order from address 0 in order to write to the payload data storage memory 22 in a predetermined bit width unit.
[0072]
When the payload data P # 1 has been written to the payload data storage memory 22, the header corresponding pointer generation circuit 24 extracts the address value at the end of the writing in order to store that the payload data is the first header equivalent data H. Then, it is stored (written) in the first header equivalent data register of the pointer holding circuit 25. The subsequent payload equivalent data P # 2 of the second header equivalent data is written from the address value +1 at the end of the writing of the first payload equivalent data P # 1, and the address value at the end of the writing is used for the second header equivalent data. Store in the register of the pointer holding circuit 25. Similarly, the third payload equivalent data P # 3 is stored.
[0073]
When the analysis of the first header equivalent data H by the packet analysis elements #a, #b, and #c is completed, the packet analysis element #c transfers the packet to the destination of the result obtained from the table search to the header edit storage circuit 170c. Or an instruction to insert or delete VLAN, for example, and write the header control data 172N together with the header data 151N that became a new header in synchronization with the packet analysis completion timing signal 153c. Output to.
[0074]
The update packet transmission unit 60 performs packet update processing such as insertion or deletion into new header data. If the flag indicating the end of the packet cannot be detected when the update header data has been processed to the end, the subsequent payload-corresponding data exists and is combined into one packet. A payload read control signal 62 is output.
[0075]
The first header stored in the pointer holding circuit 25 from the pointer 0 via the payload data read circuit 27 by the read pointer generation circuit 26 so that the first payload equivalent data following the first header equivalent data can be read according to the control signal 62. The address up to the write end pointer value of the corresponding data is instructed to the payload data storage memory 22 to read the data. When reading to the write end pointer value stored in the pointer holding circuit 25 is completed, the read pointer generation circuit 26 stores the address at that time and holds it until the next payload read control signal 62 is received.
When the packet discard instruction is included in the header control data 172N, the read pointer generation circuit 26 shown in FIG. 6 selects the pointer holding value to be read next without reading the payload equivalent data 12 as the control signal 62. .
[0076]
<< Detailed Description of Search Data Selector 30 >>
As shown in detail in FIG. 7, the search data selector 30 includes a search key selection unit 33, a search result transmission unit 34, and a search result reception FIFO (queue) 35. The search key selection unit 33 receives the search key data 171 output from any one of the packet analysis elements 100a, 100b to 100N, and sends the search key data 171a, 171b to 171N (any one) to the search table 40. Output. The search result sending unit 34 receives the search result 41 from the search table 40 via the FIFO 35, and designates the search results 32a, 32b to N corresponding to the search key data 171 as the designated packet analysis elements 100a, 100b to 100N. Output to.
[0077]
With the above-described configuration, the search data selector 30 is necessary for a program that only analyzes a MAC address and a program that also analyzes an IP header, an upper header, and the like, for example, when performing individual analysis for each packet analysis element 100. Since the number of packet analysis elements changes, the search key data 171 is not necessarily output from the fixed packet analysis element 100, but a packet analysis program for generating the search key data 171 based on information by packet analysis is implemented. The search key data 171 from the packet analysis element 100 being selected is selected and output to the search table 40. Further, the search result data 32 corresponding to the search key data 171 is output only to the packet analysis element 100 used for generating a new header.
[0078]
Further, the search result data 41 output from the search table 40 is accumulated in the search result reception FIFO 35, and the search result data 32 is not output until there is an instruction from the packet analysis element 100 as the output destination. For example, when an update header is generated by the packet analysis elements 100a, 100b, and 100c, the search key data 171 is transmitted from the packet analysis element 100b and the search result data 32 is required by the element 100c, and the search table 40 itself It is possible to cope with a processing time delay and a difference in search time by the plural search key data 171.
[0079]
<< Detailed Description of Update Packet Transmitter 60 >>
As shown in detail in FIG. 8, the update packet transmission unit 60 includes a control signal generation unit 63 that generates a payload read control signal 62 and a packet generation unit 64. The packet generation unit 64 inserts instructions into the header data output from the packet analysis element 100N (a = N in the case of one packet analysis element) corresponding to the final stage among the one or more packet analysis elements 100a and 100b to 100N. In accordance with the header control data 172N including the signal 1721N, the deletion instruction signal 1722N from the header data, and the transfer or discard instruction signal 1723N, the header equivalent data 151N to be updated, and the transmission waiting packet payload data 21 read from the payload accommodating unit 20 Combine serially.
[0080]
With the above-described configuration, the update packet transmission unit 60 synchronizes with the packet analysis completion timing signal 153 from the packet analysis element 100N, the takeover header data 151N, the insertion instruction signal 1721N into the header data from the header edit storage circuit 170N, and the header. The header control data 172N including the deletion instruction signal 1722N from the data and the transfer or discard instruction signal 1723N is received. The takeover header data 151N is updated to a new header by various instruction signals, combined if necessary, and output as a transmission packet 61.
[0081]
<< Modification of Packet Analysis Element 100 >>
In the modified example of the packet analysis element 100 shown in FIG. 9, sequential number comparison circuits (also simply referred to as comparison circuits) 180N and 181N are added to the configuration shown in FIG.
[0082]
Sequential number comparison units 180N and 181N receive search key data 171 for table search via header data storage circuit 150, header analysis result storage circuit 160, and header edit storage circuit 170 in order to analyze the header of received packet 1. Since one received packet information is transmitted through three routes of sending and receiving a search result, the packet analysis element in the first stage is used to detect that the information of the same received packet is not prepared due to a failure in one of the routes. A sequential number is assigned by the packet analysis program 100a, and the sequential number 162N transmitted via the header analysis result storage circuit 160 and the sequential number transmitted via the header data storage circuit 150 are given to the final stage of the packet analysis element 100. With the number 1571N Compare results, and outputs two kinds of comparison result of the header analysis result storage circuit 160 compares the sequential number 173N transmitted in sequential number 162N and the search table 40 which is transmitted via the result.
[0083]
The transfer image of the sequential number with the above configuration will be described with reference to FIG. When the packet analysis element 100 has three stages (#a, #b, #c), the search data selector 30 outputs the search key data 171a and the element 100c receives the search result 32c. When the packet analysis program of the packet analysis element 100a writes the analysis result of the received packet 1 to the header analysis result storage circuit 160a, the sequential number #A is also written to the header analysis result storage circuit 160a. Similarly, the sequential number #A is written to the header data storage circuit 150a that stores the header equivalent data that is the basis of this analysis result.
[0084]
The sequential number #A is also written and transferred to the search key data 171 generated based on the information extracted from the header equivalent data 12 via the header edit storage circuit 170a. These sequential numbers #A are synchronized with the packet analysis completion timing signal 153a, the header data storage circuit 150a is sent to the header data storage circuit 150b together with the header equivalent data 11, and the header analysis result storage circuit 160a is the analysis result information. One is transferred to the analysis result storage circuit 160b, and the header edit storage circuit 170a is not directly transferred to the edit storage circuit 170b, but transferred as search key data 171 to the search table 40. In the search result data 32 corresponding to the search key data 171, the sequential number #A multiplexed in the search key data 171 is stored in the header editing storage circuit 170c of the packet analysis element 100c. And the #A value is output from the table path sequential number 173c.
[0085]
In the same manner as described above, the elements 100a to 100b and the elements 100b to 100c are also transferred between the elements 100 in synchronization with the packet analysis completion timing signal 153, and the #A value is output from the sequential number 1571N of the header data storage circuit 150 path. To do. The #A value is output from the sequential number 162N of the header data analysis result storage circuit 160 path. The sequential numbers of these routes are compared, and since all are #A values, it can be detected that one packet information is normally transferred through three routes.
[0086]
【The invention's effect】
As described above, according to the configuration described in claims 1 and 2, processing such as identification of each field in the received packet header, extraction of search key information, and generation of a transmission packet header after receiving the search result is received. Since it is possible to select the number of packet analysis elements to be processed according to the type of packet and the type of processing to be performed by each packet analysis element, it is not necessary to prepare a high-performance CPU.
According to the configuration of claim 3, since the transfer of information between the packet analysis elements of the pipeline configuration is also performed with a predetermined timing signal, no special flag (register) and processing are required. All can be assigned to individual packet analysis processing.
According to the configuration of claim 4, when configured with one or more packet analysis elements, the information extracted and analyzed by the packet analysis element in the previous stage is not processed redundantly. Distribution can be flexibly handled, and all memory sizes for storing programs can be assigned to individual packet analysis processes.
According to the configuration of the fifth aspect, since the analysis result information of the current packet can be held even during reception of the next packet, the packet analysis result information can be transmitted to the subsequent packet analysis element without lowering the throughput.
According to the configuration of the sixth aspect, since the special arithmetic unit can directly read and write data in the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit, By changing the instruction order of operation instructions, design changes and function additions can be realized, and high-speed packet processing can be maintained.
According to the structure of Claim 7, a design change and a function addition are realizable.
According to the configuration of the eighth aspect, information necessary for executing the special operation instruction can be directly read and written from the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. In addition, an access control signal such as an address can be generated, and various enable signals necessary for executing instructions can be generated.
According to the configuration of claim 9, since the reception of the next packet can be started even during analysis of the current packet, the header equivalent data is transmitted to the CPU and special arithmetic unit in the packet analysis element while maintaining the wire speed, In addition, data can be taken over to the header data storage circuit in the packet analysis element at the subsequent stage.
According to the configuration of the tenth aspect, since only a number of pointers corresponding to the header-corresponding data under packet analysis are managed for one memory, each payload data for receiving a plurality of received packets is stored. A device can be realized at low cost without the need for a memory.
According to the configuration of claim 11, when configured with a plurality of packet analysis elements, the search data selector can receive a search key from any packet analysis element, and the search result is sent to any packet analysis element. Therefore, even a plurality of packet analysis elements can access the search table, which increases the flexibility of program processing.
According to the configuration of claim 12, when the search data selector receives the search result data from the search table by the FIFO, the search result is obtained at a timing when the packet analysis element is necessary even if the response time of the search table changes. Can receive data.
According to the configuration of claim 13, the update packet transmission unit is configured to generate a header newly generated from the header equivalent data stored via the header data storage circuit according to the analysis result of the packet analysis element. A new transmission packet can be generated from the payload equivalent data stored in the payload storage unit.
According to the configuration of claim 14, information extracted from one received packet for packet analysis passes through three paths, but is transmitted with a common sequential number assigned to each path. By mounting a comparison circuit for finally detecting consistency in the packet analysis element, it is possible to improve the reliability in the packet processing apparatus.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of a packet processing apparatus according to the present invention.
FIG. 2 is a block diagram showing in detail the bus configuration in the packet analysis element of FIG.
FIG. 3 is a block diagram showing a special arithmetic unit in FIG.
4 is a block diagram showing a special operation instruction decode circuit in FIG. 1. FIG.
FIG. 5 is a block diagram showing a header data storage circuit in FIG.
6 is a block diagram showing a received packet payload accommodating unit in FIG. 1;
7 is a block diagram showing a search data selector in FIG. 1. FIG.
FIG. 8 is a block diagram showing an update packet transmission unit in FIG.
FIG. 9 is a block diagram showing a modification in which a sequential number comparison circuit is added to the packet analysis element in FIG.
FIG. 10 is an image diagram showing the sequential number comparison of FIG. 9;
FIG. 11 is a processing timing chart when three packet analysis elements according to the present invention are used, the minimum packet length, and the minimum inter-packet gap.
FIG. 12 is a processing timing chart when three packet analysis elements according to the present invention are used, an arbitrary packet length, and an arbitrary inter-packet gap.
FIG. 13 is a block diagram showing a conventional packet processing apparatus.
FIG. 14 is a diagram illustrating a configuration of a lower layer header of a conventional packet
FIG. 15 is a diagram showing the configuration of a conventional IPv4 header
[Explanation of symbols]
1 Received packet
10 Received packet separator
11 Header equivalent data
12 Payload equivalent data
20 Received packet payload storage
21 Waiting packet payload data
22 Payload data storage memory
23 Payload data writing circuit
24 Header compatible pointer generation circuit
25 Pointer holding circuit
26 Read pointer generation circuit
27 Payload data reading circuit
30 Search data selector
40 Search table
50 Comparison information storage circuit
60 Update packet transmitter
61 Transmitted packets
62 Payload read control signal
63 Payload read control signal generator
64 packet generator
100, 100a, b, ..., N Packet analysis element
110a, b, ..., N CPU
111a, b,..., N CPU read data from storage circuits 150, 50
112a, b,..., N Memory circuit 150, 50 access control signal from CPU
113a, b,..., N Memory circuit 150, 50 write data from CPU
115a, b, ..., N Special operation instruction instruction signal
120a, b, ..., N CPU program storage memory
130a, b, ..., N Special operation instruction decode circuit (decoder)
131 Instruction instruction analysis unit
132a, b, ..., N Special operation data extraction access control signal
133a, b, ..., N Special operation instruction decode signal
140, 140a, b, ..., N Special arithmetic unit
141, 141a, b,..., N Special operation data control signal (read data from header data storage circuit 150 and comparison information storage circuit 50 of special operation unit)
142a, b, ..., N state notification signal
143, 143a, b, ..., N Write data to the storage circuits 150, 50 of the special arithmetic unit
145 Special calculation control unit
146 arithmetic unit group
147 Status notification part
148 Special operation result data output part
150, 150a, b,..., N header data storage circuit
151a, b, ..., N Inter-element takeover header data
152, 152a, b, ..., N Packet analysis start timing signal
153, 153a, b, ..., N Packet analysis completion timing signal
154 packet analysis timing generation circuit
156 Header register write select circuit
157 Header register
158 Header register read select circuit
159 Header register pointer selector
160, 160a, b,..., N analysis result storage circuit
161a, b, ..., N Inter-element takeover analysis result data
162N Header analysis result storage circuit path sequential number
170, 170a, b,..., N header edit memory circuit
171, 171 a, b,..., N Search key data
172a, b, ..., N Header control data
1331 Enable instruction signal for each instruction
1332 bit mask signal
1333 bit shift direction indication signal
1334 Large / small comparison direction indication signal
1335 immediate data
1321 First address for special operation
1322 (For special operation) First write or read enable
1323 Second address (for special operation)
1324 (For special operation) Second write or read enable
1325 (for special operation) 3rd address
1326 (for special operation) 3rd write or read enable
1461 One-to-Many Match Comparison Unit
1462 Comparison section
1463 data transfer unit
1464 Partial data transfer unit
1465 AND
1466 OR part
1467 Adder
1468 bit shift section
1469 Bitwise OR part
1470 Checksum calculation unit
1471 Indirect address data transfer unit
1541 Packet analysis plane selection signal
1561 Header register write pointer
1571 header data storage circuit path sequential number
1581 Header register read pointer
1721 Header insertion instruction data
1722 Header deletion instruction data
1723 Packet transfer discard instruction signal
173N Search table route sequential number

Claims (13)

A search data storage step for storing search data for converting a header of a received packet into a header of a transmitted packet in a search table;
A comparison information storing step for storing comparison information for determining the type of the received packet;
A received packet separating step for detecting a data delimiter of the received packet and separating a header equivalent data portion and a payload equivalent data portion;
The pipeline is configured by the number according to the type of the received packet and / or the packet analysis content assigned in advance, and is stored by the comparison information storage step and the header equivalent data portion separated by the received packet separation step at a fixed period. Comparing the received comparison information to determine the type of the received packet, searching the search table, updating the header-corresponding data as necessary, and outputting to the next stage. One or more packet analysis steps to take over to the next stage when
An update packet transmission step for outputting the payload corresponding data portions separated by the reception packet separation steps header corresponding data from the last stage of the one or more packet analysis step as forming combined and transmitted packets,
Prepared ,
Each of the packet analysis steps includes:
A header data storage step of storing the header equivalent data portion separated by the received packet separation step and outputting a packet analysis start timing signal after completion of the storage;
A header editing storage step for extracting and storing different information in the header data storage step according to a packet analysis program, and for storing the comparison information and temporary data generated during execution of the packet analysis program; ,
A header analysis result storage step for storing a packet analysis result obtained by executing the packet analysis program;
Using a general-purpose register, a general-purpose calculation step for starting execution of a packet analysis program triggered by a packet analysis start timing signal output from the header data storage unit;
Based on a special operation instruction included in the packet analysis program, the data of the result of the header data storage step, the header edit storage step, the header analysis result storage step or the comparison information storage step is directly read and read. A logical operation for packet analysis is performed on the data, and the result is stored as the result data of the header data storage step, the header edit storage step, the header analysis result storage step or the comparison information storage step. A calculation step,
A packet processing method. A search table for storing search data for converting the header of the received packet into the header of the transmitted packet;
A comparison information storage unit for storing comparison information for determining the type of the received packet;
A received packet separator that detects a data delimiter of the received packet and separates a header equivalent data portion and a payload equivalent data portion;
A pipeline is configured with a number corresponding to the type of the received packet and / or the packet analysis content allocated in advance, and is stored in the header equivalent data portion separated by the received packet separation unit at a fixed period and the comparison information storage unit. Comparing the received comparison information to determine the type of the received packet, searching the search table, updating the header-corresponding data as necessary, and outputting to the next stage. One or more packet analysis elements to take over to the next stage when
And an update packet transmission unit which outputs the payload corresponding data portions separated by the header corresponding data and the received packet separation section from the final stage of the one or more packet analysis element as sintering combined and transmitted packets, comprising,
Each of the packet analysis elements includes:
A header data storage unit that stores a header equivalent data portion sent from the received packet separation unit and outputs a packet analysis start timing signal after the storage is completed;
A header editing storage unit for extracting and storing different information from the header data storage unit according to a packet analysis program, and for storing the comparison information and temporary data generated during execution of the packet analysis program; ,
A header analysis result storage unit for storing a packet analysis result obtained by executing the packet analysis program;
A general-purpose arithmetic unit having a general-purpose register and starting execution of a packet analysis program triggered by a packet analysis start timing signal output from the header data storage unit;
Based on a special operation instruction included in the packet analysis program, the header data storage unit, the header edit storage unit, the header analysis result storage unit, or the comparison information storage unit is directly read and read. A special operation that performs a logical operation for packet analysis on data and directly writes a result to the header data storage unit, the header edit storage unit, the header analysis result storage unit, or the comparison information storage unit With the calculator
A packet processing apparatus. Each of the packet analysis elements includes :
Comprising a memory for storing the packet analysis program skilled the packet analysis element is executed,
3. The packet processing apparatus according to claim 2, wherein execution of the packet analysis program is completed after the fixed period, and a packet analysis completion timing signal is output to a next-stage element or an update packet transmission unit. Each of the packet analysis elements further includes:
Packet processing apparatus according to claim 3, characterized in that for outputting data stored in synchronization with the prior SL packet analysis completion timing signal at the header analysis result storage unit to the header analysis result storage unit of the subsequent packet analysis element . The header analysis result storage unit
While analyzing the current header, the next packet is received and the analysis result of the current header is not overwritten with the analysis result of the next header. The packet processing device according to claim 4, wherein the packet processing device stores the information alternately. The special arithmetic unit further packet processing apparatus according to claims 3 to any one of the 5, characterized in that for performing a logical operation of immediate data included in the packet analysis program. The special operation instruction is
The header data storage unit , the header analysis result storage unit , the access control signal for directly reading and writing data in any one of the header edit storage unit and the comparison information storage unit , and various types necessary for instruction execution The packet processing apparatus according to claim 2 , further comprising an enable signal. The header data storage unit has a header register that alternately stores the header equivalent data of each packet in a two-plane configuration of a plane that is written during packet reception and a plane that is analyzed by the general-purpose arithmetic unit and the special arithmetic unit. packet processing apparatus according to any one of claims 3, characterized in that it comprises 6. A payload accommodating unit that accommodates each payload-corresponding data portion of the plurality of received packets separated by the received packet separating unit until the processing of the final stage element is completed, and the payload accommodating unit includes the plurality of payload accommodating units packet processing apparatus according to any one of claims 2 to 8, characterized in that managed by the pointer contains the payload corresponding data packets into one payload data storage memory. The search key output from the one or more packet analysis elements is selected to search the search table, and the search key is output to the search table. The search result output from the search table based on the search key is packet processing apparatus according to any one of further comprising a retrieval data selector for outputting the packet analysis element search outputting the key claim 2, wherein the 9. The search data selector is
A queue for responding to a difference in search time of each element with respect to the search table is provided, search result data output from the search table is stored in the queue, and output according to an instruction from a packet analysis element as an output destination The packet processing device according to claim 9 . The update packet transmitter is
When a transmission instruction is output from the packet analysis element at the final stage, after updating the header equivalent data according to the rewrite / insertion / deletion instruction to the header data, Send it as a packet,
When a discard instruction is output from the packet analysis element in the final stage, it is not a pointer to be read that was scheduled to be combined with the payload equivalent data instructed to be discarded via the payload read control signal to the payload accommodating unit, select the pointer to read next packet processing apparatus according to any one of claims 2 to 11, characterized in that hold up the next read instruction. Three systems of header equivalent data stored in the header data storage unit , temporary data stored in the header edit storage unit , and packet analysis results stored in the header analysis result storage unit in the first stage element The same sequential number is assigned to each data packet and transferred to the next stage element, and the three systems of data of the same packet are matched by the sequential number in the last stage element. Item 12. The packet processing device according to any one of Items 2 to 11 .

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