JP3905660B2 - Microcomputer and microcomputer system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer incorporating a central processing unit and a data transfer device, and further to a microcomputer system using such a microcomputer.
[0002]
[Prior art]
As an example of a microcomputer, “LSI handbook” P540 and P541 issued by Ohm on November 30, 1984 includes a ROM (read only memory) for holding programs and a data holding centering on a central processing unit (CPU). For example, a functional block such as a random access memory (RAM) and an input / output circuit for inputting / outputting data is formed on one semiconductor substrate.
[0003]
Some microcomputers have a built-in direct memory access controller (DMAC) and can transfer data independently of the CPU. JP-A-5-307516 is an example of a document describing such a microcomputer.
[0004]
Some microcomputers have an external bus right release function for releasing the bus right to the outside and can operate the internal bus such as ROM read by the CPU even while the external bus right is released. . If a DMAC is connected to the external bus of such a microcomputer, the operation of the internal bus such as ROM read by the CPU and the data transfer on the external bus by the external DMAC can be performed in parallel.
[0005]
[Problems to be solved by the invention]
The present inventor studied the microcomputer with built-in DMAC, a system using the microcomputer, and a system in which a DMAC is connected outside the microcomputer having the external bus release function.
[0006]
First, in a microcomputer with built-in DMAC, the DMAC can be activated by an interrupt request, and can perform a repeat mode, a block transfer mode, and the like. In a system such as a printer, a microcomputer with a built-in DMAC is suitable for controlling stepping motors (plural), controlling printer print data, and storing received data in a memory. The DMAC has a plurality of data transfer channels. be able to.
[0007]
However, the DMAC transfer control is independent of the operation of the CPU. However, since the bus is shared, the bus cycle required for data transfer stops the operation of the CPU. For example, when data is transferred from the RAM to the input / output circuit by the built-in DMAC, if the RAM access is set to two states, the input / output circuit access is set to three states, and one dead cycle is included, the data transfer includes six states. Cost. During this period, the CPU cannot use the bus. Although not particularly limited, here, one cycle of a reference clock of a data processing LSI such as a microcomputer is defined as one state.
[0008]
On the other hand, in a system in which a DMAC is connected to the outside of the microcomputer having the external bus release function, the operation of the internal bus such as the ROM read of the CPU and the data transfer on the external bus by the external DMAC are performed. Can be done in parallel.
[0009]
However, when the external bus right is released, it is necessary to recognize an acknowledge signal, a request signal, etc. with the outside when the bus right is exchanged, and at least an extra operation time is required. Further, in order to prevent the microcomputer and the external DMAC bus from colliding with each other, there is a time when both do not use the bus, and an overhead unrelated to the actual operation is likely to occur. If overhead occurs before and after a single data transfer, it cannot be ignored compared to the actual data transfer time. Moreover, if a general-purpose DMAC is used for the DMAC outside the microcomputer, functions that are not used are generated, which is not a good solution in terms of cost effectiveness. Further, although it is possible to individually develop a DMAC suitable for each system, newly developing a separate LSI from the microcomputer tends to be disadvantageous in terms of manufacturing costs.
[0010]
Further, for example, in a system such as a printer, during printing, it is necessary to drive a stepping motor for driving the printer, and it is also necessary to perform data processing unique to the system such as processing of print data. It is necessary to receive data asynchronously with the operating state of the printer. In order to increase the speed and accuracy of the printer, it is necessary to improve the processing capacity of the microcomputer.
[0011]
As described above, the present inventor has found the importance of the viewpoint of incorporating a data transfer device such as DMAC in a microcomputer and improving the total performance of processing by the microcomputer.
[0012]
An object of the present invention is to provide a microcomputer capable of improving the total performance of data processing by a microcomputer incorporating a data transfer device such as a DMAC.
[0013]
Another object of the present invention is to minimize the increase in physical and logical scale and to enable parallel processing of data transfer control on the external bus of the microcomputer and CPU operation such as internal bus access by the built-in CPU. It is to provide a microcomputer capable of performing the above.
[0014]
Still another object of the present invention is to enable data transfer control between a microcomputer and the outside and arithmetic processing inside the microcomputer to be performed in parallel, with little processing overhead and an increase in physical scale. It is another object of the present invention to provide a microcomputer system that can be minimized.
[0015]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0017]
That is, a first data transfer device (4) such as a direct memory access controller for controlling data transfer on the external bus of the microcomputer (1) is provided, and the first data transfer device on the external bus The data transfer at the same time and the instruction execution using the first internal bus (IAB, IDB) by the data processing device (2) such as CPU can be performed in parallel. More specifically, the microcomputer (1) performs bus control and arbitration of the bus right, bus interface means (72) that enables the first internal bus or the first data transfer device to be connected to an external bus. Bus control means (12), wherein the bus control means is an access operation only inside the microcomputer using the first internal bus, and an external address via the bus interface means by the first data transfer device. It enables parallel access operations in space.
[0018]
Since the data transfer on the external bus by the first data transfer device and the instruction execution using the internal bus by the data processing device such as the CPU can operate in parallel, the processing performance of the microcomputer can be improved. Data transfer on the external bus can be performed without degrading the processing performance of the data processing apparatus.
[0019]
The bus control means (12) can be constituted by an internal bus controller and an external bus controller. The external bus controller divides the address space so that bus specifications such as the type of memory, the bus width, and the number of access states can be set, and an external bus right request by a bus master such as a data processing device such as a CPU, It can be configured to arbitrate between an external bus right request by the first data transfer device and a bus right request from outside the microcomputer. Thereby, control of internal access using the first internal bus by the data processing device in parallel with external bus access by the first data transfer device, and external bus access using the first internal bus by the data processing device And the external bus access by the first data transfer device can be easily realized by individual logic, and both ease of control contents and suppression of increase in the control logic scale are simplified.
[0020]
At this time, if the address or bus command output from the first data transfer device is supplied to the bus interface means via a dedicated signal line such as a second internal bus (EXAB), the first data transfer device The state transition control operation can be simplified, and the logical scale can be reduced.
[0021]
In addition, the external bus controller arbitrates the external bus right request including the bus right request from the outside of the microcomputer together with the external bus right request by the first data transfer device built in the microcomputer. And the first data transfer apparatus can reduce the overhead when transferring the external bus right, and can further improve the processing performance.
[0022]
A storage means (6) such as a ROM for storing a program of a data processing device such as a CPU can be made selectable in an operation mode so as not to include a vector of the data processing device such as a CPU. As a result, the overall processing program can be stored in the external ROM, and the program that requires high-speed processing can be stored in the built-in ROM, thereby improving usability such as flexibility in changing the program.
[0023]
The activation factor and transfer mode of the first data transfer device can be limited to functions necessary for data transfer on the external bus. This can reduce the physical scale.
[0024]
The number of registers can be reduced by determining the transfer address in the first data transfer apparatus and using the address specifying means (40, 41) in which the initial value of the address information is specified also as the transfer count register.
[0025]
Further, by temporarily holding data read from the source address in the dual address transfer by the latch circuit (72L) such as an input / output port constituting the bus interface means (72), such data is transferred to the first data. The data bus leading to the transfer device becomes unnecessary, and the physical scale can be reduced.
[0026]
If the first data transfer device also supports single address transfer, the bus cycle required for transfer can be shortened and the processing performance can be further improved.
[0027]
The first data transfer device can have a plurality of data transfer channels. At this time, an external data transfer activation request signal can be assigned to each channel. Thereby, the usability of data transfer control in the microcomputer system is improved, and the processing performance can be improved.
[0028]
An external buffer memory can be easily used as a ring buffer by performing address updating by repeatedly storing operation results for an address designating means such as a register for storing transfer addresses. If a data processing device such as a CPU can read / write a register such as the addressing means in the first data transfer device via the third internal bus (PAB, PDB) as needed, the ring The amount of data stored on the buffer can be easily managed.
[0029]
In enabling the repetitive address update operation for use as the ring buffer, carry / borrow propagation may be prohibited by a predetermined bit when the address information of the addressing means is incremented / decremented. By prohibiting carry / borrow propagation with a predetermined bit, the function as a ring buffer can be realized with a minimum physical scale. Even if the start address and the end address of the ring buffer cannot be arbitrarily designated, there is no great inconvenience when a large-capacity memory such as an external RAM is used for the ring buffer. By making the operation repeatable, it is possible to eliminate a load such as interrupt processing for a data processing device such as a CPU.
[0030]
For temporary storage of transfer data at the time of dual address transfer, the input / output port of the bus interface means or the like can be used so that the first data transfer device itself does not directly input / output transfer data. As a result, the data input / output by the first data transfer device is not read / written by the first data transfer device itself, but is only read / written by a data processing device such as a CPU. The conflict between the access from other bus masters such as a processing device and the data transfer of the first data transfer device itself can be essentially avoided, the logical configuration can be further simplified, and the microcomputer development period can be shortened. Also contributes.
[0031]
In addition to the data processing device such as the CPU and the first data transfer device such as the DMAC, the second can support the data transfer control inside and outside the microcomputer connected to the internal bus for the conventional microcomputer. The data transfer device (3) can also be incorporated. As a result, the first data transfer device has a configuration specialized for data transfer control related to the external bus as compared with a case where a data transfer channel necessary for general-purpose DMAC is used for internal and external DMA transfer control. Therefore, even if the necessary number of data transfer channels are provided, an increase in logical scale can be minimized.
[0032]
When the bus control means also enables refresh control of a DRAM or the like, the refresh timer may perform bus right arbitration as an external bus right request source.
[0033]
By configuring the second data transfer device connected to the first internal bus and the first data transfer device as an integrated module, limited data transfer channels can be used interchangeably. be able to.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an example of a microcomputer according to the present invention. The microcomputer 1 shown in the figure is a semiconductor integrated circuit formed on one semiconductor substrate (one chip) such as single crystal silicon.
[0035]
The microcomputer 1 includes a central processing unit (CPU) 2, a DMA controller (DMAC) 3 as a second data transfer device, an external bus DMAC (EXDMAC) 4 as a first data transfer device, and a read-only memory (ROM). 5, random access memory (RAM) 6, timer 7, pulse output circuit 8, serial communication interface (SCI) 9, A / D converter (A / D) 10, interrupt controller 11, bus controller 12, clock oscillator (CPG) ) 13, functional blocks of input / output port (IOP (A)) 21 to input / output port (IOP (F)) 26 and input / output port (IOP (1)) 31 to input / output port (IOP (5)) 35 (Also referred to as a module).
[0036]
The CPU 2 is the main operation, and mainly operates by reading commands from the ROM 5. Although not shown in particular, the CPU 2 fetches an instruction, decodes the fetched instruction and generates a control signal for each part, and performs an address operation and a data operation in accordance with the control signal from the instruction control unit. And an operation execution unit for executing instructions.
[0037]
The DMAC 3 shares the buses IAB and IDB with the CPU 2 and can perform data transfer control on behalf of the CPU 2. The DMAC 3 is a circuit module that can perform data transfer control in place of the CPU 2 both inside and outside the microcomputer 1.
[0038]
The EXDMAC 4 exclusively controls data transfer on the external bus, and can perform data transfer control to the outside in parallel with the operation of the CPU 2 or DMAC 3 on the internal bus. The EXDMAC 4 can only control data transfer to the outside of the microcomputer 1. In other words, the EXDMAC 4 can control data transfer between memories provided outside the microcomputer 1 in the dual addressing mode, and data between the external memory of the microcomputer 1 and the external input / output circuit of the microcomputer 1 can be controlled. Transfer control is enabled in single addressing mode.
[0039]
The details of the EXDMAC 4 will be described later, but the outline will be described here. The CPU 2 sets data transfer control conditions for the EXDMAC 4 via the bus controller 12 and the buses PDB and PAB. The EXDMAC 4 is arbitrated exclusively with an external access request by a bus master module such as the CPU 2 or the DMAC 3 to obtain a bus right. Address signals for external data transfer control by the EXDMAC 4 can be output to the outside from the IOP (A) 21 to IOP (C) 23 via the bus EXAB. At this time, in the data transfer in the dual addressing mode by EXDEMAC4, the transfer data is not temporarily taken in the EXDMAC4, but is temporarily held in the latch circuits inside the IOPD24 and IOPE25.
[0040]
The functional blocks of the microcomputer 1 will be further described in detail. The functional blocks of the microcomputer 1 are connected to each other by an internal bus. The internal bus has a control bus (not shown) in addition to an address bus and a data bus. The control bus includes a bus right request signal, a bus acknowledge signal, a bus command, an external bus command, a ready signal, an external bus ready signal, a read signal / write signal, a bus size signal, and a system clock. IAB, PAB, and EXAB are internal address buses, and IDB and PDB are internal data buses. These buses are connected to the bus controller 12. Internal buses IAB and IDB are connected to CPU2, DMAC3, ROM5, RAM6, and bus controller 12, and internal address bus IAB is connected to IOP (A) 21 to IOP (C) 23 for external address output. The data bus IDB is connected to the IOP (D) 24 and IOP (E) 25 for external data input / output.
[0041]
The internal buses PAB and PDB are the bus controller 12, EXDMAC 4, timer 7, pulse output circuit 8, SCI 9, A / D converter 10, interrupt controller 11, IOP (A) 21 to IOP (F) 26, and IOP (1 ) 31 to IOP (5) 35.
[0042]
The internal address bus EXAB is connected to the EXDMAC 4, the bus controller 12, and the IOP (A) 21 to IOP (C) 23.
[0043]
The bus controller 12 determines an access destination and refers to an address signal in order to select an operation according to the bus specification. Accordingly, the bus controller 12 need only input upper address bits for determining the area from the address bus. Address output for external data transfer control by EXDMAC 4 is performed via an address bus EXAB.
[0044]
The bus controller 12 includes an internal bus controller 120, an external bus controller 121, a refresh timer 122, and the like. Address output to the outside of the microcomputer 1 is performed via the IOP (A) 21 to IOP (C) 23. Data input / output to the outside of the microcomputer 1 is performed via the IOP (D) 24 and the IOP (E) 25.
[0045]
The CPU 2 and the DMAC 3 can use the internal bus as an internal bus master, and the internal bus arbiter (internal bus arbitration circuit) of the bus controller 12 arbitrates the bus use request in accordance with each bus right request signal. As for external access, the external bus arbiter of the bus controller 12 (external bus access by the CPU 2 or DMAC 3, EXDMAC 4, bus right release request from the outside of the microcomputer, refresh request from the refresh timer 122, according to each bus right request signal. The external bus arbitration circuit arbitrates.
[0046]
ROM 5, RAM 6, timer 7, pulse output circuit 8, SCI 9, A / D converter 10, IOP (A) 21 to IOP (F) 26, IOP (1) 31 to IOP (5) 35, interrupt controller 11 Each of the functional blocks and EXDMAC 4 are read / written by the CPU 2 or DMAC 3 as internal bus slaves. The case where the EXDMAC 4 is accessed as a bus slave is a case where data transfer conditions and the like are set by the CPU 2 or the like.
[0047]
The interrupt controller 11 inputs interrupt signals output from the timer 7, the SCI 9, the A / D converter 10, and the input / output port, and outputs an interrupt request signal to the CPU 2 and an activation request signal to the DMAC 3. Also, a clear signal output from the DMAC 3 is input, and an interrupt clear signal is output. These interrupt signals are not shown.
[0048]
The input / output ports 21 to 26 and 31 to 36 are also used for input / output of external bus signals and input / output signals of the input / output circuit. The IOP (A) 21 to IOP (C) 23 are used as address bus outputs, the IOP (D) 24 and IOP (E) 25 are used as data bus inputs / outputs, and the IOP (F) 26 is also used as bus control signal input / output signals. Yes. The external address bus and the external data bus are connected to buses IAB, IDB, and EXAB through buffer circuits included in these input / output ports, respectively. The buses PAB and PDB are used for reading / writing the registers of the input / output ports, and are not directly related to the external bus. The bus control signal output includes an address strobe, a high / low data strobe, a read strobe, a write strobe, and a bus acknowledge signal. The bus control input signal includes a wait signal and a bus request signal. These input / output signals are not shown. The expansion of the external bus is selected by an operation mode or the like, and the functions of these input / output ports are also selected.
[0049]
IOP (1) 31 is a timer input / output, IOP (2) 32 is a pulse output, IOP (3) 33 is an SCI input / output, IOP (4) 34 is an analog input, and IOP (5) 35 is EXDMAC4 and DMAC3. This is also used for input / output of a transfer request signal and a transfer acknowledge signal. EXDMAC4, DMAC3, timer 7, SCI9, pulse output 8, input / output signals between the A / D converter 10 and IOP (1) 31 to IOP (5) 35, internal interrupt request signals, etc. are not shown.
[0050]
In addition, there are input terminals such as power terminals Vcc and Vss, analog power terminals AVcc and AVss, reset input RES, standby input STBY, interrupt input NMI, clock inputs EXTAL and XTAL, operation mode inputs MD0, MD1, and MD2.
[0051]
FIG. 2 illustrates an address map of a predetermined operation mode of the microcomputer 1. The address space is not particularly limited, but is 16 Mbytes, and an address is assigned for each byte.
[0052]
Each functional block has a unique address on the address space of the CPU 2 regardless of the bus to be connected. The I / O (data input / output means) includes the timer 7, DMAC 33, EXDMAC 4, pulse output circuit 8, SCI 9, A / D converter 10, IOP (A) 21 to IOP (F) 26, IOP in FIG. (1) 31 to IOP (5) 35 and the internal I / O registers of the interrupt controller.
[0053]
Although ROM ROM 5 is not particularly limited, it is 32 kbytes, mapped to addresses H′200000 to H′207FFF, RAM6 is mapped to 2 kbytes, mapped to addresses H′FFF700 to H′FFFEFF, and I / O is an address It is mapped to H'FFFF00 to H'FFFFFF. H ′ represents a hexadecimal number.
[0054]
Other addresses are set as an external address space. Since the CPU2 vector exists at the head of the address space, it is necessary to connect a ROM for storing the program to the outside including this part.
[0055]
A ROM for storing a program, a DRAM for data, other circuits (ASIC), and the like are connected to the external address space as needed. The external address space is divided into 8 areas 0 to 7 in units of 2 MB, each bus specification can be set, and an area selection signal can be output. Different memories can be easily connected to each area. In areas 2 to 5, an address multiplex for accessing the DRAM and a DRAM interface capable of executing the high-speed page mode can be selected. Such bus control is described in “H8S / 2655 Series Hardware Manual” published by Hitachi, Ltd. in March 1995.
[0056]
The built-in ROM 5 is easy to access at high speed with respect to the external ROM. Further, the contents of the built-in ROM 5 are not output to the outside as long as they are read by the internal CPU 2 and DMAC 3. This is because the bus controller 12 keeps the IOP (D) 24 and IOP (E) 25 for data input / output in an inoperable state for the access of the address mapped in the ROM 5.
[0057]
When the built-in ROM 5 is a mask ROM, changing the contents means changing the entire microcomputer 1 and is difficult to change. On the other hand, when the built-in ROM 5 is an electrically writable ROM such as a flash memory, the cost tends to increase undesirably because the manufacturing process becomes complicated. On the other hand, although it is difficult to access the external ROM at high speed, the change in the contents is only the change in the external ROM, and the external ROM is general-purpose, so it is often inexpensive. If the program is changed, the size of the program changes, so the CPU vector is often changed. According to the address map of FIG. 2, a program that requires high-speed processing and is unlikely to be changed, or a program whose contents are not desired to be known by a third party is stored in the built-in ROM 5, and the CPU vector. By storing the entire processing including the above in an external ROM, it is possible to improve processing performance, improve usability, reduce costs, and the like.
[0058]
Depending on the operation mode, the address of the built-in ROM 5 may be changed to area 0 so as to include the CPU vector. A microcomputer system can be configured without requiring an external ROM for storing programs.
[0059]
FIG. 3 shows the bus configuration of the microcomputer 1 in more detail. As described above, the bus controller 12 includes an internal bus controller (I-BSC) 120, an external bus controller (EX-BSC) 121, and a refresh timer 122. The I / O 70 includes the timer 7, the pulse output circuit 8, the SCI 9, the A / D converter 10, the IOP (A) 21 to IOP (F) 26, and the IOP (1) 31 to IOP (5) 35 shown in FIG. , Including an internal I / O register in each of the interrupt controllers 11. The memory 71 means the ROM 5 and the RAM 6. Functional blocks or circuit modules that are not connected to the bus, such as the CPG 13, are not shown.
[0060]
The external bus buffer circuit (BUF) 72 is an address buffer, a data buffer, or the like included in the IOP (A) 21 to IOP (F) 26 and IOP (5) 35. Each of the IOP (D) 24 to IOP (E) 25 is provided with a data bus latch circuit. This latch circuit is represented by a circuit block denoted by reference numeral 72L.
[0061]
The internal buses IDB and IAB are buses directly connected to the CPU 2 and the DMAC 3. A memory 71 is also connected to the buses IDB and IAB for high-speed access to internal memories such as the RAM 6 and the ROM 5. Access to the memory 71 is performed in one state.
[0062]
To the internal buses PAB and PDB, functional block registers represented by the I / O 70 are connected. By separating the buses IAB and IDB from the buses PAB and PDB, the load (capacitive load) of the buses IAB and IDB that are mainly used is reduced by the program read of the CPU 2, etc. The power consumption can be reduced by maintaining the state of the buses PAB and PDB. When the CPU 2 and the other internal bus master DMAC 3 access the registers of the functional blocks represented by the I / O 70 connected to the buses PAB and PDB, they pass through the buses IAB and IDB and the bus controller 12. Do. Access to the registers of the functional block represented by the I / O 70 is performed in two states.
[0063]
When the CPU 2 or DMAC 3 accesses an external memory (not shown) connected to the external buses EABUS and EDBUS, the CPU 2 or DMAC 3 performs the access via the buses IAB and IDB and the external bus buffer (BUF) 72.
[0064]
The CPU 2 and DMAC 3 use buses IAB and IDB exclusively. For this purpose, the CPU 2 and the DMAC 3 output a bus right request signal, which is judged by the arbitration circuit 120A of the internal bus controller 120 and gives the bus right to either the CPU 2 or the DMAC 3. The CPU 2 or DMAC 3 confirms that the bus right is given, outputs an address signal to the bus IAB, and outputs a bus command to a control bus (not shown). The bus command is a control code that indicates, for example, read, write, access data size (byte, word, longword) and the like.
[0065]
The internal bus controller 120 confirms the contents of the bus IAB and performs access control using the buses IAB and IDB if it is an access to the memory 71. Further, the internal bus controller 120 controls the register access of the I / O 70 via the buses PAB and PDB if it is an access to the register of the internal I / O 70.
[0066]
The external buses EDBUS and EABUS are controlled by the external bus controller 121. The external bus controller 121 also performs control such as address multiplexing when a DRAM is connected to the outside. The bus masters that can use the external bus are CPU2, DMAC3, EXDMAC4, refresh timer 122, and external bus master not shown. The arbitration circuit 121A performs arbitration of the bus right for them. The internal bus masters such as the CPU 2 and the DMAC 3 once arbitrate the bus right by the internal bus controller 120, and when the bus right is given, the internal bus controller 120 transfers the external bus right by the external bus right request signal EXBREQ1. Request to 121. In other words, as long as the internal bus masters CPU2 and DMAC3 use the internal bus, an external bus right request for external access does not occur from the internal bus master. Therefore, the external bus controller 121 can perform refresh or external bus transfer by the refresh timer 122 or EXDMAC 4 or external bus transfer in parallel with the internal bus masters CPU2 and DMAC3 even when the internal bus is being used by the internal bus masters CPU2 and DMAC3. External bus authority release requests can be processed in parallel. The external bus controller 121 returns the external bus right acknowledge signal EXBACK1 to the internal bus controller 120 when giving the bus right to the bus right request by the bus right request signal EXBREQ1.
[0067]
The refresh timer 122 generates a refresh request to the external bus controller 121 by a refresh request signal RFREQ at regular intervals. This refresh request is also made an external bus request. When the refresh timer 122 acquires the external bus right, the external bus controller 121 performs CAS before RAS refresh as DRAM refresh.
[0068]
Further, when an external bus right request is given to the external bus controller 121 by the external bus right request signal EXBREQ3 from the outside of the microcomputer 1, when the bus right is given to this, the external bus controller 121 makes the IOP (A) The external address output, the external data input / output, and the external access control signal input / output of 21 to IOP (F) 26 are set in a high impedance state to enable the use of the external bus by an external bus master, and the external bus right acknowledge signal EXBACK3 Is activated, and this is notified to the external bus requester.
[0069]
The EXDMAC 4 is connected to the buses PAB and PDB, and is read / written from an internal bus master such as the CPU 2 or the DMAC 4 for initial setting of transfer control conditions. The EXDMAC 4 starts the DMA transfer control operation in response to a DMA transfer request signal EXDREQi (i = 0 to 3) given from the outside. When there is a DMA transfer request in this way, the EXDMAC 4 requests an external bus right from the external bus controller 121 by an external bus right request signal EXBREQ2, outputs an external bus command, and further passes through the address bus EXAB. Issue external access address signal. When the external bus controller 121 grants the bus right for the external bus request, the bus controller 121 asserts the external bus acknowledge signal EXBACK2 to the EXDMAC4. As a result, the EXDMAC 4 starts external bus access.
[0070]
The external bus buffers of IOP (D) 24 to IOP (E) 25 include the latch circuit 72L, and temporarily hold transfer data according to an instruction from the external bus controller 121 during the EXDMAC4 dual address transfer control. Further, at the time of single address transfer, a data acknowledge signal EXDACKi indicating the start of data transfer is output to an input / output circuit which is a data transfer destination or data transfer source.
[0071]
The method for dividing the functional block is not particularly limited. For example, the EXDMAC 4, the external bus controller, and the roller 121 may be integrated.
[0072]
FIG. 4 shows an example of an address decoding circuit included in the internal bus controller 120. The address decoding circuit 120D decodes an address signal output from the CPU 2 or DMAC 3 to the internal bus IAB, and performs address determination on the ROM 5, RAM 6, I / O, and external space. The signal MSROM is a module select signal of the ROM 5, MSRAM is a module select signal of the RAM 6, MSIO is a select signal of the I / O module, and EXTA is a module select signal of the external space of the microcomputer 1.
[0073]
As described above, the ROM 5 can be arranged in either the area 0 or the area 1 shown in FIG. 2 depending on the operation mode of the microcomputer 1. By setting the signal ROME to “0” by specifying the operation mode or the internal I / O register, the ROM 5 can be not used.
[0074]
When I / O is selected (MSIO = 1), bus access using the buses PAB and PDB is activated, and when the outside is selected (EXTA = 1), the signal is sent to the external bus controller 121 to the external bus. It is supplied as the right request signal EXBREQ1.
[0075]
FIG. 5 illustrates an EXDMAC4 register configuration. The EXDMAC 4 has, for example, four channels, and is activated by a corresponding external request EXDREQi (i = 0 to 3), and performs single address transfer and dual address transfer. FIG. 5 illustrates a register configuration for one channel.
[0076]
The EXDMAC4 register includes a 24-bit source address register (SAR) 40, a destination address register (DAR) 41, and a 16-bit mode register (DTMR) 42. The SAR 40 and DAR 41 are 24 bits long, and can specify the entire 16 Mbyte address space. EXDMAC 4 does not have a so-called transfer count register. Also used for SAR40 or DAR41. That is, the values of SAR 40 and DAR 41 are incremented or decremented as the data transfer control proceeds.
[0077]
The function of each bit of the DTMR 42 is as follows. Bit 15 is an EDTE bit and permits the EXDMAC 4 operation of the channel. If there is a transfer request by EXDREQi with the EDTE bit set to “1”, data transfer of the channel is performed.
[0078]
Bit 14 is a DRQS bit and defines the active state of the EXDREQi signal. The DRQS bit selects the input. When cleared to “0”, low level sensing is selected, and when set to “1”, falling edge sensing is selected.
[0079]
Bit 13 is an EDE flag, which is set to “1” when a predetermined number of data transfers are completed by the transfer channel.
[0080]
Bit 12 is an EDIE bit, and is a bit for determining whether or not to permit an interrupt. When both the EDIE bit and the EDE flag are set to “1”, the CPU 2 is requested to interrupt. If the EDE flag is set to “1” while the EDIE bit is set to “1”, the EDTE bit is cleared to “0” at the same time, the operation of the channel is interrupted, and the CPU 2 waits for processing.
[0081]
The EXDMAC 4 can use the memory to be transferred as a ring buffer. That is, when a ring buffer is used, the transfer destination or transfer source address is automatically restored to the initial value (bits below a predetermined bit are cleared to “0”). unnecessary. If the EDIE bit is cleared to “0”, the memory can be used as a ring buffer. Bits 10 to 8 are RPB2 to RPB0 bits, and specify the size of the ring buffer, that is, the unit to be repeated. The units to be repeated are 64 kB (RPB2 to RPB0 = B′000), 128 kB (RPB2 to RPB0 = B′001), 256 kB (RPB2 to RPB0 = B′010), 512 kB (RPB2 to RPB0 = B′011), 1 MB (RPB2 to RPB0 = B′100) and 2 MB (RPB2 to RPB0 = B′101). When the SAR40 and DAR41 values are incremented and updated by the address calculator as the data transfer control proceeds, the RPB2 to RPB0 bits are sent to the SAR40 and DAR41 bits 15, 16 according to the values. , 17, 18, 19, and 20 are prohibited from transmitting carry / borrow. When the carry / borrow transmission is prohibited, the bits lower than the prohibited bit are set to 0 at that time, so that the address is automatically returned to the initial value. Thereby, the EXDMAC 4 can control the data transfer address so as to automatically configure a ring buffer.
[0082]
Bits 7 and 6 are SM1 and SM0 bits, which specify whether the SAR 40 is incremented, decremented, or fixed after data transfer. When the SM1 bit is cleared to “0”, the SAR 40 is fixed. If the SM0 bit is cleared to “0” with the SM1 bit set to “1”, the increment is performed. If the SM0 bit is set to “1”, the decrement is performed.
[0083]
Bits 5 and 4 are DM1 and DM0 bits, which specify whether the DAR 41 is incremented, decremented, or fixed after data transfer. When the DM1 bit is cleared to “0”, the DAR 41 is fixed. When the DM0 bit is cleared to “0” while the DM1 bit is set to “1”, the increment is performed. When the DM0 bit is set to “1”, the decrement is performed.
[0084]
Bits 3 and 2 are MD1 and MD0 bits, and select a data transfer mode. When the MD1 bit is cleared to “0”, the dual address mode is set. In the dual address mode, data is transferred once from the address indicated by the SAR 40 to the address indicated by the DAR 41 by one activation. Thereafter, the operations of the SAR 40 and the DAR 41 are performed based on the designation of the SM1, SM0, DM1, and DM0 bits.
[0085]
When the MD0 bit is cleared to “0”, the SAR 40 also functions as a transfer count function. When a carry occurs from a predetermined bit of the SAR 40, it is determined that a predetermined number of transfers have been completed, and the transfer end flag EDE is set to "1".
[0086]
When the MD0 bit is set to “1”, the DAR also functions as a transfer count function.
[0087]
When the MD1 bit is set to “1”, the single address address mode is set. In the single address address mode, either the transfer source or the transfer destination is designated by the acknowledge signal EXDACKi.
[0088]
When the MD0 bit is cleared to “0”, the transfer destination is specified by the acknowledge signal EXDACKi, the SAR 40 specifies the transfer source address, and also functions as a transfer count function.
[0089]
When the MD0 bit is set to “1”, the transfer source is specified by the acknowledge signal EXDACKi, the SAR 40 specifies the transfer destination address, and also functions as the transfer count function.
[0090]
In either case, when a carry / borrow is generated from a predetermined bit specified by the RPB2 to RPB0 bits of the SAR 40 or the DAR 41, it is determined that the transfer has been completed a predetermined number of times, and the transfer end flag EDE is set to “1”.
[0091]
Bit 0 is an SZ bit, and selects whether one data transfer is performed in byte size or word size. When the SZ bit is cleared to "0", byte size data transfer is performed, and when the SZ bit is set to "1", word size data transfer is performed. The word size is 2 bytes.
[0092]
FIG. 6 shows a block diagram of EXDMAC4. The EXDMAC 4 receives an activation request signal EXDREQi (i = 0 to 3) from the outside. The EXDMAC 4 generates an external bus right request EXBREQ2, generates an external bus command, and outputs an address to the external bus controller 121, and inputs an external bus right acknowledge signal EXBACK2 and an external bus ready signal EXBRDY from the external bus controller 121. Works. EXDACKi used at the time of single address transfer is indicated by an external bus command. The negated state of the external bus ready signal EXBRDY can be grasped as a wait state insertion request from the external bus controller 121 to the EXDMAC 4. EXBRDY from the external bus controller 121 to the internal bus controller 120 can also be grasped as a wait insertion request.
[0093]
Further, as a bus interface inside the microcomputer 1, a module select signal, a read signal, and a write signal are input from the internal bus controller 120 to read / write the CPU 2 and DMAC 3, and are connected to the address bus PAB and the data bus PDB. Is done.
[0094]
When the normal DMAC 3 is in the dual address mode, the read data is temporarily stored in the DMAC 3 and written. On the other hand, the EXDMAC 4 substitutes this function for an input / output port, and the latch circuit 72L of the IOP (D) 24 and IOP (E) 25 has a temporary data holding function. As the operation of the microcomputer becomes faster, a pipeline operation becomes necessary. The DMAC 3 itself has a read / write operation for data transfer with the bus right and the setting of data transfer control conditions by the CPU 2 for the DMAC 3. When the read / write operation for the DMAC3 is continuous, it becomes difficult for the DMAC 3 to transition between the operation as the bus master and the operation as the bus slave, the operation cannot be completed within a predetermined state, or an inconvenient operation occurs. The potential increases. On the other hand, EXDMAC 4 can essentially avoid the inconvenience, and can reduce the logical scale and the design period. Even during the data transfer control by the EXDMAC 4, the CPU 2 can perform an access operation using the internal bus, so that the CPU 2 can read the register inside the EXDMAC 4 at an arbitrary timing. Therefore, the state of the EXDMAC 4 from the CPU 2 can be easily monitored.
[0095]
The EXDMAC 4 is intended to perform data transfer independent of the CPU 2, but at this time, in the dual addressing mode or the like, it is necessary to provide a dedicated data bus in order to temporarily hold the read data in the own module. It will occur. In EXDMAC4, such a dedicated data bus is not required, and the physical scale can be reduced in this respect as well.
[0096]
According to FIG. 6, EXDMAC 4 is composed of the following circuit blocks. The EXDMAC 4 includes registers for the DTMR 42, DAR 41, and SAR 40 for each of four channels, and includes a common control circuit 45, data buffer (DB) 44, address buffer (AB) 46, and arithmetic operation circuit (AU) 43 for each channel. Have. These blocks are connected by two internal buses, A bus and B bus.
[0097]
The control circuit 45 detects the activation request signal EXDREQi (i = 0 to 3) and starts its operation, outputs an external bus right request EXBREQ2, an external bus command and an address, an external bus right acknowledge EXBACK2, and an external bus ready signal. The external bus is operated while inputting EXBRDY. On the other hand, input / output of the internal register is performed in accordance with the module select signal, read signal, write signal, address lower bits on the address bus PAB, and the value of the data bus PDB.
[0098]
The address buffer 46 has a 24-bit configuration corresponding to the external address space of 16 Mbytes, receives data from the A bus, holds an address to be read / written, and outputs it to EXAB.
[0099]
The data buffer 44 has a 16-bit configuration, is connected to the data bus PDB, and inputs / outputs data when the CPU 2 reads / writes a register in the EXDMAC 4. Since the SAR 40 and the DAR 41 have a 24-bit configuration, they are accessed twice from the CPU 2, but at this time, only one read / write is performed in the EXDMAC 4 so that an inconvenient operation is not performed.
[0100]
The functions of the DTMR 42, DAR 41, and SAR 40 registers are as described above. Data is input from the B bus and output to the A bus. The arithmetic operation circuit (AU) 43 performs increment / decrement processing. The input is A bus and the result is output to B bus.
[0101]
FIG. 7 shows a state transition diagram of EXDMAC4. The EXDMAC 4 has three states: state I (idle state), state S (source transfer state), and state D (destination transfer state).
[0102]
After reset, the state transitions to state I. In state I, the activation request signal EXDREQi (i = 0 to 3) of EXDMAC 4 is sampled. When the EDTE bit of any channel is set to 1, the EXDREQi input of that channel is detected. When a plurality of channels are activated, the channel 0 is preferentially operated.
[0103]
When EXDREQi is enabled, the transition is made to state S. In state S, the contents of the SAR 40 of the channel are output to EXAB, the contents of the SAR 40 are updated according to the SM1 and SM0 bits, and the external bus request EXBREQ2 and the bus command are output to the external bus controller 121.
[0104]
The external bus controller 121 arbitrates the external bus request, activates the acknowledge signal EXACK2 at a predetermined timing, and activates the external bus in order to give the EXDMAC 4 an external bus right. When the external bus is terminated, the external bus ready signal EXBRDY is activated. Thereby, the EXDMAC 4 can end the bus cycle.
[0105]
In the single address mode, the EXDMAC 4 ends the operation and transitions to the state I when it detects the external bus ready EXBRDY while the bus acknowledge signal EXBACK2 is active.
[0106]
In the dual address mode, when the acknowledge signal is active and external bus ready is detected, the state transitions to state D. In the state D, the contents of the DAR 41 of the channel are output to the address bus EXAB, the contents of the DAR 41 are updated according to the SM1 and SM0 bits, and the external bus request EXBREQi and the bus command are output to the external bus controller 121.
[0107]
The external bus controller 121 activates the external bus. When the external bus is terminated, the external bus ready signal EXBRDY is activated. When the EXACKC4 detects the external bus ready EXBRDY while the bus acknowledge signal EXBACK2 is active, the EXDMAC4 ends the access cycle and transitions to the state I.
[0108]
In the case of the single address mode, the transfer acknowledge signal EXDACKi is instructed to be activated in the state S bus command. In the dual address mode, in the state S bus command, an instruction not to transfer the bus right after the read and an instruction to temporarily hold the read data in the latch circuits of the IOP (D) 24 and IOP (E) 25 give.
[0109]
A dedicated external address bus EXAB is used, and it is not necessary to determine whether or not to acquire the bus right, and after confirming this, it is not necessary to output a bus command and address. Scale can be controlled.
[0110]
FIG. 8 shows an example of a microcomputer system using the microcomputer for printer control.
[0111]
The printer control system includes a microcomputer 1, a receiving circuit 100 such as a Centronics interface, a universal serial bus (USB) or an option, a buffer RAM 101 composed of DRAM, a character generation ROM (CGROM) 102, a program ROM 103, and a print control circuit 104. These are connected via the external bus 105 of the microcomputer 1.
[0112]
The program ROM 103 is assigned to area 0, the buffer RAM 101 is assigned to area 2, the CGROM 102 is assigned to area 6, and the receiving circuit 100 and the print control circuit 104 are assigned to area 7. As the buffer RAM 101, a DRAM that requires a refresh operation as a readable / writable memory but is known to be inexpensive is used. In FIG. 8, the address arrangement of the buffer RAM 101 is shown. According to this example, the buffer RAM 101 has a storage capacity of 2 MB (16 Mbits), 1 Mbyte of which is used as the work area of the CPU 2 and the remaining 512 kB is used as a ring buffer.
[0113]
The system shown in FIG. 8 further includes a print head 106, a buffer circuit 107, a line feed motor 108, and a carriage return motor 109. These motors 108 and 109 respectively output the timer 7 and the pulse output of the microcomputer 1. It is controlled by the output of the device 8. The line feed motor 108 and the carriage return motor 109 are stepping motors although not particularly limited.
[0114]
Although not shown, the SCI 9 of the microcomputer 1 is used for communication with a host device or the like, and the A / D converter 10 inputs sensor information such as the number of sheets.
[0115]
The EXDMAC 4 receives data by a plurality of receiving circuits 100 such as a Centronics interface and a universal serial bus in parallel with the operation of the CPU 2. The microcomputer 1 receives the transfer request signal EXDREQi and can perform single address transfer by the transfer acknowledge signal EXDACKi. For example, input strobe signal of Centronics interface is input to EXDREQ0, dual address transfer is performed on channel 0, reception signal of option interface is input to EXREQ1, EXDACK1 output is given to option interface, and single address transfer is performed on channel 1 I do.
[0116]
The internal DMAC 3 outputs print data and pulse data to drive the line feed motor 108 and the carriage return motor 109. Also, transmission data and reception data of SCI 9 are transferred. Such a method of using DMAC 3 is described in Japanese Patent Laid-Open No. 5-307516.
[0117]
Note that, by improving the integration degree of the semiconductor integrated circuit, a part of the receiving circuit 100 other than the option, the print control circuit 104, and the like can be integrated in a one-chip microcomputer. Further, a general-purpose memory such as the buffer RAM 101 can be integrated in a one-chip microcomputer. As for the program ROM 103, the CGROM 102, and the like, it is more convenient to use an individual semiconductor integrated circuit such as an individual printer model that is changed for each microcomputer system. Regardless of which part is mounted on a one-chip microcomputer, the logical configuration of the bus need not be changed as described above.
[0118]
FIG. 9 shows an example of bus operation timing of the microcomputer system of FIG.
[0119]
Most of the internal buses IAB and IDB perform program read from the ROM 5 of the CPU 2 and data read / write to the RAM 6 in one state. Among these, the CPU 2 reads the internal I / O register (for example, A / D converter) using the P buses PAB and PDB from T3, and reads the external memory (for example, CGROM) from T12. Since the circuit connected to the P buses PAB and PDB has a slower access speed than the RAM 6 and the ROM 5, the bus ready signal BRDY is supplied by the bus controller 120.
[0120]
The DMAC 3 performs the transfer from the memory to the internal I / O register (for example, the RAM 6 to the pulse output circuit 8) from T7.
[0121]
On the other hand, in EXDMAC4, channel 0 is dual address transfer, channel 1 is single address transfer, channel 0 is activated at T0, and channel 1 is activated at T7 and T14. Note that the activation request signal EXDREQi (i = 0 to 3) is displayed in an overlapping manner. For example, a portion described as ch0 indicates that EXDREQ0 is activated.
[0122]
At T0, EXDMAC4 transitions to state S in response to EXDREQ0 becoming active, generates an external bus right request and an external bus command, and outputs EXAB. The external bus command instructs read, bus right transfer prohibition after read, latch of read data, and the like. The external bus controller 121 arbitrates the external bus right, immediately gives the external bus right to the EXDMAC 4 by EXBACK2, and starts the external bus. The external bus controller 121 once deactivates the bus ready signal EXBRDY and causes the EXDMAC 4 to insert a wait cycle.
[0123]
When the bus ready signal EXBRDY output from the external bus controller 121 is returned to the active state, the EXDMAC 4 finishes its memory cycle, transitions to the state D, generates the next external bus right request and external bus command, and The address is output to EXAB. The external bus command instructs writing, outputting latched data, and the like. The external bus controller 121 activates the external bus. Similarly to the above, the external bus controller 121 once deactivates EXBRDY to insert a wait cycle into EXDMAC4.
[0124]
When EXBRDY becomes active, EXDMAC4 finishes its memory cycle, transitions to state I, and returns to the standby state.
[0125]
In response to EXDREQ1 becoming active at T7, EXDMAC4 transitions to state S, generates an external bus request and an external bus command, and outputs EXAB. The external bus command instructs the external bus controller 121 to read and output EXDACK1. The external bus controller 121 arbitrates the external bus right, immediately gives the external bus right to the EXDMAC 4 by EXBACK2, and starts the external bus. Similarly to the above, EXBRDY is once deactivated, and a wait cycle is inserted into EXDMAC4. The external bus controller 121 determines access to the DRAM area and performs access in four states including precharge, RAS, and CAS cycles. When EXBRDY becomes active, EXDMAC 4 transitions to state I and returns to the standby state.
[0126]
Further, in response to EXDREQ1 becoming active at T14, EXDMAC4 transitions to state S, generates an external bus right request and an external bus command, and outputs EXAB. The external bus command instructs reading and output of EXDACK1. At this time, the external bus controller 121 arbitrates the external bus right, but since the external read is being executed by the CPU 2, the external bus right is not given to the EXDMAC 4 and the external read by the CPU 2 is awaited. At T17, an external bus right is given to EXDMAC 4 to activate the external bus. As described above, the bus controller 121 once deactivates the bus ready signal EXBRDY and requests EXDMAC4 to insert a wait cycle. When EXBRDY becomes active, EXDMAC 4 transitions to state I and returns to the standby state.
[0127]
In DTMR1, it is assumed that DTIE = 0, RPB2-0 = B′011, SM1, 0 = B′10 and repeat operation of 512 kB unit is set, and when SAR is incremented at T9, from H′5FFFFF It is updated to H'580000 and the operation is continued. That is, a ring buffer on the buffer RAM 101 of H'580000 to H'5FFFFF is configured. The CPU 2 can obtain the input pointer of the ring buffer by reading the SAR 40. While referring to the input pointer, it is easy to read the ring buffer so that the amount of data stored in the ring buffer is appropriate.
[0128]
Further, since the EXDMAC 4 continues to operate without stopping, the startup request signal is not undesirably detected or cannot be detected at the time of restart.
[0129]
When the CPU 2 requests reading / writing using an external bus and external bus transfer by EXDMAC 4 at the same time, either the CPU 2 or EXDMAC 4 is temporarily stopped, but the data access frequency of the CPU 2 is low, and the CPU 2 is continuously Since the EXDMAC 4 does not continuously transfer data, the CPU 2 and the EXDMAC 4 can be prevented from being stopped for a long time. At least the CPU 2 can execute the program on the ROM 5 and the external bus transfer by the EXDMAC 4 can be performed in parallel. In other words, external bus transfer can be performed without degrading the processing performance of the CPU 2. Further, external data transfer by EXDMAC4 can be performed in parallel with transfer by DMAC3 by the internal bus.
[0130]
It is possible to transfer the bus right between the CPU 2 and the DMAC 3 without overhead by synchronizing an internal bus right request or an internal bus right acknowledge signal with a clock or a bus ready signal. Similarly, transfer of the bus right between the external access of the CPU 2 or the DMAC 3 and the EXDMAC 4 can be performed without overhead.
[0131]
FIG. 10 shows a block diagram of an external bus DMAC 4A having the functions of both the general-purpose DMAC 3 and EXDMAC 4.
[0132]
The data transfer channels are 0 to 7, and each has DTMR 42, SAR 40, DAR 41, and two sets of transfer counters TCR 47A and BTCR 47B as control registers. A shifter 47C is added to the arithmetic operator 43A, and there are three types of internal buses: A bus, B bus, and C bus.
[0133]
In the example of FIG. 10, as in FIG. 6, in addition to the interface to the external bus controller 121, the interface to the CPU 2, etc., as an interface to the internal bus controller 120, an internal bus right request signal, an internal bus command, an IAB output, Internal bus right acknowledge, internal bus ready input, and IDB input / output are added.
[0134]
When the EDTE bit of DTMR42 is set to “1”, an external bus right request or an external bus command is output to the external bus controller 121, and a transfer on the external bus is executed on the internal bus of the CPU 2 Can be done in parallel.
[0135]
On the other hand, when the IDTE bit (not shown) of the DTMR 42 is set to “1”, an internal bus request or an internal bus command is output to the internal bus controller 120 and the internal bus (I bus) is used. Thus, transfer between arbitrary addresses can be performed exclusively with the operation of the CPU 2.
[0136]
According to the configuration of FIG. 10, limited channels such as 8 channels can be used interchangeably. The external bus transfer as the external bus DMAC 4A can be 2 channels, and the transfer using the internal bus can be 6 channels. In addition, logic such as an arithmetic operator and a bus interface can be used in common. When a plurality of activation requests are generated, it is preferable to increase the priority of external bus transfer so that parallel operation with the CPU 2 is enabled.
[0137]
Furthermore, external bus transfer control circuit and internal bus transfer control circuit are provided separately. If each arithmetic operation unit and bus are provided separately, external bus transfer and internal bus transfer can be operated in parallel. become.
[0138]
If the single address mode is selected, external bus transfer is selected, and if the dual address mode is selected, transfer is performed using the internal bus. Can be saved.
[0139]
According to the embodiment described above, the following operational effects are obtained.
[0140]
[1] The control of the internal bus of the microcomputer 1 and the control of the external bus are made independent, and the operation of the CPU 2 using the internal bus and the data transfer performed using the external bus by the EXDMAC 4 are performed independently. The processing performance of the computer 1 can be improved.
[0141]
[2] The external bus controller 121 can divide the address space and set bus specifications such as memory type, bus width, number of access states, etc., and external bus access by the CPU 2 and other internal bus master DMAC3 and external access by EXDMAC4 Are collectively controlled by the external bus controller 121, the EXDMAC 4 that does not use the internal bus can also be accessed by the external bus similar to the CPU 2 and DMAC 3, and the increase in logical scale can be reduced.
[0142]
[3] By making the address, bus command, etc. output from the external bus controller 121 a dedicated signal transmitted via the bus EXAB, the operation of the control signal, state transition, etc. of the external bus DMAC is simplified. The scale can be reduced.
[0143]
[4] The external bus controller 121 arbitrates between the external bus access by the CPU 2 and the DMAC 3 and the EXDMAC 4 or other external bus right request, thereby allowing the external bus right between the external bus access by the CPU 2 and the DMAC 3 and the EXDMAC 4. The overhead at the time of transfer can be eliminated, and the processing performance can be further improved.
[0144]
[5] A program that requires high-speed processing in an external ROM by making the internal ROM 5 for storing a program of the CPU 2 selectable in an operation mode or the like so as not to include a vector of the CPU 2 And the like can be stored in the built-in ROM 5, and the usability such as the flexibility to change the program can be improved.
[0145]
[6] The EXDMAC 4 has a plurality of channels, and each channel has an independent external transfer request input, so that the usability can be improved and the processing performance can be improved. By supporting single address transfer, the bus cycle required for transfer can be reduced and the processing performance can be further improved.
[0146]
[7] The EXDMAC 4 can reduce the logical scale by providing a function suitable for external bus transfer, such as the receiving circuit 100 to the buffer RAM 101. The transfer counter is also used as an address counter to reduce the number of registers, temporarily hold transfer data, etc. by using the latch circuit 72L such as an input / output port, thereby eliminating the need for a data bus to the EXDMAC4. Can be scaled down. Further, it is possible to essentially avoid the conflicting operation between the access from the CPU 2 and the DMAC 3 and the data transfer of the EXDMAC 4 itself, further simplifying the logical configuration, and shortening the development period.
[0147]
[8] Higher bits are fixed from predetermined bits of the transfer source / destination address registers 40 and 41 to enable repetitive operation, and a ring buffer can be easily configured on the buffer RAM 101 without load of the CPU 2 it can. Even if the start address and the end address of the buffer cannot be arbitrarily designated, there is no great inconvenience in a large-capacity memory such as the buffer RAM 101. Since the CPU 2 can read / write the contents of the EXDMAC 4 at any time, the management of the amount of data stored in the ring buffer can be facilitated. By making the operation repeatable, it is possible to eliminate a load such as the interrupt processing of the CPU 2.
[0148]
[9] The processing performance of the microcomputer 1 can be improved by independently performing the transfer on the internal bus by the DMAC 3 connected to the internal bus and the data transfer performed by using the external bus by the EXDMAC 4. In a microcomputer system such as a printer, the transfer on the internal bus by the DMAC 3 for driving the motor and the transfer using the external bus such as the transfer to the buffer RAM 101 of the receiving circuit 100 can be performed simultaneously. The processing performance of the microcomputer system can be improved.
[0149]
[10] By realizing the microcomputer 1 and the receiving circuit 100 as the same semiconductor integrated circuit, the size of the system can be reduced.
[0150]
[11] By incorporating the DMAC 3 connected to the internal bus and the external bus controller 121 having only a function suitable for external bus transfer, the increase in the logical scale is minimized while the overall number of channels is increased. Can be. Further, the DMAC 3 connected to the internal bus has a general-purpose function, so that the usability is not lowered.
[0151]
[12] By configuring the DMAC 3 connected to the internal bus and the EXDMAC 4 as an integrated module, limited channels can be used interchangeably. In addition, logic such as a bus interface can be used in common.
[0152]
The invention made by the inventors as described above is not limited to the description of the above embodiment, and various modifications can be made without departing from the scope of the invention.
[0153]
For example, the number of bits in the address registers of the DMACs 3 and 4 is not limited to 24 bits. The number of address bits can be changed according to the address space of the CPU or semiconductor integrated circuit device. For example, if the address space is 4 Gbytes, it may be 32 bits.
[0154]
Various transfer modes and the like in the first data transfer apparatus can be changed. The capacity of the ring buffer can also be changed. You may have another register that specifies the capacity of the ring buffer. Alternatively, the transfer counter may be independent. It is possible to limit the number of address registers to only one in the single address mode.
[0155]
The configuration of the microcomputer is not limited. It is also possible to incorporate other functional blocks. In addition to the DMAC, another data transfer device such as a data transfer controller connected to the internal bus may be incorporated. The data transfer controller is described in “H8S / 2655 Series Hardware Manual” published by Hitachi, Ltd. in March 1995.
[0156]
Various changes can also be made to specific circuit configurations such as EXDMAC, bus controller, and internal bus configurations. An internal bus such as IAB or IDB and an internal bus such as PAB or PDB can be configured integrally.
[0157]
The microcomputer system is not limited to a printer. For example, it can be used in a digital communication system. Transfer from the receiver circuit to the buffer RAM, perform demodulation, error correction, etc., further modulate, store in another buffer RAM, and transfer from the buffer RAM to the transmitter circuit, etc. Transfer from the receiver circuit to the buffer RAM Further, EXDMAC is used for transfer from the buffer RAM to the transmission circuit, and external data transfer control can be performed in parallel with the processing of other processors such as a CPU, thereby improving the processing performance.
[0158]
In the above description, the case where the invention made mainly by the present inventor is applied to a ROM built-in microcomputer, which is the field of use behind it, is not limited to this, but a microcomputer without a built-in ROM, The present invention can also be applied to a microcomputer centering on a digital signal processor (DSP), and the present invention can be applied at least to a condition in which a data processing device and a data transfer device are incorporated.
[0159]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0160]
That is, by configuring the bus and the bus controller so that the data transfer on the external bus by the first data transfer device and the instruction execution using the internal bus by the CPU can be operated in parallel, the processing of the microcomputer Improves performance, improves usability, and minimizes logical and physical scale.
[0161]
The total performance of data processing by a microcomputer incorporating a data transfer device such as DMAC can be improved.
[0162]
The microcomputer system to which the microcomputer is applied is capable of parallel processing of data transfer control between the outside and arithmetic processing inside the microcomputer, and has a small processing overhead and an increase in physical scale. Can be minimal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a microcomputer according to the present invention.
FIG. 2 is an explanatory diagram showing an example of an address map in the microcomputer of FIG. 1;
FIG. 3 is a block diagram showing the microcomputer of FIG.
FIG. 4 is a block diagram showing an example of an address decoder included in the bus controller.
FIG. 5 is a block diagram showing an example of a register configuration of an external bus DMAC.
FIG. 6 is a block diagram showing the entire external bus DMAC.
FIG. 7 is a state transition diagram of an external bus DMAC.
8 is a block diagram showing an example of a system to which the microcomputer of FIG. 1 is applied.
FIG. 9 is a timing chart showing an example of operation timing of the microcomputer.
FIG. 10 is a block diagram showing another example of the external bus DMAC.
[Explanation of symbols]
1 Microcomputer
2 Central processing unit
3 DMAC
4 EXDMAC
5 ROM
6 RAM
IDB, PDB internal data bus
IAB, PAB, EXAB Internal address bus
12 Bus controller
120 Internal bus controller
121 External bus controller
122 Refresh timer
21-26 IO port
31-35 IO port
40 Source Address Register (SAR)
41 Destination Address Register (DAR)
42 Data transfer mode register (DTMR)
43 Arithmetic Unit (AU)
44 Data buffer (DB)
45 Control circuit
46 Address buffer (AB)
100 Receiver circuit
101 Buffer RAM
102 CGROM
103 Program ROM

Claims (17)

A storage means; a data processing apparatus that can access the storage means via a first internal bus and that executes instructions; a first data transfer apparatus that performs data transfer control; and the first internal bus or the a bus interface unit which can be connected to a first data transfer device to the external bus, Ri comprises a bus control unit for arbitrating bus control and bus, to one semiconductor chip,
Said bus control means that enables parallel access operation of the external address space via said bus interface means to the access operation of the microcomputer internal only by the first data transfer device using said first internal bus a microcomputers,
The bus control means includes an internal bus controller that arbitrates a bus right request by a bus master means that shares the first bus, and an external bus controller that arbitrates a bus right request to access the external bus,
The external bus controller requests the external bus right from the internal bus controller when the bus master means requesting external access acquires the bus right from the internal bus controller, and from the first data transfer device. A microcomputer capable of arbitrating between an external bus right request and a bus right request given from the outside of the microcomputer . The first data transfer device has a plurality of data transfer channels each capable of direct memory access control, and inputs an external data transfer start request signal for each data transfer channel. claim 1 Symbol placement microcomputer to. The first data transfer device has address specifying means for specifying an initial value of address information, address buffer means, and arithmetic operation means,
The address information output by the addressing means is supplied to the address buffer means and arithmetic operation means via a bus,
The address information supplied to the address buffer means can be supplied to the bus interface means,
The arithmetic operation means performs an arithmetic operation on the condition that a value of a higher bit than a predetermined bit position of the address information is fixed with respect to the input address information, and supplies the operation result to the address designating means. The microcomputer according to claim 1 or 2, wherein The storage means is a ROM for storing an operation program of the data processing device, and can be selected to be arranged in an address area including the vector of the data processing device or in an address area not including the vector. The microcomputer according to any one of claims 1 to 3 . The first data transfer device is coupled to said bus interface means via the second bus, coupled to said internal bus controller via a third bus,
First data transfer device, the third data transfer condition over the bus is set, according to claim 1, wherein a and outputs an address signal to be used for external access to the second bus Microcomputer. The bus interface means includes data latch means, and the external bus controller reads a source address in a dual addressing mode of the first data transfer device when the bus right is given to the first data transfer device. 6. The microcomputer according to claim 5 , wherein data is latched by said data latch means, and the latched data is controlled to be written to a destination address. A second data transfer device is further provided as the bus master means for sharing the first bus, and the second data transfer device is capable of direct memory access control when a data transfer control condition is set by the data processing device. 2. The microcomputer according to claim 1 , wherein the microcomputer is configured as follows. The data processing device and the second data transfer device each output a bus right request signal to the internal bus controller, and the internal bus controller arbitrates the bus right request by the bus right request signal, and the arbitration result is sent to the bus right. 8. The microcomputer according to claim 7 , wherein the microcomputer is provided to the data processing device and the second data transfer device by an acknowledge signal. The internal bus controller, said bus right acknowledge signal the data processor or the second data transfer device has acquired the bus by to access the external address space, the external bus controller through an external bus request signal Notify
When the external bus controller approves the external bus right request from the internal bus controller, the external bus controller notifies the internal bus controller of the bus right approval by an external bus right acknowledge signal, and the data processing device that has approved the bus right or the second 9. The microcomputer according to claim 8 , wherein the data transfer device enables an external address space to be accessed via the bus interface means and the first bus. The bus control means further includes a refresh timer, and the external bus controller arbitrates the refresh request output from the refresh timer with other external bus requests, and when the refresh request is approved, the bus interface means performs a refresh operation. 10. The microcomputer according to claim 9 , wherein the microcomputer outputs an instruction signal. The external bus controller inputs a bus right release request signal from outside the microcomputer, arbitrates the request with the external bus right request and the refresh request, and approves the bus right release request to the outside. 11. The microcomputer according to claim 10 , wherein the microcomputer outputs a signal to the outside and controls the bus interface means to a high impedance state. Storage means, a data processing apparatus that can access the storage means via the first internal bus and executes instructions, and data that is connected to the first internal bus and the second internal bus and performs data transfer control One transfer device, bus interface means for selectively connecting the first internal bus or the second internal bus to an external bus, and bus control means for performing bus control and bus arbitration Ri comprises a semiconductor chip,
The bus control means can perform an access operation only inside the microcomputer using the first internal bus and an access operation of the external address space from the second bus via the bus interface means by the data transfer device. a der luma Lee black computer intended to,
The bus control means includes an internal bus controller that arbitrates a bus right request by a bus master means that shares the first bus, and an external bus controller that arbitrates a bus right request to access the external bus,
The external bus controller requests the external bus right from the internal bus controller when the bus master means requesting external access acquires the bus right from the internal bus controller, and from the first data transfer device. A microcomputer capable of arbitrating between an external bus right request and a bus right request given from the outside of the microcomputer . A microcomputer according to any one of claims 1 to 12 ,
An external bus connected to the microcomputer bus interface means;
A microcomputer system comprising a RAM connected to the external bus. A microcomputer according to claim 2 ;
An external bus connected to the microcomputer bus interface means;
A RAM connected to the external bus;
Including a data communication circuit connected to the external bus,
The data communication circuit supplies an external data transfer activation request signal to the first data transfer device of the microcomputer;
The microcomputer system according to claim 1, wherein when the bus right is approved by the bus control means, the first data transfer device instructs the data communication circuit to transfer by an external data transfer approval signal. The first data transfer device can control data transfer between the data communication circuit and the RAM in a single addressing mode, and instructs the data communication circuit to transfer by the external data transfer approval signal, 15. The microcomputer system according to claim 14, wherein the RAM is instructed to start access by an access address signal. The first data transfer device has address specifying means for specifying an initial value of address information, address buffer means, and arithmetic operation means,
The address information output by the addressing means is supplied to the address buffer means and arithmetic operation means,
The address information supplied to the address buffer means can be supplied to the bus interface means,
The arithmetic operation means performs an arithmetic operation on the condition that a value of a higher bit than a predetermined bit position of the address information is fixed with respect to the input address information, and supplies the operation result to the address designating means. 16. The microcomputer system according to claim 15, wherein: The arithmetic operation means performs, as the arithmetic operation, an operation for incrementing or decrementing a RAM address designated by the address designating means so that the RAM can be used as a ring buffer. The microcomputer system according to claim 16 .

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