JP3960091B2

JP3960091B2 - Semiconductor device and manufacturing method thereof

Info

Publication number: JP3960091B2
Application number: JP2002077671A
Authority: JP
Inventors: 明彦大井
Original assignee: Fuji Electric Holdings Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2002-03-20
Filing date: 2002-03-20
Publication date: 2007-08-15
Anticipated expiration: 2022-03-20
Also published as: JP2003282870A

Description

【０００１】
【発明の属する技術分野】
この発明は、トレンチゲート構造を有する半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
トレンチゲートを用いる素子においては、トレンチ内に形成されるゲート電極と、このゲート電極と接続するゲート配線引出し部（ゲートパッドのこと）との境界部であるトレンチ開口周縁部では、トレンチ内に埋め込まれるドープド・ポリシリコン（不純物をドープしたポリシリコンで抵抗値が極めて低いポリシリコンのこと）とトレンチから引き出されるゲート配線引出し部であるゲートパッドは同時に製作されるために、ゲートパッドのドープド・ポリシリコン直下の酸化膜はトレンチ内に形成されるゲート酸化膜の膜厚と等しくなる。
【０００３】
図７および図８は、従来の半導体装置で、図７は要部平面図、図８（ａ）は図７のＦ−Ｆ線で切断した要部断面図、図８（ｂ）は図７のＧ−Ｇ線で切断した要部断面図である。
図７および図８において、ｎシリコン基板２０１にストライプ状のトレンチ２２３を形成し、トレンチ２２３を挟んでｐウエル領域２２１を形成し、ｐウエル領域２２１の表面層にトレンチ２２３を挟んでｎ⁺ソース領域２２２を形成し、トレンチ２２３の側壁および底面にゲート酸化膜２０６を形成し、ｎシリコン基板２０１上にも、同時にゲート酸化膜２０６が形成され、このゲート酸化膜２０６は絶縁用酸化膜となる。トレンチ２２３にゲート酸化膜２０６を介してポリシリコンを充填し、ゲート電極２０７ａを形成し、またトレンチ２２３の長手方向の端部側のゲート酸化膜２０６を介してポリシリコンでゲート配線引出し部であるゲートパッド２０７ｂを形成する。
【０００４】
尚、以下の説明では、トレンチ開口周縁部を、図８（ａ）のｎ+ ソース領域２２２がある箇所（詳しくは、ｎ+ ソース領域２２２の長手方向端部とゲートパッド２０７ｂ端部の間の中間点）のトレンチ開口周縁部（以下、第１周縁部２３１と称す）と、同図（ｂ）のゲートパッド２０７ｂと隣接する箇所のトレンチ開口周縁部（以下、第２周縁部２３２と称す）に分け、単にトレンチ開口周縁部という場合は両者を合わせたものを指すことととする。また、図７の２２４はゲート配線用のコンタクトホールである。
【０００５】
【発明が解決しようとする課題】
ゲート酸化膜を介して、ゲート容量による電流（Ｃ・ｄＶ／ｄｔ）が第２周縁部２３２上のポリシリコンを通してゲートパッド２０７ｂに流れ、この第２周縁部２３２のコーナー部２１１のゲート酸化膜２０６ｂ付近での電位分布がこの電流で乱される。また、形状的要因で、ゲート電圧印加時には、トレンチの先端箇所のコーナー部２１１、２１２のゲート酸化膜２０６付近では電界集中を起こしやすくなる（正のゲート電圧では２１１、負のゲート電圧では２１２で電界集中が起きやすい）。その結果、この箇所で、ゲート耐圧破壊が起こる。図９は、従来の半導体装置のゲート絶縁耐圧分布を示す図である。電界集中の割合は２１１、２１２の曲率半径に強く依存するため、ゲート絶縁耐圧分布もブロードになる。
【０００６】
この発明の目的は、前記の課題を解決して、ゲート絶縁耐圧の向上を図ることができる半導体装置およびその製造方法を提供することにある。
【０００７】
【課題を解決するための手段】
前記の目的を達成するために、半導体基板に形成されたストライプ状のトレンチと、該トレンチ内面および前記トレンチに隣接する前記半導体基板表面上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に前記トレンチ内に充填されたゲート電極と、前記トレンチの長手方向の端部側で前記ゲート絶縁膜を介して前記ゲート電極と同じ材料で形成されたゲート配線引出し部とを具備する半導体装置において、前記トレンチの平面形状は、同一の幅を有する第１箇所と端部が徐々に狭くなっている第２箇所から構成され、前記ゲート絶縁膜の内、第１箇所に形成される第１ゲート絶縁膜の厚さより第２箇所に形成される第２ゲート絶縁膜の厚さを厚くする構成とする。
【０００８】
半導体基板に形成されたストライプ状のトレンチと、該トレンチ内面および前記トレンチに隣接する前記半導体基板表面上に形成されたゲート絶縁膜と、該ゲート絶縁膜を介して前記トレンチ内に充填されたゲート電極と、前記トレンチの長手方向の端部側で前記ゲート絶縁膜を介して前記ゲート電極と同じ材料で形成されたゲート配線引出し部とを具備する半導体装置において、前記トレンチの先端近傍を除く箇所において、ゲート配線引出し部が、ゲート電極と接続する構成とする。
【０００９】
また、前記ゲート電極および前記ゲート配線引出し部が、ポリシリコンで形成されるとよい。また、半導体基板に形成されたストライプ状のトレンチと、該トレンチ内面および前記トレンチに隣接する前記半導体基板表面上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に前記トレンチ内に充填されたゲート電極と、前記トレンチの長手方向の端部側で前記ゲート絶縁膜を介して前記ゲート電極と同じ材料で形成されたゲート配線引出し部とを具備する半導体装置の製造方法において、前記半導体基板に、平面形状が一定幅の第１箇所と、端部が徐々に狭くなる第２箇所から成るトレンチを形成する工程と、前記トレンチ内面に厚い絶縁膜を形成して第２箇所の先端近傍のトレンチを該厚い絶縁膜で充填する工程と、前記第２箇所の先端近傍のトレンチに充填された厚い絶縁膜を残し、前記第１箇所の側壁に形成された前記厚い絶縁膜を除去する工程と、前記トレンチ内面および前記トレンチに隣接する前記半導体基板表面上に前記厚い絶縁膜よりも厚さが薄い薄い絶縁膜を形成する工程と、前記厚い絶縁膜および前記薄い絶縁膜からなる前記ゲート絶縁膜上に、ポリシリコンにより前記ゲート電極およびゲート配線引出し部を形成する工程とを含む製造方法とする。
【００１０】
【発明の実施の形態】
図１および図２は、この発明の第１実施例の半導体装置で、図１（ａ）は要部平面図、図１（ｂ）は図１（ａ）のイ部の拡大図、図２（ａ）は図１（ｂ）のＡ−Ａ線で切断した要部断面図、図２（ｂ）は図１（ｂ）のＢ−Ｂ線で切断した要部断面図、図２（ｃ）は図１（ｂ）のＣ−Ｃ線で切断した要部断面図である。
【００１１】
図１および図２において、ｎシリコン基板１０１にストライプ状のトレンチ１２３を形成する。このトレンチ１２３の両端部は、徐々に狭くなる形状となっている（一定幅の箇所が第１箇所で、徐々に狭くなっている箇所が第２箇所である）。トレンチ１２３を挟んでｐウエル領域１２１を形成し、ｐウエル領域１２１の表面層にトレンチ１２３を挟んでｎソース領域１２２を形成し、トレンチ１２３の側壁および底面に厚みがＷ１のゲート酸化膜１１８ａを形成し、トレンチ１２３の第２箇所の先端付近に厚い膜厚（Ｗ２）のゲート酸化膜１１８ｂを形成する。ｎシリコン基板１０１上に絶縁用酸化膜１１８ｃ（これは、ゲート酸化膜１１８ａと同時に形成する）を形成する。トレンチ１２３にゲート酸化膜１１８ａ、１１８ｂを介してポリシリコンを充填してゲート電極１１９ａを形成し、またトレンチ１２３の長手方向の端部側に、ゲート酸化膜１１８ｂおよび絶縁用酸化膜１１８ｃを介してポリシリコンでゲート配線引出し部であるゲートパッド１１９ｂを形成する。
【００１２】
図２（ａ）のチャネル形成領域上のゲート酸化膜１１８ａの膜厚を薄く形成し、図２（ｃ）のゲートパッドと隣接するトレンチ１２３の第２箇所の先端付近のゲート酸化膜１１８ｂの膜厚は厚く形成する。図中の１２４はポリシリコンのゲートパッド１１９ｂが図示しない金属配線と接続させるための図示しないゲートパッド上に形成する絶縁膜に形成されるコンタクトホールである。また、１３１は第１周縁部で、ａ−ａ点線間のトレンチ１２３の長手方向のトレンチ開口周縁部を示し、１３２は第２周縁部で、ａ−ａ点線より外側（Ｙ方向）のトレンチ１２３の端部先端付近のトレンチ開口周縁部を示す。
【００１３】
ゲートパッド１１９ｂにプラス、ｎ⁺ソース領域１２２にマイナスの極性で、ゲート電圧を印加したとき、ゲート容量を介して電流がゲートパッド１１９ｂからゲート電極１１９ａへ流れる。しかし、ゲート酸化膜１１８ｂが厚いために、この電流がコーナー部１１１ａでの電位分布へ与える影響は小さく、コーナー部１１１ａでの電界集中は小さい。そのため、ゲート破壊耐圧を向上させることができる。また、ゲート酸化膜１１８ｂの膜厚が厚いために、この箇所でのチャネル形成電圧であるゲートしきい値電圧を高くすることができる。そのため、この箇所でのゲートの機能を封じることができて、この箇所に主電流が流れないようにできる。このことで、半導体装置のゲート破壊耐圧が一層向上する。また、同様に、ゲートパッド１１９ｂにマイナス、ｎ⁺ソース領域１２２にプラスの極性で、ゲート電圧を印加したときにも、コーナー部１１１ｂのゲート酸化膜１１８ｂが厚いために、この箇所での電界集中は小さい。
【００１４】
また、図２（ａ）のコーナー部１１２ａ、１１２ｂのゲート酸化膜１１８ａは薄いが、その上にゲートパッド１１９ｂへ接続するポリシリコンがない（図１（ｂ））ために、コーナー部１１２ａ、１１２ｂでの電界集中は小さい。
尚、図１および図２に示した半導体装置は完成品ではなく途中工程の一例であり、また、この図の他には、ｐウエル領域１２１がトレンチ１２３より深いものや、トレンチ１２３を挟むｎ⁺ソース領域１２２が互いに繋がっているものなど、多種多様のものがある。また、図１（ｂ）のＡ−Ａ線で切断した箇所にｎ⁺ソース領域１２２やｐウエル領域１２１が無い場合もある。
【００１５】
図３は、図１の半導体装置のゲート絶縁耐圧の分布を示した図である。厚いゲート酸化膜１１８ｂを形成したことで、ゲート絶縁耐圧の最小値は高くなり、分布もシャープになっている。図４は、この発明の第２実施例の半導体装置の製造方法で、同図（ａ）から同図（ｄ）はトレンチにゲート酸化膜とゲート電極を形成する工程を工程順に示した要部平面図である。この図は図１（ｂ）に相当した図である。図示しないｐウェル領域１２１やｎ+ ソース領域１２１を形成した半導体基板１０１に端部が徐々に狭くなったストライプ状のトレンチ１２３を形成する。トレンチ１２３の一定幅の箇所は１μｍ程度である（同図（ａ））。つぎに、ＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法で、例えば、４００ｎｍの厚い酸化膜１１８ｃをトレンチ１２３内に形成する。先端近傍は、トレンチ１２３の側壁に形成された酸化膜同士が接触して、この先端付近は酸化膜１１８ｃで埋め尽くされる（充填される）（同図（ｂ））。つぎに、一定幅のトレンチ１２３の側壁が露出するまで、酸化膜１１８ｃを除去する。このとき、トレンチ１２３の先端近傍には酸化膜１１８ｃが残留する（同図（ｃ））。つぎに、例えば、１００ｎｍの薄い膜厚のゲート酸化膜１１８ａをトレンチ１２３の側壁と底面に形成する。先端付近は、先に形成した酸化膜１１８ｃと今回形成したゲート酸化膜１１８ａを合わせたものが厚いゲート酸化膜１１８ｂとなる。その後で、トレンチ１２３にゲート酸化膜１１８ａ、１１８ｂを介して、蒸着でポリシリコンを充填し、ゲート電極１１９ａを形成する（同図（ｄ））。
【００１６】
図５は、この発明の第３実施例の半導体装置であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のロ部の拡大図である。
図１との違いは、トレンチ１１９ａが長方形をしている点と、このトレンチ１１９ａの端部がゲートパッド１１９ｂに接していない点である。トレンチ１１９ａの端部が、ゲートパッド１１９ｂと接していないために、この端部でのゲート容量による電流の流れがなくなり、従って電界集中が起こらず、ゲート絶縁耐量が向上する。
【００１７】
図６は、この発明の第４実施例の半導体装置の要部平面図である。この図は、図１（ｂ）に相当する図で、図１との違いは、図５と同様に、トレンチ１１９ａの端部がゲートパッド１１９ｂと接していない点である。図５と同様の効果が期待できる。
【００１８】
【発明の効果】
この発明によれば、トレンチ端部を徐々に狭めたストライプ状として、端部の先端近傍のゲート絶縁膜の厚さを厚くすることで、形状に起因した電界集中によるゲート絶縁破壊を防止し、ゲート絶縁耐圧の向上と、ゲート絶縁耐圧のばらつきの低減を図ることができる。
【００１９】
また、トレンチ端部にゲートパットを接触させないことで、形状に起因した電界集中によるゲート絶縁破壊を防止し、ゲート絶縁耐圧の向上と、ゲート絶縁耐圧のばらつきの低減を図ることができる。
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置で、（ａ）は要部平面図、（ｂ）は（ａ）のイ部の拡大図
【図２】この発明の第１実施例の半導体装置で、（ａ）は図１（ｂ）のＡ−Ａ線で切断した要部断面図、（ｂ）は図１（ｂ）のＢ−Ｂ線で切断した要部断面図、（ｃ）は図１（ｂ）のＣ−Ｃ線で切断した要部断面図
【図３】図１の半導体装置のゲート絶縁耐圧の分布を示した図
【図４】この発明の第２実施例の半導体装置の製造方法で、（ａ）から（ｄ）はトレンチにゲート酸化膜とゲート電極を形成する工程を工程順に示した要部平面図
【図５】この発明の第３実施例の半導体装置であり、（ａ）は要部平面図、（ｂ）は（ａ）のロ部の拡大図
【図６】この発明の第４実施例の半導体装置の要部平面図
【図７】従来の半導体装置の要部平面図
【図８】従来の半導体装置の要部平面図で、（ａ）は図７のＦ−Ｆ線で切断した要部断面図、（ｂ）は図７のＧ−Ｇ線で切断した要部断面図
【図９】従来の半導体装置のゲート絶縁耐圧分布を示す図
【符号の説明】
１０１ｎシリコン基板
１０２第１熱酸化膜
１０３第１フォトレジスト
１０４第２熱酸化膜（犠牲酸化膜）
１１１ａ、１１１ｂ、１１２ａ、１１２ｂコーナー部
１１８ａ、１１８ｂゲート酸化膜
１１８ｃ酸化膜
１１９ａゲート電極
１１９ｂゲートパッド
１２１ｐウエル領域
１２２ｎ⁺ソース領域
１２３トレンチ
１２４コンタクトホール
１３１第１周縁部
１３２第２周縁部
Ｗ１薄いゲート酸化膜の厚さ
Ｗ２厚いゲート酸化膜の厚さ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a trench gate structure and a method for manufacturing the same.
[0002]
[Prior art]
In an element using a trench gate, a trench opening peripheral portion which is a boundary portion between a gate electrode formed in the trench and a gate wiring lead portion (gate pad) connected to the gate electrode is embedded in the trench. Since the doped polysilicon (polysilicon doped with impurities and polysilicon having a very low resistance value) and the gate pad which is the gate wiring lead-out portion extracted from the trench are manufactured at the same time, the doped polysilicon of the gate pad The oxide film immediately below the silicon becomes equal to the thickness of the gate oxide film formed in the trench.
[0003]
7 and 8 show a conventional semiconductor device. FIG. 7 is a plan view of the main part, FIG. 8A is a cross-sectional view of the main part taken along the line FF of FIG. 7, and FIG. It is principal part sectional drawing cut | disconnected by the GG line | wire.
7 and 8, a stripe-shaped trench 223 is formed in an n silicon substrate 201, a p-well region 221 is formed with the trench 223 interposed therebetween, and an n ⁺ source with the trench 223 sandwiched between the surface layers of the p-well region 221. Region 222 is formed, gate oxide film 206 is formed on the side wall and bottom surface of trench 223, and gate oxide film 206 is simultaneously formed on n silicon substrate 201. This gate oxide film 206 becomes an insulating oxide film. . The trench 223 is filled with polysilicon via a gate oxide film 206 to form a gate electrode 207a, and is a gate wiring lead-out portion made of polysilicon via the gate oxide film 206 on the end side in the longitudinal direction of the trench 223. A gate pad 207b is formed.
[0004]
In the following description, the peripheral edge of the trench opening is located at the location where the n + source region 222 is located in FIG. 8A (specifically, between the longitudinal end of the n + source region 222 and the end of the gate pad 207 b. A trench opening peripheral portion (hereinafter referred to as a first peripheral portion 231) at the intermediate point) and a trench opening peripheral portion (hereinafter referred to as a second peripheral portion 232) adjacent to the gate pad 207b in FIG. When it is simply referred to as the peripheral edge of the trench opening, it refers to a combination of both. Further, reference numeral 224 in FIG. 7 is a contact hole for gate wiring.
[0005]
[Problems to be solved by the invention]
A current (C · dV / dt) due to the gate capacitance flows through the polysilicon on the second peripheral portion 232 to the gate pad 207b through the gate oxide film, and the gate oxide film 206b at the corner portion 211 of the second peripheral portion 232 is supplied. The potential distribution in the vicinity is disturbed by this current. Also, due to the shape factor, when a gate voltage is applied, electric field concentration is likely to occur near the gate oxide film 206 at the corners 211 and 212 at the tip of the trench (211 for a positive gate voltage and 212 for a negative gate voltage). Electric field concentration is likely to occur). As a result, breakdown voltage of the gate occurs at this point. FIG. 9 is a diagram showing a gate dielectric breakdown voltage distribution of a conventional semiconductor device. Since the electric field concentration ratio strongly depends on the curvature radii of 211 and 212, the gate dielectric breakdown voltage distribution is also broad.
[0006]
An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above-described problems and can improve the gate breakdown voltage.
[0007]
[Means for Solving the Problems]
To achieve the above object, a stripe-shaped trench formed in a semiconductor substrate, a gate insulating film formed on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench , and on the gate insulating film In a semiconductor device comprising: a gate electrode filled in the trench; and a gate wiring lead portion formed of the same material as the gate electrode through the gate insulating film on a longitudinal end side of the trench . The planar shape of the trench is composed of a first location having the same width and a second location where the end portion is gradually narrowed, and a first gate insulation formed at the first location in the gate insulating film. The second gate insulating film formed at the second location is thicker than the thickness of the film.
[0008]
A stripe-shaped trench formed in a semiconductor substrate, a gate insulating film formed on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench, and a gate filled in the trench through the gate insulating film In a semiconductor device comprising an electrode and a gate wiring lead portion formed of the same material as the gate electrode through the gate insulating film on the longitudinal end side of the trench, a portion excluding the vicinity of the tip of the trench The gate wiring lead portion is connected to the gate electrode .
[0009]
The gate electrode and the gate wiring lead portion may be formed of polysilicon. Further, a stripe-shaped trench formed in the semiconductor substrate, a gate insulating film formed on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench, and the trench filled in the gate insulating film In the method of manufacturing a semiconductor device, comprising: a gate electrode; and a gate wiring lead portion formed of the same material as the gate electrode through the gate insulating film on a longitudinal end side of the trench. A step of forming a trench composed of a first portion having a constant planar shape and a second portion whose end portion is gradually narrowed; and a trench in the vicinity of the tip of the second portion by forming a thick insulating film on the inner surface of the trench The thick insulating film formed on the side wall of the first location, leaving the thick insulating film filled in the trench near the tip of the second location. Removing a thin insulating film thinner than the thick insulating film on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench; and from the thick insulating film and the thin insulating film Forming a gate electrode and a gate wiring lead portion on the gate insulating film using polysilicon .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
1 and 2 show a semiconductor device according to a first embodiment of the present invention, in which FIG. 1 (a) is a plan view of an essential part, FIG. 1 (b) is an enlarged view of a portion of FIG. 2A is a cross-sectional view of the main part cut along the line AA in FIG. 1B, FIG. 2B is a cross-sectional view of the main part cut along the line BB in FIG. 1B, and FIG. ) Is a cross-sectional view of the principal part taken along line CC in FIG.
[0011]
1 and 2, a stripe-shaped trench 123 is formed in an n silicon substrate 101. Both end portions of the trench 123 are gradually narrowed (a portion having a certain width is a first portion, and a portion gradually narrowing is a second portion). A p-well region 121 is formed across the trench 123, an n-source region 122 is formed across the trench 123 on the surface layer of the p-well region 121, and a gate oxide film 118a having a thickness W1 is formed on the sidewall and bottom surface of the trench 123. Then, a thick (W2) gate oxide film 118b is formed near the tip of the second portion of the trench 123. An insulating oxide film 118c (which is formed simultaneously with the gate oxide film 118a) is formed on the n silicon substrate 101. The trench 123 is filled with polysilicon through the gate oxide films 118a and 118b to form the gate electrode 119a, and the trench 123 is disposed at the end in the longitudinal direction via the gate oxide film 118b and the insulating oxide film 118c. A gate pad 119b, which is a gate wiring lead portion, is formed of polysilicon.
[0012]
The gate oxide film 118a on the channel formation region of FIG. 2A is formed thin, and the gate oxide film 118b near the tip of the second portion of the trench 123 adjacent to the gate pad of FIG. The thickness is formed thick. In the figure, reference numeral 124 denotes a contact hole formed in an insulating film formed on a gate pad (not shown) for connecting a polysilicon gate pad 119b to a metal wiring (not shown). Reference numeral 131 denotes a first peripheral edge, which indicates a peripheral edge of the trench opening in the longitudinal direction of the trench 123 between the aa dotted lines. Reference numeral 132 denotes a second peripheral edge, which is the trench 123 on the outer side (Y direction) from the aa dotted line. The trench opening peripheral part of the edge part vicinity is shown.
[0013]
When a gate voltage is applied with a positive polarity to the gate pad 119b and a negative polarity to the n ⁺ source region 122, a current flows from the gate pad 119b to the gate electrode 119a through the gate capacitance. However, since the gate oxide film 118b is thick, the influence of this current on the potential distribution at the corner portion 111a is small, and the electric field concentration at the corner portion 111a is small. Therefore, the gate breakdown voltage can be improved. Further, since the gate oxide film 118b is thick, the gate threshold voltage, which is a channel formation voltage at this point, can be increased. Therefore, the function of the gate at this location can be sealed, and the main current can be prevented from flowing through this location. This further improves the gate breakdown voltage of the semiconductor device. Similarly, even when a gate voltage is applied with a negative polarity to the gate pad 119b and a positive polarity to the n ⁺ source region 122, the gate oxide film 118b at the corner portion 111b is thick, so that the electric field concentration at this location. Is small.
[0014]
Further, although the gate oxide films 118a of the corner portions 112a and 112b in FIG. 2A are thin, there is no polysilicon connected to the gate pad 119b (FIG. 1B), so that the corner portions 112a and 112b are formed. The electric field concentration at is small.
The semiconductor device shown in FIGS. 1 and 2 is not a finished product but an example of an intermediate process. In addition to this figure, the p-well region 121 is deeper than the trench 123 or n sandwiches the trench 123. ⁺ There are a wide variety of things, such as those in which the source regions 122 are connected to each other. In some cases, the n ⁺ source region 122 and the p well region 121 are not present at the location cut along the line AA in FIG.
[0015]
FIG. 3 is a diagram showing a distribution of gate dielectric strength of the semiconductor device of FIG. By forming the thick gate oxide film 118b, the minimum value of the gate withstand voltage is increased and the distribution is sharp. FIG. 4 shows a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS. 4A to 4D are schematic views showing the steps of forming a gate oxide film and a gate electrode in the trench in order of steps. It is a top view. This figure corresponds to FIG. 1 (b). Striped trenches 123 whose end portions are gradually narrowed are formed in the semiconductor substrate 101 on which a p-well region 121 and an n + source region 121 (not shown) are formed. The portion of the trench 123 having a constant width is about 1 μm ((a) in the figure). Next, a 400 nm thick oxide film 118c, for example, is formed in the trench 123 by a CVD (Chemical Vapor Deposition) method. In the vicinity of the tip, the oxide films formed on the side walls of the trench 123 come into contact with each other, and the vicinity of the tip is filled (filled) with the oxide film 118c (FIG. 5B). Next, the oxide film 118c is removed until the sidewall of the trench 123 having a constant width is exposed. At this time, an oxide film 118c remains in the vicinity of the tip of the trench 123 ((c) in the figure). Next, for example, a gate oxide film 118 a having a thin film thickness of 100 nm is formed on the side wall and the bottom surface of the trench 123. In the vicinity of the tip, a thick gate oxide film 118b is formed by combining the previously formed oxide film 118c and the gate oxide film 118a formed this time. Thereafter, the trench 123 is filled with polysilicon by vapor deposition through the gate oxide films 118a and 118b to form the gate electrode 119a (FIG. 4D).
[0016]
FIGS. 5A and 5B show a semiconductor device according to a third embodiment of the present invention, in which FIG. 5A is a plan view of an essential part, and FIG. 5B is an enlarged view of a portion B of FIG.
The difference from FIG. 1 is that the trench 119a is rectangular and the end of the trench 119a is not in contact with the gate pad 119b. Since the end portion of the trench 119a is not in contact with the gate pad 119b, there is no current flow due to the gate capacitance at this end portion, so that electric field concentration does not occur and the gate dielectric strength is improved.
[0017]
FIG. 6 is a plan view of the main part of the semiconductor device according to the fourth embodiment of the present invention. This figure corresponds to FIG. 1B, and the difference from FIG. 1 is that the end of the trench 119a is not in contact with the gate pad 119b, as in FIG. The same effect as FIG. 5 can be expected.
[0018]
【The invention's effect】
According to this invention, the trench end portion is gradually narrowed in a stripe shape, and by increasing the thickness of the gate insulating film near the end of the end portion, gate breakdown due to electric field concentration due to the shape is prevented, It is possible to improve the gate withstand voltage and reduce variations in the gate withstand voltage.
[0019]
In addition, since the gate pad is not brought into contact with the end of the trench, gate dielectric breakdown due to electric field concentration due to the shape can be prevented, and gate dielectric breakdown voltage can be improved and variation in gate dielectric breakdown voltage can be reduced.
[Brief description of the drawings]
1A is a plan view of an essential part of a semiconductor device according to a first embodiment of the present invention; FIG. 1B is an enlarged view of a portion of FIG. 2A; In the semiconductor device, (a) is a cross-sectional view taken along line AA in FIG. 1 (b), (b) is a cross-sectional view taken along line BB in FIG. 1 (b), and (c) ) Is a cross-sectional view of the main part taken along the line CC in FIG. 1B. FIG. 3 is a diagram showing the distribution of gate dielectric strength of the semiconductor device in FIG. 1. FIG. 4 shows the second embodiment of the present invention. FIGS. 5A to 5D are main part plan views showing steps of forming a gate oxide film and a gate electrode in a trench in order of the manufacturing method of a semiconductor device. FIG. 5 is a semiconductor device according to a third embodiment of the present invention. (A) is a plan view of the main part, (b) is an enlarged view of the part (b) of (a). FIG. 6 is a plan view of the main part of the semiconductor device according to the fourth embodiment of the present invention. Main part of semiconductor device FIG. 8 is a plan view of a main part of a conventional semiconductor device, where (a) is a cross-sectional view of the main part taken along line FF in FIG. 7, and (b) is a cross-sectional view taken along line GG in FIG. FIG. 9 is a partial cross-sectional view. FIG. 9 is a diagram showing a gate dielectric breakdown voltage distribution of a conventional semiconductor device.
101 n silicon substrate 102 first thermal oxide film 103 first photoresist 104 second thermal oxide film (sacrificial oxide film)
111a, 111b, 112a, 112b Corner portions 118a, 118b Gate oxide film 118c Oxide film 119a Gate electrode 119b Gate pad 121 p well region 122 n ⁺ source region 123 trench 124 contact hole 131 first peripheral portion 132 second peripheral portion W1 thin Gate oxide thickness W2 Thick gate oxide thickness

Claims

A stripe-shaped trench formed in a semiconductor substrate, a gate insulating film formed on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench, and a gate electrode filled in the trench on the gate insulating film And a gate wiring lead portion formed of the same material as the gate electrode through the gate insulating film on the end side in the longitudinal direction of the trench, the planar shape of the trench is the same It is composed of a first portion having a width and a second portion where the end portion is gradually narrowed, and is formed in the second portion from the thickness of the first gate insulating film formed in the first portion of the gate insulating film. A semiconductor device characterized in that the thickness of the second gate insulating film is increased.

A stripe-shaped trench formed in a semiconductor substrate, a gate insulating film formed on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench, and a gate filled in the trench through the gate insulating film In a semiconductor device comprising an electrode and a gate wiring lead portion formed of the same material as the gate electrode through the gate insulating film on the longitudinal end side of the trench, a portion excluding the vicinity of the tip of the trench A semiconductor device, wherein the gate wiring lead portion is connected to the gate electrode.

3. The semiconductor device according to claim 1, wherein the gate electrode and the gate wiring lead portion are formed of polysilicon.

A stripe-shaped trench formed in a semiconductor substrate, a gate insulating film formed on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench, and a gate electrode filled in the trench on the gate insulating film And a gate wiring lead portion formed of the same material as that of the gate electrode through the gate insulating film on the end side in the longitudinal direction of the trench. Forming a trench comprising a first portion having a constant width and a second portion having a gradually narrowed end, and forming a thick insulating film on the inner surface of the trench to form a trench near the tip of the second portion. The step of filling with a thick insulating film, and leaving the thick insulating film filled in the trench near the tip of the second location, excluding the thick insulating film formed on the side wall of the first location. A step of forming a thin insulating film having a thickness smaller than that of the thick insulating film on the inner surface of the trench and the surface of the semiconductor substrate adjacent to the trench, and the thick insulating film and the thin insulating film. And a step of forming the gate electrode and the gate wiring lead portion on the gate insulating film with polysilicon.