JP3867730B2 - Integrated circuit for digital signal processing - Google Patents

Description

  The present invention relates to an integrated circuit for processing digital image signals, for example.

  For example, when the processing hardware of a digital image signal is an LSI, one method is to develop and design a dedicated LSI corresponding to the processing, and the other method is a DSP (Digital Signal having versatility). Processor). The DSP is composed of a product-sum operation unit, RAM / ROM, and the like, and can perform digital signal processing such as FFT and digital filter.

  In the case of a method for developing and designing a dedicated LSI, it is necessary to develop and design the LSI for the number of types of digital signal processing. Further, the DSP is excellent in versatility, but has a problem of poor efficiency.

  Accordingly, it is an object of the present invention to provide an integrated circuit for digital signal processing that can share a basic hardware configuration and realize a plurality of functions by one chip.

In order to solve the above-mentioned problems, the present invention is provided with a selection means capable of switching between a plurality of circuit groups and at least two states in a single integrated circuit, and the selection means is selected by an external signal. An integrated circuit for digital signal processing that is controlled and enables classification adaptive processing,
When the selection means takes the first selection state, at least a part of the plurality of circuit groups is set to the first connection state so that the first signal processing function by the class classification adaptive processing can be performed in the first connection state. When the selection means takes the second selection state, at least a part of the plurality of circuit groups is set to a second connection state different from the first connection state, and the first signal processing function is established in this connection state. is Ninasa to perform second signal processing function according to different classification adaptive processing and,
At the same time, at least a part of the plurality of circuit groups has different circuit functions depending on the selection state of the selection means, whereby the signal processing function of the entire integrated circuit is switched. An integrated circuit for digital signal processing.
In the present invention, the selection means is controlled by a control signal given from the outside of the integrated circuit, whereby the connection state of the plurality of circuit groups is switched. A single chip integrated circuit can realize a plurality of functions that can share the hardware configuration in the integrated circuit and can be selectively designated by a control signal.

  The present invention is not limited to a specific function like a dedicated LSI, and limits the range of functions to be realized to some extent like the class classification adaptive processing in the above-described embodiment. Although not versatile, efficient processing can be performed.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of the present invention. That is, in FIG. 1, the configuration surrounded by a broken line is the configuration of a one-chip integrated circuit (LSI) 1. The LSI 1 is provided with input terminals t1 and t2, output terminals t3 and t4, and a control signal input terminal t5. Although not shown, actually, in addition to the input / output terminals, a power supply terminal, a test terminal, and the like are provided in the LSI 1 as usual.

  A plurality of circuit groups are formed in the LSI 1. These are arithmetic circuit groups 11a and 11b, memories 12a and 12b, product-sum arithmetic circuit groups 13a and 13b, adders 14a and 14b, multipliers 15a and 15b, and register groups 16a and 16b. Then, for these circuit groups or circuits, the input / output or mutual connection state (which means both circuit groups or interconnections between circuits and interconnections between circuits within the circuit groups) is switched. A switching device for this purpose is provided in the LSI 1. In other words, the flow of digital signals in the LSI 1 and the function of each circuit group can be controlled by the control signals.

  In other words, switching devices 21a and 21b are provided in association with the arithmetic circuit groups 11a and 11b, switching devices 22a and 22b are provided in association with the memories 12a and 12b, and related to the product-sum arithmetic circuit groups 13a and 13b. Switching devices 23a and 23b are provided. Further, a switcher 24 is provided in association with the adders 14a and 14b, the multipliers 15a and 15b, and the register groups 16a and 16b. These switching devices 21a, 21b, 22a, 22b, 23a, 23b and 24 are supplied with control signals S1 to S7 of several bits, respectively. The control signals S1 to S7 can be supplied from an external control signal generator (for example, a configuration in which a predetermined control signal is generated by a lip switch) through a control signal input terminal t5.

  The above-described configuration of the present invention can process a plurality of digital signals by changing the control signal. A specific example will be described. First, an example applied to the up-conversion processing of a digital television signal will be described. Here, a standard-definition digital television signal (referred to as an SD signal) is input, and the number of pixels is first separated by a process of first doubling the number of pixels in the horizontal direction and then doubling the number of pixels in the vertical direction. An example of up-conversion for forming a digital television signal (referred to as HD signal) with a resolution of 4 times as high will be described.

  FIG. 2 shows the LSI 1 configured to perform such up-conversion processing using the control signals S1 to S7. A class classification circuit 31a and one-dimensional filters 32a and 33a are connected to an input terminal t1 to which an SD signal is supplied. Class information (code signal) from the class classification circuit 31a is supplied as an address to the coefficient memory 34a. In the coefficient memory 34a, coefficients obtained by learning in advance are stored. The coefficients read from the coefficient memory 34a are supplied to the one-dimensional filters 32a and 33a.

  The one-dimensional filters 32a and 32b multiply the plurality of pixel data of the SD signal and the plurality of coefficients from the coefficient memory 34a, respectively, and add the multiplication results. The outputs of the one-dimensional filters 32a and 33a are supplied to the mixing circuit 35a, and the output of the mixing circuit 35a is taken out to the output terminal t3. The configuration between the input terminal t1 and the output terminal t3 doubles the number of pixels in the horizontal direction. This output signal is supplied to the scanning line conversion circuit 36a. The scanning line conversion circuit 36a includes a memory, and performs conversion from horizontal scanning (television raster scanning order) to vertical scanning. That is, pixels aligned in the vertical direction are output in order from top to bottom.

  The output signal of the scanning line conversion circuit 36a is supplied to the input terminal t2 of the LSI 1 again. A configuration similar to that of the input terminal t1 is connected to the input terminal t2. That is, it comprises a class classification circuit 31b, one-dimensional filters 32b and 33b, a coefficient memory 34b, and a mixing circuit 35b, and is provided with a circuit configuration for doubling the number of pixels in the vertical direction. Accordingly, the number of pixels is doubled in the horizontal and vertical directions at the output terminal t4, and a signal having a quadruple number of pixels is extracted. Then, the pixel order is converted from vertical scanning to horizontal scanning by the scanning line conversion circuit 36b outside the LSI 1. An HD signal is obtained from the scanning line conversion circuit 36b.

  The correspondence relationship between the up-conversion configuration of FIG. 2 and the configuration of FIG. 1 will be described. The class classification circuits 31a and 31b are configured by arithmetic circuit groups 11a and 11b. The coefficient memories 34a and 34b are composed of memories 12a and 12b. The one-dimensional filters 32a, 32b, 33a, and 33b are configured by product-sum operation circuit groups 13a and 13b. The mixing circuits 35a and 35b are composed of adders 14a and 14b and register groups 16a and 16b.

The up-conversion process will be described in more detail. FIG. 3 shows a relationship between a plurality of pixel data on the same line of the input SD signal and a horizontal double speed signal formed from this (the number of pixels is doubled in the horizontal direction). . As an example, the target pixel is obtained by linear linear combination of _seven pixels x _{1 to} x 7 that are continuous in the horizontal direction and two sets of coefficients a _{1 to} a ₇ and b _{1 to} b ₇ read from the coefficient memory 34a. Values y _a ′ and y _b ′ are generated. That is,
y _a ′ = a ₁ x ₁ + a ₂ x ₂ +... + a ₇ x ₇
y _b ′ = b ₁ x ₁ + b ₂ x ₂ +... + b ₇ x ₇

One predicted pixel value y _a ′ is obtained from the one-dimensional filter 32a, and the other predicted pixel value y _b
'Is obtained from the one-dimensional filter 32b. These pixels are selectively output alternately by the mixing circuit 35a. For example, when the input SD signal is 13.5 MHz, 27 MHz of a horizontal double speed signal having a sampling rate of 27 MHz is obtained at the output terminal t3. This horizontal double speed signal is converted into a 27 MHz vertical signal by the scanning line conversion circuit 36a. Then, it is supplied to the input terminal t2 of the LSI 1 and converted into a doubled number of pixels in the same manner as described above, and a vertical double speed signal with a sampling rate of 54 MHz is generated from the output terminal t4. This is supplied to the external scanning line conversion circuit 36b, and a 54 MHz HD signal is obtained.

The coefficients stored in the coefficient memories 34a and 34b are acquired in advance by learning. This coefficient is determined for each class of the target pixel. For example, in FIG. 3, y _a ′ and y _b ′ are data of the target pixel. Since the class classification of the two target pixels is common, the two sets of coefficients stored in the coefficient memory are stored as higher-order data and lower-order data of the same address. One of the classification methods uses a level distribution pattern of an input signal around a pixel of interest. For example, in FIG. 3, classification is performed based on a level distribution pattern of _three pixel data x ₃ , x ₄ , and x ₅ of the SD signal around the target pixel.

In general, since pixel data is 8-bit quantized data, in the case of 3 pixels, (8 × 3 = 24 bits), and all combinations of 24 bits are 2 ²⁴ . The number of classes is enormous, and hardware such as a memory for storing coefficients becomes complicated. Therefore, the class classification circuits 31a and 31b set the number of classes to an appropriate value by compressing the number of bits of each pixel used for class classification.

  One method for compressing the number of bits of each pixel referred for classification is to normalize each pixel in the level direction. As an example, an average value of three pixels to be referred to is obtained, and surrounding pixels are compressed from 8 bits to 1 bit according to a magnitude relationship with respect to the average value. That is, if the value is greater than the average value, ｀ 1 'is assigned, and if the value is less than the average value, ｀ 0' is assigned. As a result, class information is indicated by a 3-bit code signal.

  As another method of normalization, ADRC can be used. ADRC detects the dynamic range DR and minimum value MIN of a plurality of pixels, subtracts the minimum value MIN from the value of each pixel, divides the value obtained by subtracting the minimum value by the dynamic range DR, and converts the quotient to an integer. It is processing.

For example, in the case of 1-bit ADRC, the maximum value MAX and the minimum value MIN among the three pixels are detected, and the dynamic range DR (= MAX−MIN) is calculated. The minimum value MIN is subtracted from the value of each pixel, and the value after removal of the minimum value is divided by the dynamic range DR. The quotient of this division is compared with 0.5, and when it is 0.5 or more, it is ｀ 1 ′, and when the quotient is less than 0.5, it is ｀ 0 ′. The 1-bit ADRC provides substantially the same result as that for comparing the above average value and the value of each pixel. In the case of 2-bit ADRC, the value after removal of the minimum value is divided by the quantization step width calculated by DR / 2 ² .

  Next, learning for obtaining coefficients stored in the coefficient memories 34a and 34b will be described. FIG. 4 shows a configuration at the time of learning for determining the coefficient stored in the coefficient memory 34a. Since the determination of the coefficient stored in the coefficient memory 34b is the same, the description thereof is omitted. In FIG. 4, an HD signal is supplied to an input terminal 41, and the number of pixels is thinned in half in the horizontal direction by the thinning filter 42. An output signal of the thinning filter 42 is supplied to the coefficient determination circuit 43 and the class classification circuit 44. Similar to the class classification circuit 31a, the class classification circuit 44 uses the surrounding pixels to determine the class of the pixel of interest. The class code from the class classification circuit 44 is supplied to the coefficient determination circuit 43 and the memory 45, respectively.

  The coefficient determination circuit 43 determines a coefficient that minimizes the sum of squares of errors between a predicted value generated by linear linear combination and its true value. The HD signal supplied to the input terminal 41 is supplied to the coefficient determination circuit 43 as the true value of the target pixel. The coefficient determination circuit 43 determines the best prediction coefficient by the least square method. The determined coefficient is stored in the memory 45. The storage address is indicated by the class code from the class classification circuit 44.

  The operation of determining the coefficient by software processing will be described with reference to FIG. First, control of processing is started from step 51, and in the learning data formation of step 52, learning data corresponding to a known image is formed. At the end of the data at step 53, the control shifts to the prediction coefficient determination at step 56 if the processing of all input data, for example, one frame of data has been completed, and to the class determination at step 54 otherwise.

  The class determination in step 54 is a step for performing the class determination process for the pixel of interest described above to form a class code indicating the class. In the normal equation generation in the next step 55, a normal equation described later is created. After the processing of all data from the end of the data in step 53, the control shifts to step 56. In the prediction coefficient determination in step 56, a coefficient is determined by solving equation (8) described later using a matrix solving method. The prediction coefficient is stored in the memory 45 in the prediction coefficient store in step 57, and the control of the learning process is ended in step 58.

The processing of step 55 (normal equation generation) and step 56 (prediction coefficient determination) in FIG. 5 will be described in more detail. At the time of learning, the true value y of the target pixel is known. When the correction value of the pixel of interest is y ′ and the values of the surrounding pixels are x ₁ to x _n , the coefficients w ₁ to w _n (corresponding to a _{1 to} a ₇ or b _{1 to} b ₇ described above) for each class. Y ′ = w ₁ x ₁ + w ₂ x ₂ +... + W _n x _n (1)
Set. Before learning, w _i is an undetermined coefficient.

As described above, learning is performed for each class, and when the number of data is m, according to equation (1),
y _j ′ = w ₁ x _j1 + w _{2 xj2} +... + w _{n xjn} (2)
(However, j = 1, 2, ... m)

When m> n, w _{1 to} w _n are not uniquely determined, so the elements of the error vector E are expressed as e _j = y _j − (w ₁ x _j1 + w ₂ x _j2 +... + w _n x _jn ) ( 3)
(However, j = 1, 2, ... m)
And a coefficient that minimizes the following equation (4) is obtained.

This is a so-called least square method. Here, the partial differential coefficient according to w _i of the equation (4) is obtained.

Since Equation (5) may be determined each w _i to zero,

  As a matrix

It becomes. This equation is generally called a normal equation. Using the general matrix solution of sweeping-out method such as this equation, solving for w _i, Motomari prediction coefficient w _i, the class code as an address and stores the prediction coefficient w _i in the memory 45.

  Note that the up-conversion based on the class classification adaptation process is not limited to the above example, and various configurations are possible. For example, the predicted value itself can be acquired in advance by learning and stored in a memory. Also, the HD pixel value may be obtained by two-dimensional or three-dimensional processing instead of one-dimensional processing.

  Next, another example of the signal processing circuit constituted by the LSI 1 shown in FIG. 1 will be described. Another example is a digital noise reducer configured as shown in FIG. 6 by setting a control signal. In FIG. 6, a digital video signal including noise is supplied to an input terminal 61. The input video signal is supplied to the input terminal t1 of the LSI 1 and the frame memory 62. The video signal of the previous frame from the frame memory 62 is supplied to the input terminal t2 of the LSI 1.

  The video signal of the current frame from the input terminal t1 is supplied to the class classification circuit 63a, the two-dimensional filter 66a, the line memory 64, the class classification circuit 63b, and the three-dimensional filter 66b. The video signal of the previous frame from the input terminal t2 is supplied to the class classification circuit 63b and the three-dimensional filter 66b. The line memory 64 is provided in order to synchronize data of a plurality of adjacent lines of raster scan order data. The output data of the line memory 64 is supplied to the class classification circuit 63a, the two-dimensional filter 66a, the class classification circuit 63b, and the three-dimensional filter 66b.

  The class information (code signal) obtained by the class classification circuit 63a is supplied as an address to the coefficient memory 65a, and the class information obtained by the class classification circuit 63b is supplied as an address to the coefficient memory 65b. Coefficients obtained in advance by learning are stored in the coefficient memories 65a and 65b, and the coefficients read corresponding to the class information are supplied to the two-dimensional filter 65a and the three-dimensional filter 65b, respectively. The two-dimensional filter 66a generates pixel data from which noise is removed in units of two-dimensional blocks composed of a plurality of adjacent pixels in the current frame. The three-dimensional filter 66b generates pixel data from which noise has been removed in units of three-dimensional blocks including a plurality of pixels in the current frame and the previous frame.

  A video signal from which noise has been removed from the two-dimensional filter 66a is obtained at the output terminal t3. Output signals from the two-dimensional filter 66 a and the three-dimensional filter 66 b are supplied to the adder 67. The synthesized video signal from the adder 67, that is, the digital video signal from which noise has been removed is taken out to the output terminal t4. The adder 67 weights and adds the output signal of the two-dimensional filter 66a and the output signal of the three-dimensional filter 66b with the motion coefficient K. The motion coefficient K is generated by the class classification circuit 63b.

  The correspondence relationship between the configuration of the noise reducer of FIG. 6 and the configuration of FIG. 1 will be described. The class classification circuits 63a and 63b are configured by arithmetic circuit groups 11a and 11b. The coefficient memories 65a and 65b and the line memory 64 are constituted by memories 12a and 12b. The two-dimensional filter 66a and the three-dimensional filter 66b are configured by product-sum operation circuit groups 13a and 13b. The adder 67 includes adders 14a and 14b, multipliers 15a and 15b, and register groups 16a and 16b.

  The class classification circuit 63a performs two-dimensional class classification. That is, the class of the target pixel is determined based on the level distribution pattern of the block centered on the target pixel. On the other hand, the class classification circuit 63b performs three-dimensional class classification. The three-dimensional class classification may be performed based on the level distribution pattern of the three-dimensional block. However, in order to generate the motion coefficient K, the class classification based on the motion detection result is preferable.

As one of known motion detection methods, a so-called gradient method can be adopted. This is to obtain the amount of motion using the frame difference and inclination information (sampling difference in the horizontal direction and line difference in the vertical direction) for all pixels in the motion region. First, when the slope of the video signal moves, the frame difference ΔF (subtracts the corresponding pixel value of the previous frame from the pixel value of the current frame) and the sampling difference ΔE (subtracts the value of the previous pixel from the current pixel value) Find E). Then, from the integrated value Σ | ΔF | in the motion region of the absolute value | ΔF | of the frame difference ΔF and the integrated value Σ | ΔE | in the motion region of the absolute value | ΔE | The magnitude of the movement amount v1 is obtained. That is,
| V1 | = Σ | ΔF | / Σ | ΔE |
Here, the direction of movement is obtained from the relationship between the polarity of the frame difference ΔF and the polarity of the sampling difference ΔE. The vertical movement can be detected in the same manner.

  The class classification circuit 63b obtains a motion amount by the above-described gradient method, for example, and generates a motion coefficient K corresponding to the motion amount. Also, classification is performed based on the frame difference ΔF (or | ΔF |) and the sampling difference ΔE (or | ΔE |). In this case, a proper number of classes are formed using values obtained by normalizing these frame difference and sampling difference values.

  The above-described noise reducer will be described by taking two-dimensional processing as an example. In the coefficient memory 65a, coefficients previously obtained by learning are stored. FIG. 7 shows a configuration at the time of learning, and a digital video signal including noise is supplied to an input terminal 71. This input signal is supplied to the noise reducer 72 and the blocking circuit 73. The noise reducer 72 removes noise in the input signal. For example, a noise reducer 72 that uses an N-frame memory and forms an average value of N + 1 frame images can be used. That is, since noise is generally random, noise is removed by averaging.

  An output signal (noise reduction signal) of the noise reducer 72 is supplied to the blocking circuit 74. Blocking circuits 73 and 74 are time-series conversion circuits, and convert the raster scan order into block order data. An output signal of the blocking circuit 73 is supplied to the class classification circuit 75. The class classification circuit 75 determines the class of the target pixel based on the level distribution in the block centered on the target pixel. The class information from the class classification circuit 75 is supplied to the coefficient determination circuit 76 and the memory 77.

  The coefficient determination circuit 76 is supplied with the input signal and the noise reduction signal from the blocking circuits 73 and 74. The coefficient determination circuit 76 determines the best coefficient by the least square method, similarly to the coefficient determination in the case of the above-described upconversion. That is, when a predicted value of a target pixel is generated by linear primary combination of a plurality of pixels (pixels of an input signal) and a plurality of coefficients in a block around the target pixel, the corresponding pixel of the predicted value and the noise reduction signal A coefficient that minimizes an error from the value of is determined. The determined coefficient from the coefficient determination circuit 76 is written to the address of the memory 77 specified by the class information.

As shown in FIG. 8A, the blocking circuit 73 forms a block BL1 having a size of (3 × 3), for example, centering on the pixel x ₁ . On the other hand, the blocking circuit 74 forms a block BL11 having a size of (3 × 3) with the pixel y ₁ as the center, as shown in FIG. 8B. Here, the pixels x ₁ and y ₁ are pixels at corresponding positions in the image, the pixel x ₁ includes noise, and y ₁ is noise-reduced. The next block BL2 and BL12, as shown in FIGS. 8C and FIG. 8D, are those boundary block is shifted by one pixel, in which the center pixel x ₂ and y _2, respectively.

In this way, by shifting the block boundaries, a large number of learning data are collected, and the coefficients are determined by the flowchart of FIG. 5 and the processing described above. As a result, for example, when the block BL1 of the input signal shown in FIG. 8A is given, the linear first-order eight pixels values (values of pixels other than the pixel of interest x ₁₎ and 8 coefficients in a block BL1 The predicted value formed by the combination is almost the same value as the pixel value y ₁ not including noise. In this way, the noise of the pixel of interest x ₁ is removed.

  The three-dimensional filter 66b performs noise removal processing in the same manner as the above-described two-dimensional filter 66a except for the classification. Since the motion coefficient K corresponds to the amount of motion, the output signal of the two-dimensional filter 66a is multiplied by the coefficient K, and the output signal of the three-dimensional filter 66b is multiplied by the coefficient (1-K). A signal multiplied by the coefficient is added. That is, when the amount of motion is large, the correlation between the images in the time direction decreases, so that the output weight of the two-dimensional filter 66a is increased.

  Although specific examples of up-conversion and noise reducer have been described, control can be performed using a control signal so as to exhibit other digital signal processing functions. In an example of digital image signal processing using class classification adaptive processing, an interpolation circuit for interpolating pixels thinned out by subsampling, a key signal generation circuit in a digital chroma key device, and the like can be configured.

1 is a block diagram showing a schematic configuration of an embodiment of an integrated circuit according to the present invention. It is a block diagram of an up-conversion circuit which is one of the functions realized by one embodiment of the present invention. It is a basic diagram for demonstrating an up-conversion process. It is a block diagram of an example of the structure for obtaining the coefficient for an up conversion process. It is a flowchart when performing learning for obtaining a prediction coefficient by software processing. It is a block diagram of the noise reducer which is another one of the functions implement | achieved by one Example of this invention. It is a block diagram of an example of the structure for obtaining the coefficient for noise removal processing. It is a basic diagram for demonstrating a noise removal process.

Explanation of symbols

1 LSI
t1, t2 input terminal t3, t4 output terminal t5 control signal input terminals 21a, 21b, 22a, 22b, 23a, 23b, 24 switching circuit

Claims (3)

A selection means capable of switching between a plurality of circuit groups and at least two states is provided in a single integrated circuit, and the selection means can be selected and controlled by an external signal, thereby enabling a class classification adaptive process. An integrated circuit for digital signal processing,
When the selection means takes the first selection state, at least a part of the plurality of circuit groups is set to the first connection state, and performs a first signal processing function by class classification adaptive processing in the first connection state. When the selection means takes the second selection state, at least a part of the plurality of circuit groups is set to a second connection state different from the first connection state, and in this connection state, The second signal processing function is performed by a class classification adaptive process different from the first signal processing function,
At the same time, at least a part of the plurality of circuit groups has a different circuit function depending on the selection state of the selection means, thereby switching the signal processing function of the entire integrated circuit. An integrated circuit for processing a digital signal. The digital signal processing integrated circuit according to claim 1 ,
The first signal processing function is signal processing for resolution compensation by class classification adaptive processing using coefficients previously obtained by learning , and the second signal processing function is class classification adaptive using coefficients previously obtained by learning. An integrated circuit for digital signal processing, which is signal processing for noise removal by processing. The digital signal processing integrated circuit according to claim 1 ,
An integrated circuit for digital signal processing characterized in that two different circuit functions according to the selection state of the selection means are one of a one-dimensional digital filter, a two-dimensional digital filter and a three-dimensional digital filter.

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