JP3724034B2 - Control circuit for production equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control circuit for production equipment to which a safety function is added in a control device used for production equipment such as an injection molding machine.
[0002]
[Prior art]
Conventionally, for example, when a system abnormality occurs during operation of an injection molding machine, the system is restarted by detecting a runaway by a detection circuit such as a watchdog timer and resetting the processor.
[0003]
FIG. 6 shows a block diagram of a control circuit for production equipment having such a conventional general safety function, and FIG. 7 shows a timing chart when the system is abnormal.
[0004]
In FIG. 6, 1 is a processor, 2 is a watchdog timer, 3 is an interface circuit, and FIGS. 7A and 7B show waveforms of respective parts.
[0005]
The operation of the production facility control circuit having the conventional safety function configured as described above will be described below.
[0006]
As shown in FIG. 7A, the processor 1 continues to issue a clear pulse (a) to the watchdog timer 2 every predetermined period Ta. Further, the processor 1 writes data into the data latch circuit 11 of the interface circuit 3, and performs setting of operation and stop of a load such as a hydraulic motor incorporated in the injection molding machine. Clear pulse (a) is not input to watchdog timer 2 even after a certain period Ta due to program runaway, etc., and runaway detection preset in watchdog timer 2 as shown in FIG. When the time Tb is exceeded, the watchdog timer 2 outputs a reset signal (b) and resets the processor 1 through the OR circuit 4A. After the reset is released, the processor 1 starts again from the initial state and restarts the system.
[0007]
[Problems to be solved by the invention]
However, in the configuration of the control circuit for production equipment having the conventional safety function, the system is restarted and returns to normal after resetting with the watchdog timer only by the program runaway, but there is an abnormality such as hardware failure of the processor etc. In some cases, even if the program is operating normally, it becomes a mode that cannot be assumed after system restart depending on the hardware status. There was a possibility. For this reason, the safety | security in the apparatus when a system abnormality generate | occur | produces was requested | required.
[0008]
An object of the present invention is to solve such a conventional problem and to provide a control circuit for production equipment having a safety function which does not damage a mold or the like when a system abnormality occurs in an injection molding machine. is there.
[0009]
[Means for Solving the Problems]
In order to solve this problem, the production facility control circuit according to the present invention is configured to forcibly stop the operation of the facility regardless of the control signal from the processor and to maintain the state.
[0010]
According to the present invention, it is possible to obtain a control circuit for production equipment having a safety function that does not damage a mold or the like when a system abnormality occurs in an injection molding machine.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
The invention according to claim 1 of the present invention is based on the reset holding signal generated by the holding circuit from the first reset signal output from the watchdog timer in the event of a system malfunction due to a program runaway of the processor controlling the equipment or a hardware failure. The forced stop circuit generates a forced stop circuit from the second reset signal that is one of the first reset signal , the reset hold signal, and the third reset signal that resets the processor when the power is turned on while holding the processor in the reset state. The equipment is configured to forcibly stop the equipment by a stop signal and maintain the state. In the equipment of the injection molding machine , the processor is held in the reset state and the load of the hydraulic motor etc. To stop the operation forcibly and maintain its state Ri to prevent a system restart, an effect that it is possible to prevent damage such as molding die.
[0012]
According to a second aspect of the present invention, in the first aspect of the invention, the processor has a watchdog timer therein, and a first reset signal output from the watchdog timer when the system is abnormal and a third at power-on. And a delay circuit that delays the reset signal when the power is turned on and transmits the reset signal to the determination circuit. Have.
[0013]
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a production facility control circuit according to Embodiment 1 of the present invention.
[0014]
The embodiment shown in FIG. 1 has basically the same configuration as that of the conventional technique shown in FIG. 6, and therefore, the same components are denoted by the same reference numerals and detailed description thereof is omitted.
In FIG. 1, the production equipment control circuit includes a processor 1 that outputs an on / off signal for controlling the equipment based on data obtained by detecting the operating state of the equipment based on a preset program; An interface circuit 3 that outputs a device on / off signal that operates equipment based on an on / off signal, and a watchdog timer 2 that outputs a first reset signal a in the event of a system malfunction due to a program runaway or hardware failure of the processor 1 A holding circuit 5 that outputs a reset holding signal c that holds the processor 1 in a reset state by the first reset signal a, a third reset signal that resets the processor 1 when the power is turned on (not shown), and a first reset A second signal comprising any one of the signal a, the reset holding signal c and the third reset signal And a forced stop circuit 6 for outputting a forced stop signal e forcibly stopping the independent equipment and the on-off signal to the interface circuit 3 by the set signal d.
[0015]
The holding circuit 5 holds the first reset signal output from the watchdog timer 2 and includes an inverter 13 and a D flip-flop 14. The forced stop circuit 6 forcibly keeps the load in the stopped state by the held first reset signal, and is composed of AND circuits 15 and 16.
[0016]
FIG. 2 shows a timing chart when the system abnormality occurs in the first embodiment, and corresponds to the waveforms of the respective parts (a) to (e) of FIG. 2, (a) is a first reset signal output from the watchdog timer 2 (hereinafter referred to as a reset signal), and (b) is a signal for detecting the reset signal (a) (hereinafter referred to as a reset detection signal). , (C) is a signal output from the holding circuit 5 (hereinafter referred to as a reset holding signal), (d) is a second reset signal (hereinafter referred to as a system reset signal) input to the reset terminal of the processor 1, ( e) is a signal output from the forced stop circuit 6 (hereinafter referred to as a forced stop signal).
[0017]
The operation of the production facility control circuit of the present embodiment configured as described above will be described below.
[0018]
When the system is abnormal, the watchdog timer 2 outputs the reset signal (a) as “Lo”, and resets the processor 1 by setting the reset terminal of the processor 1 to “Lo” through the OR circuit 4. At the same time, at the rise timing of the reset detection signal (b) obtained by inverting the reset signal (a) by the inverter 13 from “Lo” to “Hi”, the D flip-flop 14 thereafter supplies the reset holding signal (c) to “ "Lo". The reset reset signal (a) is canceled by inputting the held reset holding signal (c) to the processor 1 through the OR circuit 4 with the system reset signal (d) set to “Lo”. The reset state of the processor 1 can be maintained afterwards.
[0019]
When the forced stop circuit 6 makes the equipment operable by setting the output of the AND circuit 15 to “Hi” with respect to the interface circuit 3 and setting the equipment to the stopped state by setting “Lo”, a system error occurs. When the reset holding signal (c) of the output of the D flip-flop 14 is held at “Lo” as described above, the output of the AND circuit 16 becomes “Lo”. Becomes “Lo”, the equipment is forcibly stopped regardless of the data setting of the data latch circuit 11. When the power is turned on, the system reset signal (d) is “Lo” and the output of the AND circuit 16 is “Lo”. Therefore, the equipment can be stopped as in the case of the system abnormality.
[0020]
Conversely, when the system is normal, the system reset signal (d) is “Hi” and the output of the D flip-flop 14 is also “Hi”, so the output of the AND circuit 16 becomes “Hi”. By setting “Hi” to “Hi”, the inputs of the AND circuit 15 both become “Hi”, so that the output of the AND circuit 15 becomes “Hi” and the equipment becomes operable.
[0021]
As described above, according to the present embodiment, when a system abnormality occurs in the injection molding machine, the processor is held in the reset state, the load of the hydraulic motor or the like is forcibly stopped, and the system is restored by holding the state. It is possible to realize a control circuit with a safety function that prevents activation and does not damage the mold.
[0022]
(Embodiment 2)
FIG. 3 is a block diagram showing a configuration of a production facility control circuit according to Embodiment 2 of the present invention.
[0023]
The present embodiment shown in FIG. 3 has basically the same configuration as that of the first embodiment shown in FIG. 1, and therefore, the same components are denoted by the same reference numerals and detailed description thereof is omitted.
[0024]
In FIG. 3, the processor 1 has a watchdog timer 2 inside, and outputs a first reset signal to the inside and outside of the processor 1 when the system is abnormal. The delay circuit 7 delays a third reset signal when the power is turned on for a certain period of time, and includes an integrating circuit including resistors 21a and 21b and a capacitor 22, and inverters 23a and 23b. The discriminating circuit 8 discriminates whether the system is abnormal or when the power is turned on, and comprises an AND circuit 24.
[0025]
FIG. 4 shows a timing chart at the time of occurrence of an abnormality in the present embodiment, and corresponds to the waveforms of the respective parts of FIGS. 4, (a) is a system clock, (b) is a third reset signal at power-on (hereinafter referred to as a power-on reset signal), and (c) is input to the reset terminal of the processor 1 or output from the reset terminal. The first reset signal (hereinafter referred to as a system reset signal), (d) is a power ON reset delay signal, (e) is a discrimination circuit output signal, and (f) is a reset holding signal. FIG. 5 shows a timing chart when the power is turned on in this embodiment.
[0026]
The operation of the production facility control circuit of the present embodiment configured as described above will be described below.
[0027]
Since the reset terminal of the processor 1 is also used as an input / output, the power-on reset signal (b) when the power is turned on needs to be input to the processor 1 using an open collector type element.
[0028]
In FIG. 3, when the power ON reset signal (b) is “Lo”, an open collector type inverter 4a and an inverter 4b are used so that the system reset signal (c) also becomes “Lo”. When the system is abnormal, the reset signal output from the watchdog timer 2 inside the processor 1 resets the inside of the processor 1 and simultaneously resets the external peripheral system by setting the system reset signal (c) to “Lo”. . At this time, the system reset signal (c) is held outside the processor 1 and is input to the processor 1 again. However, when the system reset signal (c) is held, “Lo” is applied both when the system is abnormal and when the power is turned on. Therefore, it is necessary to determine them so that they are not held when the power is turned on. For this reason, the discrimination circuit 8 is provided so that the holding circuit 5 works only when the system is abnormal.
[0029]
The operation when the system is abnormal will be described. As a method for determining when the system is abnormal, the system reset signal (c) becomes “Lo” as described above. At this time, the power ON reset signal (b) has already been turned on. It is “Hi” since it has been inserted, and it is determined that the system is abnormal under these conditions. The power ON reset signal (b) is input to the AND circuit 24 through the inverter 4b and the delay circuit 7. When the other input of the AND circuit 24 is the system reset signal (c), both are “Lo”, so that the discrimination circuit output signal ( e) becomes “Hi”, and is held at “Hi” at the rising timing of the system clock (a) in the D flip-flop 25 of the holding circuit 5, and as a result, again to the processor 1 through the open collector inverter 4 c. The reset signal “Lo” is continuously output.
[0030]
Further, the reset state is maintained even after the reset released from the watchdog timer 2 is released. The operation of the forced stop circuit 6 is the same as that in the first embodiment.
[0031]
Next, the operation when the power is turned on will be described. As described above, the system reset signal (c) and the power ON reset signal (b) are both “Lo” as the determination method when the power is turned on. It is determined that the power is turned on when the condition is met. When the power is turned on, the power ON reset signal (b) becomes “Hi” after “Lo” during the reset period, so that the output of the inverter 4 b becomes “Lo” after “Hi”. On the other hand, the system reset signal (c) also becomes “Hi” after “Lo” during the reset period, but according to the present embodiment, both are input to the AND circuit 24 at “Lo” due to the delay of the inverter 4a. As described above, the reset state may be held. Therefore, after the system reset signal (c) becomes “Hi”, the delay circuit 7 sufficiently delays the signal of the inverter 4b so that the power ON reset delay signal (d) changes from “Hi” to “Lo”. It is possible to prevent a reset from being held when the power is turned on.
[0032]
As described above, according to the present embodiment, the same production equipment control circuit as in the first embodiment can be realized even when the watchdog timer is built in the processor.
[0033]
【The invention's effect】
As described above, the production facility control circuit according to the present invention detects the operation state of the facility based on a preset program and outputs a signal for controlling the facility based on the obtained data, and the occurrence of a system abnormality. A watchdog timer that sometimes outputs a signal that resets the processor, a first reset signal that is output from the watchdog timer, and a holding circuit that holds the processor in a reset state based on the detected signal; An interface circuit for outputting a control signal for operating the equipment based on the control signal, a first reset signal held by the holding circuit, and a state of the second reset signal inputted to the reset terminal of the processor. For the control signal from the processor. If the processor has a watchdog timer inside, the first reset signal output from the watchdog timer when the system is abnormal and when the power is turned on By providing a discriminating circuit that discriminates the state of the system by the third reset signal and a delay circuit that delays the third reset signal at power-on and transmits it to the discriminating circuit, the system can be restarted when a system abnormality occurs For example, if it is used in an injection molding machine or the like, it is possible to obtain a great effect that damage to a mold or the like can be avoided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of a production facility control circuit according to the first embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the production facility control circuit according to the embodiment. FIG. 4 is a block diagram showing the configuration of a production facility control circuit according to the second embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation of the production facility control circuit when the system is abnormal. FIG. 6 is a block diagram showing the configuration of a conventional production equipment control circuit. FIG. 7 shows the operation when the system is abnormal. Timing chart to explain 【Explanation of symbols】
DESCRIPTION OF SYMBOLS 1 Processor 2 Watchdog timer 3 Interface circuit 4 OR circuit 5 Holding circuit 6 Forced stop circuit 7 Delay circuit 8 Discriminating circuit 11 Data latch circuit 12 Output buffer 13 Inverter 14 D flip-flops 15 and 16 AND circuit

Claims (2)

A processor for outputting an ON-OFF signal for controlling the equipment by the data obtained by detecting the operation state of the equipment based on a preset program, device for operating the equipment based on the on-off signal an interface circuit which outputs an on-off signal, and the watchdog timer for outputting a first reset signal to the system abnormality due to program runaway or hardware failure of the processor, the processor in reset by said first reset signal a holding circuit you output a reset hold signal for holding, a third reset signal for resetting the power is turned ON processor, the second consisting of either the first reset signal, the reset hold signal and a third reset signal the O to the interface circuit by the reset signal Off signal consists forced stop circuit that outputs a forced stop signal to forcibly stop the independent facilities,
The system abnormality processor stops the equipment by the forced stop signal holds the reset state by the reset hold signal, production equipment control circuit configured so as to sustain its state.   When the processor has a watchdog timer inside, the system status is determined by the first reset signal output from the watchdog timer when the system is abnormal and the third reset signal when the power is turned on, and when the power is turned on 2. The production facility control circuit according to claim 1, further comprising a delay circuit that delays the third reset signal and transmits the third reset signal to the determination circuit.

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