JP3588139B2 - Interface control device - Google Patents

Description

【００４４】
データ選択ＭＵＸ ４６の出力は、双方向トライステートバッファ５０に接続される。双方向トライステートバッファ５０の双方向入出力ポートが、上記の通りにバッファシステムデータバス（ＢＳＤ ＜１５：０＞） １８０に接続される。双方向トライステートバッファ５０は、バッファシステムデータバス１８０ とインタフェース制御装置３２との間のデータフローの方向を選択的に制御する。双方向トライステートバッファ５０からの単一方向出力が、システムデータ入力低（Ｓｙｓｔｅｍ Ｄａｔａ Ｉｎｐｕｔ Ｌｏｗ）（ＳＤＡＩＬ ＜６：５＞ ） 信号とＳＤＡＩＬ ＜７＞ とによって別々にフリップフロップ５２とフリップフロップ５４とに接続される。双方向トライステートバッファ５０内のデータフローの方向は、制御論理回路５６によって制御される。
【００４５】
図７は、双方向トライステートバッファを制御するための制御論理回路の略図である。図６に示されるように、制御論理回路５８は、ＳＥＬ １３₋ 信号を発生させるために、ＪＰ／ＪＰＬＥＳＳ 信号と ＲＥＡＤ １３₋ 信号との論理積（ＡＮＤ） をとり、このＳＥＬ １３₋ 信号は、構成ジャンパバッファ３９と制御論理回路５６とに与えられる。次に図７を見ると，ＳＥＬ １３₋ 信号が、Ｔｒｉ ₋ Ｏｕｔ 信号を発生させるために、システム最下位ビット（Ｓｙｓｔｅｍ Ｌｅａｓｔ Ｓｉｇｎｉｆｉｃａｎｔ Ｂｉｔ）（ＳＹＳ₋ ＬＳＢ ₋ ） 信号の反転と否定論理積（ＮＡＮＤ）され、Ｔｒｉ ₋ Ｏｕｔ 信号は、第１の論理状態（例えば論理「１」）においてインタフェース制御装置３２からＢＳＤ バス１８０ へデータが流れることを命令し、一方、これとは逆に、第２の論理状態（例えば論理「０」）においてＢＳＤ バス１８０ からインタフェース制御装置３２へデータが流れることを命令する。ＳＹＳ ₋ ＬＳＢ ₋ 信号は内部ＦＩＦＯ又はレジスタ（図示されていない）によって与えられ、修飾子である。従って、データ選択ＭＵＸ ４６は、ＩＤメモリ３６か、シフトレジスタ／カウンタ４８か、ＳＤＯＨＬ バスかのいずれかからＢＳＤ ライン１８０ 上にデータを出力するように選択される。
【００４６】
ライン２３６ 上のハードウェアリセット（Ｈａｒｄｗａｒｅ Ｒｅｓｅｔ）信号と、ライン２３７ 上のＪＰ／ＪＰＬＥＳＳ 信号と、２０ ＭＨｚクロックとが、無ジャンパ状態機械（ｊｕｍｐｅｒｌｅｓｓ ｓｔａｔｅ ｍａｃｈｉｎｅ）６０の第１と第２と第３の入力に与えられる。イーサネットインタフェースモジュール２６は、クロック１１８ （図２）からのライン２３８ 上の２０ ＭＨｚクロック信号に基づいて動作する。無ジャンパ状態機械６０の第１の出力信号であるイネーブルカウンタ（Ｅｎａｂｌｅ Ｃｏｕｎｔｅｒ）（ＥＮ ＣＮＴＲ） 信号が、シフトレジスタ／カウンタ４８にシフトレジスタ又はカウンタのどちらとして動作するかを命令するために、ライン２４４ 上をシフトレジスタ／カウンタ４８に与えられる。これに加えて、シフトレジスタクロック（ｓｈｉｆｔ ｒｅｇｉｓｔｅｒ ｃｌｏｃｋ）（ＳＲＣＬＫ） 信号も、シフトレジスタ／カウンタ４８内でデータをシフトイン（ｓｈｉｆｔ ｉｎ）するために与えられる。無ジャンパ状態機械６０は、その第２の出力からハードウェア被制御データイン（ｈａｒｄｗａｒｅ ｃｏｎｔｒｏｌｌｅｄ ｄａｔａ ｉｎ）（ＨＡＲＤ ＤＩ）信号をライン２３９ を通してＩＤメモリ制御ＭＵＸ ６２に与え、ＩＤメモリ制御ＭＵＸ ６２は、ＩＤメモリ３６にライン２００ を通して選択的にＨＡＲＤ ＤＩ 信号を与える。無ジャンパ状態機械６０は、その第３の出力からハードウェア被制御シフトクロック（ｈａｒｄｗａｒｅ ｃｏｎｔｒｏｌｌｅｄ ｓｈｉｆｔ ｃｌｏｃｋ）（ＨＡＲＤ ＳＫ）信号をライン２４１ を通してＩＤメモリ制御ＭＵＸ ６２に与え、ＩＤメモリ制御ＭＵＸ ６２は、ＩＤメモリ３６にライン２０４ を通して選択的にＨＡＲＤ ＳＫ 信号を与える。無ジャンパ状態機械６０は、その第４の出力からハードウェア被制御チップ選択（ｈａｒｄｗａｒｅ ｃｏｎｔｒｏｌｌｅｄ ｃｈｉｐ ｓｅｌｅｃｔ）（ＨＡＲＤ ＣＳ）信号をライン２４２ を通してＩＤメモリ制御ＭＵＸ ６２に与え、ＩＤメモリ制御ＭＵＸ ６２は、ＩＤメモリ３６にライン２０２ を通して選択的にＨＡＲＤ ＣＳ 信号を与える。無ジャンパ状態機械６０は、その第５の出力からＭＵＸ ハードウェア選択（ＭＵＸ ｈａｒｄｗａｒｅ ｓｅｌｅｃｔ）（ＭＵＸＨＷ）信号をライン２４３ を通してＩＤメモリＭＵＸ 制御回路６９に与える。
【００４７】
図８は、図５に示されたＩＤメモリＭＵＸ 制御回路の略図である。ＭＵＸＨＷ 制御信号がライン２４３ 上をＩＤメモリＭＵＸ 制御回路６９に与えられ、ＩＤメモリＭＵＸ 制御回路６９では、このＭＵＸＨＷ 信号が、ＳＥＬ ₋ ＭＵＸ 信号を形成するために、反転されてＪＰ／ＪＰＬＥＳＳ 信号と論理積される。再び図５を参照すると、無ジャンパ状態機械６０からＩＤメモリ３６への信号と、フリップフロップ５２、５４からの信号との何方か一方を選択するように、ＳＥＬ ₋ ＭＵＸ 信号がライン２４６ 上をＩＤメモリ制御ＭＵＸ ６２に与えられる。
【００４８】
ソフトウェア被制御チップ選択信号と、ソフトウェア被制御シフトクロック信号と、ソフトウェア被制御データイン信号とが、フリップフロップ５２、５４に与えられる。特に、ＳＤＡＩＬ ＜６：５＞ とＳＤＡＩＬ ＜７＞ とが、上記のようにバッファシステムデータバス１８０ からフリップフロップ５２、５４に別々に与えられる。更に、ＷＲＩＴＥ １０ 信号とＷＲＩＴＥ １１ 信号とがフリップフロップ５２、５４に別々に与えられる。
【００４９】
シフトレジスタ／カウンタ４８のビット２〜０は、復号器選択ＭＵＸ ６４の第１の入力にＩ／ＯＳＥＬ ＜２：０＞として接続される。シフトレジスタ／カウンタ４８のビット５〜３は、復号器選択ＭＵＸ ６４の第２の入力に信号ＭＳＥＬ ＜２：０＞として与えられる。ジャンパによって定義されるＩ／ＯＳＥＬ ＜２：０＞命令は、ライン２１６ を通して、復号器選択ＭＵＸ ６４の第３の入力に与えられる。復号器選択ＭＵＸ ６４の第４の入力は、双方向トライステートバッファ７２に接続される。双方向トライステートバッファ７２の双方向ポートは、ジャンパによって定義されるＭＳＥＬ ＜２：０＞命令を入力として搬送するか又は割込み要求（ＩＲＱ ＜３：０＞） 信号を出力として搬送する信号ラインに接続される。双方向トライステートバッファ７２への入力は、割込み要求復号器７０の第１の出力である。割込み要求復号器７０の第２の出力は、割込み要求０である。シフトレジスタ／カウンタ４８のビット７〜６も、割込み要求復号器７０の２つの入力に与えられる。双方向トライステートバッファ７２は、ジャンパ復号器４４からのライン２３７ 上のＪＰ／ＪＰＬＥＳＳ 命令によって制御される。復号器選択ＭＵＸ ６４の出力は、メモリアドレス復号器６６とＩ／Ｏ アドレス復号器６８とに接続される。メモリアドレス復号器６６の出力とＩ／Ｏ アドレス復号器６８の出力は、ＳＲＡＭ １３８ （図３）に接続される。復号器選択ＭＵＸ ６４は、ジャンパ復号器４４からのＪＰ／ＪＰＬＥＳＳ 命令によっても制御される。復号器選択ＭＵＸ ６４は、論理１のＪＰ／ＪＰＬＥＳＳ 命令又は論理０のＪＰ／ＪＰＬＥＳＳ 命令に各々に応答して、シフトレジスタ／カウンタ４８又はジャンパからＭＳＥＬ ＜２：０＞を出力することと、Ｉ／ＯＳＥＬ ＜２：０＞を出力することとの間で切り替えられる。
【００５０】
次に、上記で定義されたハードウェアに関して、イーサネットインタフェースモジュール２６の動作を、図９ 〜１２を参照して説明する。図９は、システム電源投入時、又は、Ｓｙｓｔｅｍ Ｈａｒｄｗａｒｅ Ｒｅｓｅｔ 命令が送り出される他のいずれかの時点における、ＩＤメモリからシフトレジスタ／カウンタへの構成バイトの読み取りと、メモリアドレスのコンフリクトの解消とのフローチャートである。システム電源投入時（ステップ３００ ）に、ＣＰＵ １２は、イーサネットインタフェースモジュール２６を含むＡＴバス１４上の各モジュールに対して、Ｓｙｓｔｅｍ Ｈａｒｄｗａｒｅ Ｒｅｓｅｔ 命令を開始命令又は初期設定命令として送り出す。リセット後に、ＣＰＵ １２は、最初のＡＴバス所有者となる。更に、例えば、キーボード２５上のコントロール（Ｃｔｒｌ）キーとＡＬＴ キーと削除（Ｄｅｌ） キーとを３つ同時にユーザが押すことによって、通常のシステム動作中にＨａｒｄｗａｒｅ Ｒｅｓｅｔ命令が送り出されることも可能である。以下の説明は、典型的な目的のためにシステム電源投入時に送り出されるハードウェアリセットに関して、システムの動作を説明する。しかし、本発明はこれに限定されない。
【００５１】
ハードウェアリセット時に、ジャンパ復号器４４（図５）からのＪＰ／ＪＰＬＥＳＳ 信号が示すシステム構成が有ジャンパシステム構成と無ジャンパシステム構成との何方であるかを、無ジャンバ状態機械６０が判定する。無ジャンパモジュールとしてのイーサネットインタフェースモジュール２６の動作を、先ず最初に次で説明する。
【００５２】
システムが無ジャンパシステムである場合には、無ジャンバ状態機械６０（図５）が、ライン２０２ （図４）上のＣｈｉｐ Ｓｅｌｅｃｔ 信号を高状態にセットすることによってＩＤメモリ制御ＭＵＸ ６２にＩＤメモリ３６を選択するように命令する。ライン２０４ 上のＳｈｉｆｔ Ｃｌｏｃｋ 命令（図４）が、直列データ出力２０６ 上をＩＤメモリ３６からシフトレジスタ／カウンタ４８にデータをシフトするようにセットされる。更に、シフトレジスタ／カウンタ４８にシフトレジスタとして動作することとＩＤメモリ３６からの直列データ出力２０６ をクロックイン（ｃｌｏｃｋ ｉｎ）することとを命令するために、無ジャンバ状態機械６０が、ライン２４４ （図５）を通してシフトレジスタ／カウンタ４８に命令を送る。
【００５３】
ＩＤメモリ３６の位置Ｏｘ１１から構成バイトを読み取って、それをシフトレジスタ／カウンタ４８内にロードするために、無ジャンバ状態機械６０は適切な信号を発生させる（ステップ ３０２）。上記のように、ビット５〜３はメモリ基底アドレスを決定する（ステップ ３０４）。図１０は、ＡＴバス用のメモリ基底アドレスのマップである。メモリアドレスは０（００ ００００ Ｈｅｘ）〜１６３８４ Ｋ （ＦＦ ＦＦＦＦ Ｈｅｘ）の範囲内である。実際にはアドレスは１６３８４ Ｋ マイナス１であるが、説明を分かり易くするために、この−１は、接尾辞「Ｋ 」を有するアドレスから省かれる。このアドレス範囲内で、複数の部分範囲（ｓｕｂｒａｎｇｅ）がプラットフォームメモリとＢＩ０Ｓとのために割り当てられるか又は確保される。アドレス ０ （００ ００００ Ｈｅｘ）− ５１２ Ｋ （０６ ＦＦＦＦ Ｈｅｘ）が、プラットフォームメモリ用に確保された位置である。アドレス ５１２ Ｋ （０７ ００００ Ｈｅｘ）− ６４０Ｋ （０９ ＦＦＦＦ Ｈｅｘ） が、プラットフォームメモリ用のアドレス範囲である。アドレス範囲 １０００００ （Ｈｅｘ） − ＦＤ ＦＦＦＦ （Ｈｅｘ）が、スロットメモリ用に確保される。このアドレス範囲内に、イーサネットインタフェースモジュール２６がＣ４０００−ＤＦＦＦＦ のアドレス範囲を有することが好ましい。基底アドレスビットに割り当てられるアドレスが次の表ＩＩに示されている。

【００５４】
再び図９を参照すると、この図に示されるように、イーサネットインタフェースモジュール２６は、ＩＤメモリ３６から構成バイトをロードする。ＩＤメモリ３６から構成バイトを読み取る過程は、システム電源投入時に開始し、上記のシステムＢＩＯＳ立ち上げ時の初期設定と検査とに並行している。構成バイトの並行読取りは、ＢＩＯＳが有効ブートＲＯＭ を求めてＲＯＭ 位置を走査することを可能にする。システムが適正に立ち上がる場合（ステップ ３０６）には、ブートＲＯＭ 初期設定コードがそのリソースを初期化し、所望の割込みベクトルを置換し（ステップ ３０７）、システムコントロールをシステムＢＩＯＳに戻し、その初期設定を完了する（ステップ ３０８）。
【００５５】
一方、システムが適正に立ち上がらない場合には、コンピュータ１０内のイーサネットインタフェースモジュール２６と別の増設モジュールとの間でメモリアドレスのコンフリクトがあると見なされる（ステップ ３０６）。メモリコンフリクトがある場合には、システム電源投入中にＣＰＵ １２が停止する。このコンフリクトを解消するために、イーサネットインタフェースモジュール２６が、コンピュータ１０から取り外され（ステップ ３１０）、第２のコンピュータシステム内にインストールされる（ステップ ３１２）。この第２のシステムは、メモリ基底アドレスのコンフリクトの可能性を低減させることによってイーサネットインタフェースモジュール２６が適正に動作するかどうかを判定するために使用される。この第２のシステムは、第１のシステムと同一の基本構成を有するが、増設モジュールを全く含まないことが好ましく、これによって、イーサネットインタフェースモジュール２６と増設モジュールとの間のメモリコンフリクトを排除する。これに加えて、無ジャッパモードでは、下記で説明されるように、異なるメモリ基底アドレスによってＩＤメモリ３６を再プログラムするために第２のシステムが使用される。イーサネットインタフェースモジュール２６を第２のシステム内に挿入した後に、第２のシステムが電源投入される。第２のシステムが適正に立ち上がった場合（ステップ ３１４）には、イーサネットインタフェースモジュール２６は作動中であり、第１のシステムでの問題点はメモリコンフリクトであったと見なされる。従って、このコンフリクトを排除するために、イーサネットインタフェースモジュール２６のメモリ基底アドレス位置を再割当てすることが必要である（ステップ ３１６）。
【００５６】
有ジャンパモードでは、ジャンパワイヤを物理的に付加又は変更することによってイーサネットインタフェースモジュール２６のメモリ基底構成ジャンパ１８９ （図４）を変更することによって、メモリ基底アドレス位置が再割当てされる。これとは対照的に、無ジャンパモードでは、好ましくはＩＤメモリ３６のアドレス ０Ｘ １３において構成バイトを再プログラムすることによって、メモリ基底アドレス位置が変更される。例えば、構成バイトのビット５〜３内に最初に格納されたイーサネットインタフェースモジュール２６のメモリ基底アドレス位置が０００ であるとすると、この値０００ に対応するアドレス範囲は、上記の表ＩＩに示されるように、範囲 ０ＸＣ４０００ （Ｈｅｘ）− ００ＸＣ７ＦＦＦ （Ｈｅｘ）である。アドレスコンフリクトがある場合には、この範囲内のアドレスに応答することによって、イーサネットインタフェースモジュール２６とＡＴバス１４上の第２の増設モジュールとの両方が作動する。イーサネットインタフェースモジュール２６のメモリ基底アドレスは、構成バイトのビット５〜３を変更することによって再割当てされる。例えば、０００ から００１ にビット５〜３を増分することによって、これに対応してメモリ基底アドレス範囲が、表ＩＩに示されるような ０ＸＣ８０００ （Ｈｅｘ） − ０ＸＣＢＦＦＦ （Ｈｅｘ）の範囲に増分する。
【００５７】
ＩＤメモリ３６を再プログラムするために、ＣＰＵ １２は最初に、構成バイトの現在状態を知るために、その構成バイトを読み取らなければならない。ＣＰＵ １２は、ＩＤメモリ３６のメモリ位置 ０Ｘ１３ における構成バイトのアドレスのためのメモリ読取りの要求を送り出す。ＣＰＵ １２は、データアドレスと要求命令をシステムデータバスを通してＩＤメモリ３６に通信するために、Ｉ／Ｏ 読取り（ＩＯＲバー） 信号をシステムデータバストランシーバ４０に送る。インタフェース制御装置３２は、ＩＤメモリ３６にアドレスとシフト選択命令とシフトクロック命令とを与えるために、システムデータバス１８０ からフリップフロップ５２、５４にデータを供給するようにインタフェース制御装置３２の双方向トライステートバッファ５０（図５）に命令する。ＩＤメモリ３６は、そのデータ出力ポートから、要求された構成バイトをデータ選択ＭＵＸ ４６に供給し、データ選択ＭＵＸ ４６は、バッファシステムデータバス１８０ 上にそのデータを出力するように、イーサネットインタフェースモジール２６によって命令される。インタフェース制御装置３２は、バッファシステムデータバス１８０ からＡＴバス１４を経由してシステムデータバス１０６ とＣＰＵ １２とにデータを供給することをシステムデータバストランシーバ４０に命令し、更にシステムデータバストランシーバ４０をディスエーブルにする。その後で、ＣＰＵ １２は構成バイトのビット５〜３を増分し、それによって新たなメモリ基底アドレスを発生させ、更にその後で、上記の仕方で、位置０Ｘ１３においてＩＤメモリ３６の中にその新たな構成バイトを書き込むことをイーサネットインタフェースモジュール２６に命令する。ＣＰＵ １２によるＩＤメモリ３６からの構成バイトの読取りと同様の仕方で、ＣＰＵ は、システムデータバス１０６ を通してＩＤメモリ３６に適切な命令を与えることによって、増分された構成バイトを上記０Ｘ１３メモリ位置に書き込むことを、イーサネットインタフェースモジュール２６に命令する。
【００５８】
再び図９を参照すると、この図に示されるように、新たなメモリ基底アドレスを有する構成バイトによってイーサネットインタフェースモジュール２６が再プログラムされ終わった後に、そのイーサネットインタフェースモジュール２６が第１のコンピュータシステム内にインストールされ（ステップ ３１７）、この第１のシステムが、ステップ ３００を繰り返すことによって再び立ち上げられる。この第１のシステムはその立上げルーチンを完了し、ステップ ３０２に関して上記で説明された通りに、ＩＤメモリ３６からシフトレジスタ／カウンタ４８の中に構成バイトをロードする。復号器６６、６８を使用するインタフェース制御装置３２は、その構成バイトをステップ ３０４において復号する。そのシステムがステップ ３０６で適正に立ち上がる場合には、ステップ ３１６で行われたメモリ位置の再割り当てが適正であり、イーサネットインタフェースモジュール２６は上記で説明したようにステップ ３０７に進む。一方、再構成されたイーサネットインタフェースモジュールがステップ ３０６で適正に立ち上がらない場合には、第１のシステムからそのイーサネットインタフェースモジュールを取り外し（ステップ ３１０）、第２のシステムでそのモジュールをテストする（ステップ ３１２）という過程が繰り返される。
【００５９】
第２のシステムがステップ ３１４で適正に立ち上がらない場合には、ステップ ３１６で説明した通りに、そのメモリの構成バイトが再構成される（ステップ ３１８）。ステップ ３１４で第２のシステムの立ち上げが再び試みられる。或いは、ステップ ３１８でメモリ位置を再構成する代わりに、イーサネットインタフェースモジュールが別のシステムに挿入され（ステップ ３２０）、この別のシステムが、ステップ ３１４に関して上記で説明したように、再び立ち上げられることも可能である。
【００６０】
全てのメモリ基底アドレスコンフリクトを除去するためにイーサネットインタフェースモジュール２６が再構成された後で、Ｉ／Ｏ 基底アドレスのコンフリクトがあるかどうかが判定される。概要を説明すると、そのシステムが立ち上がった時に、全てのメモリ基底アドレスコンフリクトが上記のように解消されているならば、そのシステムは、イーサネットインタフェースモジュール２６上の幾つかの予め決められたレジスタ位置から内容を読み取ることと、これらの内容をその期待値と比較することとによって、Ｉ／Ｏ 基底アドレスを検査する。別の実施例では、イーサネットインタフェースモジュールはブートメモリを含まない。この実施例では、コンフリクトが発生する可能性があるメモリがイーサネットインタフェースモジュール上にないので、メモリコンフリクトを解消することは不必要である。上記比較が一致を示す場合には、Ｉ／Ｏ 基底アドレスコンフリクトは存在しない。一方、システムは、上記比較が一致を示さない場合にはコンフリクトがあると見なす。この時には、システムは、予め決められたレジスタ位置からダミー読取り（ｄｕｍｍｙ ｒｅａｄ）を行う。これに応答して、イーサネットインタフェースモジュール２６はそのＩ／Ｏ 基底アドレスを増分する。システムは、新たなアドレスにおけるレジスタ位置の内容を読み取って比較し、再びコンフリクトがあるかどうかを判定する。コンフリクトが検出されなくなるまで、システムはこの過程を繰り返す。
【００６１】
次に、ＡＴバス１４に関するＩ／Ｏ アドレス基底を示す図１１を参照して、Ｉ／Ｏ アドレス指定を説明する。このＩ／Ｏ アドレスは、０ （００００ Ｈｅｘ）から ６４ Ｋ （ＦＦＦＦ Ｈｅｘ）の範囲である。このアドレス範囲内では、各々の１ Ｋ 範囲は２つの部分範囲に分けられる。第１の部分範囲はメモリの下位の２５６ バイトであり、割込み制御装置やＤＭＡ 制御装置のようなＩ／Ｏ プラットフォームリソース用に確保される。第２の部分範囲は残りの上位の７６８ バイトであり、これらのバイトは汎用Ｉ／Ｏ 従属モジュール用に使用可能である。
【００６２】
下記で説明される通りの好ましい実施例では、イーサネットインタフェースモジュール２６は、上記第２の部分範囲内にある ０ｘ２６０ （Ｈｅｘ）〜 ０ｘ３ＦＦ （Ｈｅｘ）のＩ／Ｏ アドレス範囲を有する。上記のように、構成バイトのビット２〜０（Ｉ／ＯＳＥＬ ＜２：０＞とも呼ばれる）は、Ｉ／Ｏ 基底アドレスを決定する。表ＩＩＩ は、 ０ｘ２６０ （Ｈｅｘ）〜 ０ｘ３ＦＦ （Ｈｅｘ）のアドレス範囲内の構成バイトに関するＩ／Ｏ アドレス復号を示す。

【００６３】
次に図１２を参照すると、この図では、Ｉ／Ｏ 基底アドレスコンフリクトルーチンの過程を説明している。この段階では、メモリ基底アドレスコンフリクトは、図９〜１０において上記で説明したように、既に解消され終わっていると見なされる。（或いは、イーサネットインタフェースモジュールがブートメモリを持たない別の実施例では、上記のようにメモリコンフリクトを解消することは不必要である。）コンピュータが立ち上げられ、図９のステップ３００ に関して上記で説明されたように初期設定ルーチンを行う（ステップ ３３０）。インタフェース制御装置３２は、図９に関して上記で説明されたステップ３０２ と同様の仕方で、ＩＤメモリ３６からシフトレジスタ／カウンタ４８の中に構成バイトをロードする（ステップ ３３２）。この読取りの完了時に、シフトレジスタ／カウンタ４８は、無シャンパ状態機械６０によってカウンタモードにセットされる。このモードでは、イーサネットインタフェースモジュール２６のＩ／Ｏ 基底アドレスを決定する構成バイトのビット２〜０だけが、カウンタによって増分される。構成バイトの残りのバイトは無変更のままに保たれる。インタフェース制御装置３２は、図９のステップ ３０４に関して説明された仕方と同様の仕方で、その構成バイトをＩ／Ｏ 基底アドレスとメモリ基底アドレスと割込みの形に復号する（ステップ ３３４）。これに加えて、イーサネットインタフェースモジュール２６内のレジスタ中の「汚染ビット（ｄｉｒｔｙ ｂｉｔ） 」が、その特殊セルのレジスタ／カウンタモードの監視のために割り当てられる。その後で、ＣＰＵ １２が初期範囲内でメモリから読み取る（ステップ ３３６）。更に明確に言えば、ＣＰＵ １２は、インタフェース制御装置３２の８つのレジスタの内容を読み取るために、そのＩ／Ｏ プログラムに入る。各レジスタが８バイトを有することが好ましい。８つのレジスタの読み取りは、単に一例として示したにすぎない。本発明は、８つのレジスタだけを読み取ることには限定されない。コンフリクトがあるかどうかを判定するためにＣＰＵ １２によって読み取られるレジスタ位置内に記憶された同じ値を、ＡＴバス１４上の２つの異なる増設モジュールが偶然の一致から有することがないという所期の見込みを満たすように、ソフトウェアプログラマーは、必要に応じた数のレジスタを読み取ることが可能である。
【００６４】
システム電源投入時に、インタフェース制御装置３２の８つのレジスタが、ハードディスク１６上に記録されたユーティリティプログラムの一部として、モジュール識別子又は「カンパニーコード（ｃｏｍｐａｎｙ ｃｏｄｅ）」としても記憶される予め決められた値にセットされる。モジュール識別子は、当該モジュールをＡＴバス１４上の他のモジュールに対して一意に識別することが好ましい。このモジュール識別子は、イーサネットインタフェースモジュール２６の最初の８つのレジスタの中に記憶された初期値であることが好ましい。これら８つのレジスタをＣＰＵ １２が読み取った後に、ＣＰＵ １２はソフトウェアユーティリティを実行し、このソフトウェアユーティリティは、ハードディスク１６からモジュール識別子を読み取り、この識別子を最初の８つのレジスタからの読取り値と比較する（ステップ ３３８）。ＣＰＵ １２は、このモジュール識別子の値に上記読取り値が一致することを期待するので、これらの２つの値の間の差異をＩ／Ｏ 基底アドレスコンフリクトと解釈する。読取り値とモジュール識別子との間に一致がある時（ステップ ３４０）には、ＣＰＵ １２は、この一致を、イーサネットインタフェースモジュール２６とＡＴバス１４上の他のモジュールとの間にＩ／Ｏ 基底アドレスコンフリクトが存在しないことと解釈すると共に、イーサネットインタフェースモジュール２６のための固有のＩ／Ｏ 基底アドレスをそのＣＰＵ １２が発見したと解釈する（ステップ ３４２）。
【００６５】
一方、ＣＰＵ １２によって読み取られた上記８つのレジスタの内容が予想値と相違する場合（ ステップ ３４０） には、システムは、この不一致を、Ｉ／Ｏ 基底アドレスのコンフリクトと解釈するか、又は、イーサネットインタフェースモジュール２６が、そのＣＰＵ １２が読み取ったばかりのＩ／Ｏ アドレスにはないということと解釈する。システムは、ＡＴバス１４上に与えられるデータを無視することによってイーサネットモジュール２６の存在を無視するが、ソフトウェアユーティリティは、予め決められたメモリ位置からの読取りを試みることによって続行する（ステップ ３４４）。この予め決められたメモリ位置は、アドレス ０Ｘ１２ （Ｈｅｘ） にあることが好ましい。ＣＰＵ １２が幾つかタイプの記憶装置に書込みを行おうとする場合に、イーサネットインタフェースモジュール２６が、コンフリクトを生じるアドレス指定によって物理的に損傷を与えられる可能性があるので、読取りが好ましい。シフトレジスタ／カウンタ４８がカウンタモード用にセットされ、且つ、何が実際に読み取られているかということをＣＰＵ １２が関知しないので、この読取りは、「ダミー読取り（ｄｕｍｍｙ ｒａｅｄ）」である。カウンタモードでは、ダミー読取りが行われる毎に、シフトレジスタ／カウンタ４８がビット２〜０の値を１ずつ増分し、それによって、Ｉ／Ｏ 基底アドレスを、表ＩＩＩ に定義されているようなその次のアドレス範囲にジャンプさせる。初期Ｉ／Ｏ 基底アドレス範囲は、値 １１１を有する構成バイトのビット２〜０によって定義される ０Ｘ３００ （Ｈｅｘ） 〜 ０Ｘ３１Ｆ （Ｈｅｘ）に設定されることが好ましい。メモリ位置 ０Ｘ１２ からの読取りによってカウンタが増分される時に、構成バイトのビット２〜０が、０Ｘ２６０ （Ｈｅｘ） 〜 ０Ｘ２７Ｆ （Ｈｅｘ）の新たなアドレス範囲に対応する ０００の値に変化する。ユーティリティプログラムは、シフトレジスタ／カウンタ４８がその次の基底Ｉ／Ｏ アドレスにカウントアップ（ｃｏｕｎｔ ｕｐ）する毎に、適正なモジュール識別子を求めてインタフェース制御装置３２を読み取る。このことは、コンフリクトを起こさないＩ／Ｏ 基底アドレスにイーサネットインタフェースモジュール２６がそのモジュール自体を動的に再構成することを可能にする。しかし、７回目の増分の後で、ビット２〜０は値 １１１に戻る。８回目の上記メモリ読取りの後では、システム内にはイーサネットインタフェースモジュール２６が存在しないか、又は、Ｉ／Ｏ 基底アドレスは全て使用不可能である。ＣＰＵ １２は、読み取られているメモリの範囲内にモジュール位置があるかどうかを判定する（ステップ ３４６）。モジュール位置が上記メモリ範囲内にない場合には、その構成バイトの値は増分（又はカウント）されず、システムはＩ／Ｏ 基底アドレスを増分し（ステップ ３５３）、その増分されたアドレスにおけるレジスタを読み取り（ステップ ３４８）、読取り値を期待値と比較するためにステップ ３３８にループバック（ｌｏｏｐ ｂａｃｋ） する。ステップ ３４０で一致が得られない時には、ＣＰＵ １２はステップ ３４４にループバックする。一致が得られた時には、ＣＰＵ １２はステップ ３４２にループバックする。ＣＰＵ １２は、予め決められたアドレスに書込み命令を送り、インタフェース制御装置３２がシフトレジスタ／カウンタ４８をカウントモードにセットして、ユーザモード（ｕｓｅｒ ｍｏｄｅ） に切り替え、必要に応じてユーザがシステム側からＩＤメモリにアクセスすることを可能にする。
【００６６】
一方、イーサネットインタフェースモジュールのアドレスがステップ ３４６で読み取られたメモリの範囲内にある場合には、ＣＰＵ １２が、それが上記範囲の最後の増分であるかどうかを判定し（ステップ ３５０）、そうであるならば、Ｉ／Ｏ 基底アドレス範囲スロットは全て使用不可能であるか、又は、システム内にはイーサネットインタフェースモジュール２６がインストールされていない（ステップ ３５４）。一方、メモリ読取りがそのメモリ範囲の最終メモリ増分でない場合には、制御装置チップ３２は、シフトレジスタ／カウンタ４８のビット２〜０を増加させることによって、イーサネットインタフェースモジュール２６のＩ／Ｏ 基底アドレスを増分する（ステップ ３５２）。ＣＰＵ はＩ／Ｏ 基底アドレスを増分し（ステップ ３５３）、その後で、その増分されたＩ／Ｏ 基底アドレスにおいて８つのレジスタから読み取る（ステップ ３４８）。ＣＰＵ １２は、ステップ ３３８における読取り値と期待値との比較にループバックする。
【００６７】
アドレス０Ｘ１２への不慮の書込みからシフトレジスタ／カウンタ４８内の構成バイトを誤って変更してしまうことを防止するために、ソフトウェア機能抑止が備えられる。データリンクレジスタ内のＩ／Ｏ 基底アンロックビット（Ｉ／Ｏ ｂａｓｅ ｕｎｌｏｃｋ ｂｉｔ） を０にセットすることによって、シフトレジスタ／カウンタ４８が、システムハードウェアリセットが再び送り出されるまで、ディスエーブルにされる。このリセット命令によって、上記アンロックビットが１にセットされ、コンフリクトを起こさないＩ／Ｏ 基底アドレスにイーサネットインタフェースモジュール２６がそのモジュール自体を動的に再構成することを可能にする。
【００６８】
Ｉ／Ｏ アドレスのコンフリクトが解消されると、上記ソフトウェアは初期設定ルーチンを続行することが可能である。イーサネットインタフェースモジュール２６は、所謂「汚染ビット」をセット／リセットすることによって、シフトレジスタ／カウンタ４８をレジスタモードに設定し直す。その直後に、上記ユーティリティプログラムは、シフトレジスタ／カウンタ４８から新たな構成バイトを読み取って、新たな基底アドレスによってＩＤメモリ３６内に格納された構成バイトを再プログラムすることが可能である。
【００６９】
さて、Ｉ／Ｏ アドレスプログラムを終了した後に、割込みを説明する。上記のように、ビット７〜６は、割込みライン構成だけに使用される。割込み信号は、ＣＰＵ １２による割込みサービスを増設カードが要求することを可能にする。これらのビットは、イーサネットインタフェースモジュール２６のホストインタフェース側で使用可能な４つの割込みラインのいずれか１つを選択するようにプログラム可能である。ユーザは、システムユーザに使用可能な４つのシステム割込みライン（割込み０〜３）の任意のセットに対して上記割込みラインを接続する任意選択権を有する。上記ユーティリティは割込み構成をテストし、コンフリクトがある場合には、その次の使用可能な割込みオプションによってＩＤメモリ３６を再プログラムし、システムを再立ち上げし、構成を再テストする。
【００７０】
次表ＩＶは割込みビット定義のリストである。

【００７１】
メモリ基底アドレスのコンフリクトと、Ｉ／Ｏ 基底アドレスのコンフリクトと、割込みのコンフリクトとを解消するためにＩＤメモリ３６が再プログラムされた後には、構成バイトの更に別の再プログラミングは不要である。こうして構成されたコンピュータ１０を引き続いて使用する際には、コンフリクトは発生しないだろう。
【００７２】
以上のように本発明が説明され、その好ましい実施例が説明されたが、他の変更と応用とが当業者にとって見い出されることが予想される。従って、本明細書の特許請求の範囲によってのみ本発明が限定されることが意図されている。
【００７３】
【発明の効果】
以上説明したように、本発明によれば、増設モジュールのメモリアドレスとＩ／Ｏアドレスとがジャンパ無しで変更されるとともに、その変更におけるステップが自動化され、ステップ数も減少する、という効果がある。
【図面の簡単な説明】
【図１】本発明の原理によるコンピュータを示す説明図である。
【図２】図１に示されたコンピュータのためのイーサネットインタフェースモジュールの機能ブロック図である。
【図３】図２に示されたインタフェース制御装置の機能ブロック図である。
【図４】図１に示されたコンピュータのためのイーサネットインタフェースモジュールの特定の実施例の機能ブロック図である。
【図５】図４に示されたインタフェース制御装置のアドレス復号回路と構成バイト処理回路との機能ブロック図である。
【図６】データ選択ＭＵＸ によってバッファシステムデータバスに与えられるデータを制御するための制御論理回路の略図である。
【図７】双方向トライステートバッファを制御するための制御論理回路の略図である。
【図８】図５に示されるＩＤメモリＭＵＸ 制御回路の略図である。
【図９】システム電源投入時における、又はＳｙｓｔｅｍ Ｈａｒｄｗａｒｅ Ｒｅｓｅｔ 命令が送り出されるその他の時点における、ＩＤメモリからシフトレジスタ／カウンタへの構成バイトの読取りと、ブートメモリのコンフリクトの解消とのフローチャートである。
【図１０】ＡＴバス用のメモリ基底アドレスのマップである。
【図１１】ＡＴバス用のＩ／Ｄ 基底アドレスのマップである。
【図１２】図４に示されたイーサネットインタフェースモジュールのＩ／Ｏ 基底アドレスを再構成する際に使用される手順を示すフローチャートである。
【符号の説明】
１０…コンピュータ
１２…中央処理装置モジュール
１４…ＡＴバス
１６…ハードディスク
１８…フロッピーディスク
２０…ランダムアクセスメモリ
２２…キーボードインタフェースモジュール
２６…イーサネットインタフェース（Ｉ／Ｆ） モジュール
２７…イーサネットネットワーク
３２…インタフェース制御装置[0001]
[Industrial applications]
The present invention relates to an add-on card for a personal computer, and more particularly, to an additional interface card for an International Business Machines (IBM) AT compatible personal computer for connecting an AT bus to an external Ethernet network. About.
[0002]
Problems to be solved by the prior art and the invention
IBM AT personal computers and AT compatible personal computers use an AT standardized bus system for internal communication. The AT bus is generally referred to as an Industry Standard Architecture (ISA) bus for 8- and 16-bit systems, and an Extended Industry Standard Architecture (EISA) for 32-bit systems. The AT bus standard is described in detail in "AT Bus Design", Edward Solari (Annbooks, 1990), the subject matter of which is incorporated herein by reference. An AT bus is an interface between various functional units of a computer, such as a central processing unit (CPU) memory and various input / output (I / O) device interfaces. The AT bus provides the necessary logic to control the system clock, storage, read / write access, I / O read / write cycles, data bus direction, data and interrupt requests, and speaker driver. . The storage device includes a hard disk, a floppy disk, an electrically erasable programmable read only memory (EEPROM), and a random access memory (RAM). The I / O device includes a printer, a modem, and an Ethernet communication network.
[0003]
A personal computer has a housing that houses a module card rack for holding and interconnecting electronic modules. When the housing is open, an electronic module is inserted into the rack and connected to a motherboard located at the end of the computer housing opposite the housing opening. This motherboard provides the electrical interconnection between the modules in the computer including the AT bus and power and ground. The user can change the capabilities of the personal computer by attaching or removing a computer module to or from the computer housing. For example, by inserting a RAM (Random Access Memory) module into the housing, the storage capacity can be increased.
[0004]
Each device connected to the AT bus and having a storage device has a memory base address (base) that defines the memory space used by that device so that the CPU can command a read or write to the storage device. (Base address). Each storage device must have a unique memory base address so that only one device responds to such a read / write instruction. The AT bus standard assigns specific memory addresses to specific devices. More specifically, the hard disk drive, floppy disk drive and RAM memory are each assigned a unique memory base address range. Therefore, all personal computers use these addresses for communication between the hard disk drive, the floppy disk drive and the RAM memory. In contrast, when a new device is connected to the personal computer, the memory base address of the new device must not be one of the addresses already assigned to other devices, It may be any address in the address range that has not yet been assigned. However, when more than one device is added, each with its own storage device and its corresponding unique memory base address, two or more devices may have the same memory base address. If this occurs, the CPU sends out addresses corresponding to two or more separate devices during an initialization routine at system power-up. The two or more separate devices each respond to an address command, and all of these devices attempt to read or write to memory. These multiple responses cause a conflict on the data portion of the bus. In some cases, the CPU may detect the conflict on the bus because, for example, during system startup or during reading, the data to be read may be different from the system expected values.
[0005]
In current systems, one type of add-on card is an Ethernet interface module for interfacing between an AT bus and an Ethernet network system. The Ethernet standard is Institute of Electrical and Electronics Engineers, Inc. It was issued in 1989 by the "Information Processing Systems - Local Area Networks - Part 3: Carrier sense multiple access with collision detection (CSMA / CD) access method and physical layer specifications", International Standard ISO, 8902-3: 1989, ANSI / IEEE Std 802.3-1988, the subject matter of which is incorporated herein by reference. Further, in the current system, when a memory address conflict is detected, the power of the system is turned off, an add-on card that is presumed to be causing the conflict is removed from the system, and any memory provided on the module is removed. It is necessary to change the configuration of the card by means, after which the expansion card is reinstalled in the system, the system is powered on, and the operation of the module is retested. (The means used in current systems to change the base address is a moveable jumper or switch.) The CPU again performs its initialization routine, and if a conflict with another memory base address is detected, The process of removing the module and physically changing the memory base address is repeated until the memory conflict is eliminated. When no memory conflict is detected, the CPU continues to execute its initialization routine.
[0006]
A plurality of I / O interface devices connected to the AT bus each have an I / O base address. When these I / O interface devices detect their I / O base address on the bus, they respond to instructions on the bus. As with the memory base addresses described above, each I / O interface device must have a unique I / O base address. Like memory addresses, the AT bus standard assigns I / O address ranges to specific devices. Therefore, these I / O addresses are used only by these devices. However, as other devices are added to the AT bus, each of those devices must have its own I / O address. However, as with the memory base address, these devices do not have pre-assigned addresses. Thus, the AT bus standard assigns I / O address ranges to these new devices.
[0007]
However, when a new device is connected to the AT bus, until the CPU has executed its initialization routine, the system will allow two or more devices on the AT bus to use the same I / O base address. I do not know if they are. Thus, when the CPU sends one I / O bus address to two or more devices on the AT bus that use the same address, all of these two or more devices respond and the Creates a conflict.
[0008]
Current systems with EEPROM-based configurations resolve conflicts in the I / O base address in a way that corresponds to how address conflicts are resolved by jumper or switch based designs. More specifically, in the case of an Ethernet module having an EEPROM-based configuration, a computer user first turns on the computer. If a conflict in the I / O memory address is detected during the initialization routine of the CPU, the user removes the module from the first computer and removes the module from the second system that has not caused an I / O base address conflict. You must insert that module into Thereafter, the user can change the I / O address of the module by rewriting the EEPROM of the module. Thereafter, the module whose original configuration has already been changed can be reinstalled in the original system.
[0009]
The above method for resolving address conflicts is cumbersome, expensive, and prone to operator error. The tasks include removing the module from the first computer, inserting the module into the second computer, turning on the second computer and re-installing the module in the second system. Configuring, removing the module from the second system, reinserting the module into the first system and retesting, and repeating this process until all conflicts are eliminated. And need. Each of these steps requires effort to perform, and is therefore time consuming. The additional time for setup, test, and rework increases the cost of the module. Furthermore, the numerous steps described above increase the likelihood of errors during rework and the possibility of damaging the module or the computer by repeated removal and installation of the module in the two computer systems.
[0010]
There is a need for changing the memory address and I / O address of an extension module without jumpers, and for automating the steps in the change to reduce the number of steps.
[0011]
Means and Action for Solving the Problems
Briefly, one embodiment of the present invention is an interface controller for an addressable interface module. This interface module is adapted to be coupled to a central processing unit via a communication bus with other addressable interface modules. Each interface module has a base address unique to each interface module provided on the communication bus by the central processing unit, and a base address on the communication bus for reading data from the interface module to the communication bus. And a write command provided by the central processing unit on the communication bus for writing data from the communication bus to the interface module. The interface controller has a stored configuration base address for determining a unique address to which the corresponding interface module must respond. In addition, the interface controller also has a decoder for decoding a base address including a modified configuration address for use by the corresponding interface module when determining a unique address for a response by the corresponding interface module. The interface controller includes circuitry for automatically changing the stored configuration base address when the stored configuration base address is the same as the unique address for any one of the other interface modules. The circuit includes a second circuit responsive to a predetermined address on the communication bus and a read command to change the stored configuration base address to a different configuration address. In one particular implementation, the first circuit includes a counter for incrementally adjusting a value represented by a configuration base address.
[0012]
Briefly, one embodiment of the present invention provides for the first identification of a first module connected to a bus to eliminate conflicts with a second module connected to the same bus. A method for adaptively adjusting a code in response to a start command. The first identification code is stored in one register. A commanded identification code is received over the bus. A stored first identification code is compared to the commanded identification code received over the bus. Data is sent out over the bus in response to a match between the first identification code and the commanded identification code. Expected data is generated. The sent data is compared to the expected value of the data, and if the sent data does not match the expected data, the result is identified as a mismatch. The first identification code stored in the register is changed in response to the identified mismatch. The above process is sequentially repeated until no discrepancy is identified between the sent date and the expected data so that the first module is uniquely identified by the first identification code.
[0013]
Preferably, the bus is an IBM AT bus, the identification code is an input / output base address, and the start command is a hardware reset command.
[0014]
Circuit for adaptively adjusting a first identification code of a first module connected to the bus in response to a start command to avoid a conflict with a second module connected to the same bus Is provided. The circuit includes means for storing the first identification code, means for comparing the first identification code in the storage means with the commanded identification code, and the commanded first identification code. Means for sending data in response to a match between the identification code, and wherein both the first module and the second module are responsive to the match between the first identification code and the commanded identification code. Means for detecting whether or not data is sent out, and for generating a conflict signal when there is no match, in response to the conflict signal, determining whether the first identification code and the commanded identification code correspond to each other. Means for changing the first identification code such that neither the first module nor the second module sends out data when a match between them occurs.
[0015]
In certain embodiments, an interface module transfers data between an Industry Standard Architecture (ISA) bus and an Ethernet network. The ISA bus transfers first and second groups of addresses and reset instructions from the central processing unit (CPU) to the interface module, and transfers data from the interface module to the CPU. This interface module has an adaptive identification code. The interface module includes a register for storing an applicable identification address. A decoder is coupled to this register for decoding the adaptive identification address from the CPU and the first group of addresses. A buffer memory is coupled to the decoder and the ISA bus. The buffer memory sends data to the ISA bus in response to the first group of decoded addresses when a selected address in the first group of decoded addresses includes an adaptive identification address. Or receive data from the ISA bus. In response to the second group of addresses from the CPU and the reset instruction, the counter changes the adaptive identification address stored in the register.
[0016]
【Example】
FIG. 1 is a functional block diagram illustrating a computer using an Ethernet interface module for communicating between an Ethernet and an AT bus according to the principles of the present invention. The computer 10 has a central processing unit (CPU) module 12 connected to an AT bus 14. The CPU 12 preferably comprises a 486-type microprocessor chip manufactured by Intel Corporation, Santa Clara, California. As described above, the AT bus 14 is a standard bus used by IBM AT personal computers and AT compatible personal computers. The AT bus 14 is also connected to a plurality of storage devices including a hard disk 16, a floppy disk 18, and a random access memory (RAM) 20. Although some storage devices are shown, the invention does not require all of these devices. A printer interface module 22 is connected to the AT bus 14 and a printer 23 outside the computer 10. A keyboard interface module 24 is connected to the AT bus 14 and the keyboard 25. Keyboard 25 provides computer 10 with instructions selected by the user. The Ethernet interface (I / F) module 26 provides an interface for communication between the AT bus 14 and the Ethernet network 27. Alternatively, the interface module 26 may interface with another bus. As mentioned above, Ethernet is a standardized communication network typically used for Local Area Network (LAN). The Ethernet interface module 26 is preferably packaged on one module.
[0017]
Power-up sequences for IBM AT computers are well known in the art. Briefly, at power up, CPU 12 sends a hardware reset to all modules in computer 10 to instruct each module in computer 10 to begin an initialization routine. CPU 12 reads instructions for a basic input / output system (BIOS) from a programmable read-only memory (PROM) located on the CPU module. After executing a plurality of initialization routines from the BIOS, the CPU 12 reads a utility program from the memory. The utility program identifies in advance one of the storage devices (preferably the hard disk 16) and the modules that are expected to be connected to the AT bus 14 and identifies these modules and these modules to the AT bus. An initialization routine and a diagnostic routine are executed with respect to the interface.
[0018]
FIG. 2 is a functional block diagram of the Ethernet interface module 26 for the computer shown in FIG. An Ethernet interface control signal is sent from the CPU 12 over the AT bus 14 over the line 102 to the interface controller 32, while the interface controller 32 is sent over the line 102 to the AT bus 14 in the opposite direction. CPU 12 provides system address instructions to boot programmable read-only memory (PROM) 34 and interface controller 32 via AT bus 14 and system address bus 116. The address of the Ethernet interface module functions as an identification code for identifying the module. Upon receiving an instruction address that matches the address of the Ethernet interface module 26, the module 26 responds to the requested function. The boot PROM 34 includes a startup program for the Ethernet interface module 26. This boot PROM 34 can be used, for example, in a diskless system without the hard disk 16 or the floppy disk 18, in which case the driver program is loaded from the Ethernet 27. The interface controller 32 provides a control circuit for interfacing between the AT bus 14 and the Ethernet 27. Interface controller 32 provides a PROM control signal over line 114 to enable boot PROM 34 and control its output. The boot PROM 34 supplies data to the interface controller 32 via the bus 110.
[0019]
In the first direction, the CPU 12 passes through the AT bus 14 and subsequently the system data bus 106, and in the case of the 16-bit AT bus 14, the system data bus high byte transceiver (system data bus high byte). The system data is supplied to both a transceiver 40 and a system data bus low byte transceiver 42, and in the case of the 8-bit AT bus 14, only the system data bus low byte transceiver 42 is provided. Give system data. In addition, instructions and states are transferred through the system data bus 106. Conversely, the CPU 12 communicates in the second direction through the system data bus 106 followed by the AT bus 14 and, in the case of the 16-bit AT bus 14, the system data bus high byte transceiver 40 and the system data bus. It receives system data from both the bus low byte transceiver 42 or, in the case of the 8-bit AT bus 14, system data only from the system data bus low byte transceiver 42. System data bus high byte transceiver 40 optionally provides data to interface controller 32 over bus 108 or receives data from interface controller 32 in the opposite direction. Interface controller 32 provides a transceiver control signal over line 104 to control data transmission through system data bus high byte transceiver 40. Similarly, system data bus low byte transceiver 42 optionally provides data to interface controller 32 over bus 110 or receives data from interface controller 32 in the opposite direction. Interface controller 32 provides a transceiver control signal over line 112 to control data transmission through system data bus low byte transceiver 42.
[0020]
Clock 118 provides a clock signal to interface controller 32 via line 238. Interface controller 32 provides control signals to light emitting diodes (LEDs) 144 via lines 143, which provide a visual indication of the status of Ethernet interface module 26. For example, the LED 144 can indicate a receive, transmit, collision, and link test pass. ID memory 36 provides jumperless form identification and node identification information to interface controller 32 via line 122 in response to an ID memory control signal from interface controller 32 via line 120. In the boot PROM configuration, ID memory 36 provides storage for the boot PROM address. Preferably, the ID memory 36 is an electrically erasable programmable read only memory (EEPROM). In another embodiment, the form identification and node identification may be stored in an ID PROM that provides this data directly to buses 108,110. The interface controller 32 supplies a buffer control signal 142 and a buffer storage bus address signal 140 to the buffer storage 138, which is preferably a static random access memory (SRAM). To provide memory storage for data transferred over data bus 136 between Ethernet and Ethernet 27. SRAM 138 is typically 8 kilobytes or 32 kilobytes.
[0021]
Connector interface 30 has several types of mechanical connectors for electrically connecting Ethernet interface module 26 to Ethernet 27. More specifically, the Ethernet interface module 26 has an Attachment Unit Interface (AUI) connector 128 for an AUI interface, has a coaxial transceiver interface 130 for signal communication through a coaxial line, and has a coaxial transceiver interface 130 for a twisted pair interface. Has a twisted pair connector 134. The interface controller 32 provides a transmit pair signal via line 124 for both the AUI connector 128 and the coaxial transceiver interface 130. Each of the AUI connector 128 and the coaxial transceiver interface 130 provide receive / collision pair signals to the interface controller 32 via line 126. Interface controller 32 and twisted pair connector 134 communicate with each other by sending differential pairs signals over line 132.
[0022]
FIG. 3 is a functional block diagram of the interface control device shown in FIG. The interface controller 32 has five functional blocks, namely, a system interface 146, a buffer controller 152, a control and status register 150, a transmission circuit 154, and a reception circuit 156.
[0023]
System interface 146 communicates with AT bus 14 using the signals on lines 102, 104, 108, 110, 112, 114, 116 as described above. The system interface 146 has a buffer register 148 for holding data during communication between the AT bus 14 and the Ethernet 27. The system interface 146 communicates bi-directionally with the buffer controller 152, which communicates with the buffer controller 152 and the buffer register 148, the ID memory 36, the SRAM 138, the receiving circuit 156, and the transmitting circuit 154. Controls data transfer between The control and status register 150 receives control and status information from the system interface 146, the buffer controller 152, the transmitting circuit 154 and the receiving circuit 156, and sends control and status information to the system interface 146 and the buffer controller 152.
[0024]
The transmission circuit 154 includes a transmission circuit control device 158 for controlling the encoding of data from the buffer control device 152 in the encoder 160. The encoded data is processed by a pulse shaping circuit and filter 162 before being amplified in a transmit circuit amplifier 166 and provided to the connector interface 30 (see FIG. 2). Conversely, receiving circuit 156 receives the data signal from connector interface 30 and amplifies it in receiving circuit amplifier 174. The amplified data signal is processed in the receiver circuit slicer 172 and then decoded by the decoder 170. Thereafter, the decoded data signal is sent to the receiving circuit controller 168 and further sent to the buffer controller 152. Collision circuit 164 resolves collisions between reception and transmission on Ethernet 27 by processing the decoded signal from decoder 170 and the encoded signal from encoder 160.
[0025]
FIG. 4 is a functional block diagram of a specific implementation of the Ethernet interface module 26 for the computer 10 shown in FIG.
[0026]
The CPU 12 sends a system address (SYSADDRESS) signal to the Ethernet interface module 26 and other modules on the AT bus 14 via the AT bus 14. More specifically, on the Ethernet interface module 26, a SYSADDRESS signal is provided via line 116 to the address input of the boot PROM 34 and the address input of the interface controller 32. CPU 12 issues these system address instructions to define a memory address space and an I / O address space. This addressing is described in detail below in conjunction with FIGS. In addition, the AT bus 14 provides a system connection to both the output enable (OE) input of the boot PROM 34 and the interface controller 32 via line 176 which is part of the Ethernet interface control signal line 102 (FIG. 2). Provide a System Memory Read (SMEMR bar) command. (The overscore (bar) convention for a signal name indicates that the signal is asserted in a low state). The SMEMR bar instruction is an active low signal from the AT bus 14 that indicates that the current bus cycle is a memory read operation and that the Ethernet interface module 26 requests output of data from the storage device. Although the instruction is described herein as an active high / low signal, the invention is not so limited. The Ethernet interface module 26 can be designed for either an active low signal or an active high signal.
[0027]
Further, the CPU 12 enables the transfer of all data, instructions, and states through a system data (SYSDATA) bus 106 or the transfer of all data, instructions, and states through the AT bus 14 to the Ethernet interface module 26. Command other devices to send to More specifically, the SYSDATA bus line 106 leading to the first bidirectional input / output terminals of both the system data bus high byte transceiver 40 and the system data bus low byte transceiver 42 is connected to the AT bus 14. System data bus except that CPU 12 controls the direction of data flow through system data bus high byte transceiver 40 while interface controller 32 controls the direction of data flow through system data bus low byte transceiver 42. Both the high byte transceiver 40 and the system data bus low byte transceiver 42 operate in the same manner. The system data bus high byte transceiver 40 sends an Input / Output Read (IOR) command from the CPU 12 via the AT bus 14 and line 178 to the transceiver's direction control (DIR) input. Receive via terminal. The active high signal on the DIR terminal causes the system to transfer data from system data bus 106 to buffered system data (BSD) bus 180 (including buses 108 and 110 (FIG. 2)) for a write operation. The data bus high byte transceiver 40 is switched. The buffer system data (BSD) bus 180 is an internal data bus on the Ethernet interface module 26. An active low signal on the DIR input switches the transceiver 40 to transfer data in the reverse direction from the BSD bus to the system data bus for a read operation. The IOR bar instruction is an active low signal from the CPU 12, which indicates that the current bus cycle is an I / O read operation, and the Ethernet interface module 26 on the system data bus 106 of the AT bus 14 Request to output data.
[0028]
A buffer system data bus (BSD <15: 0>) 180 interconnects the boot PROM 34, the system data bus high byte transceiver 40, the system data bus low byte transceiver 42, and the controller chip 32. (The convention used to define the bits on a signal line, as used herein, is to enclose the number of bits with a colon-separated <> symbol. For example, BSD <15: 0> may be bits 15- 0.) The system data bus transceivers 40, 42 are preferably 74-ALS245 tri-state bus transceivers. The outputs of jumper buffers 38, 39 are also provided on the BSD bus <15: 0> 180 to the second bidirectional I / O terminals of system data bus high byte transceiver 40 and system data bus low byte transceiver 42.
[0029]
The interface controller 32 provides an Enable Data High Byte (ENNB) command via line 182 to the Enable (EN) input of the system data bus high byte transceiver 40. The enable data high byte signal is an active low signal that enables or disables the system data bus high byte transceiver 40. More specifically, the enable data high byte instruction disables the system data bus high byte transceiver 40 to disconnect the SYSDATA bus 106 from the buffer system data bus 180.
[0030]
For control of system data flow by the Ethernet interface module 26, the system data bus low byte transceiver 42 is controlled in a similar manner. However, both control signals for the system data bus low byte transceiver 42 are provided by the interface controller 32. More specifically, the enable data low byte (ENLB bar) signal on line 184 enables the system data bus low byte transceiver 42 and the low byte direction on line 186 (ENLB bar). The Ethernet interface module 26 outputs data on the system data bus 106 by controlling the direction of data flow from the buffer system data bus 180 to the system data bus 106 by sending a Low Byte Direction (LBDIR bar) signal. .
[0031]
As will be described in more detail below, the Ethernet interface module 26 can operate in either a jumper mode or a jumperless mode. In jumper mode, the configuration of the Ethernet interface module is defined by configuration jumpers 188-195, which are the physical wires on this module. Jumpers 188 and 192 define I / O base addresses, jumpers 189 and 193 define memory base addresses, jumpers 190 and 194 define DMA (Direct Memory Access) acknowledge (Acknowledgment) (DACK), and jumper 191. , 195 define an interrupt. The DACK signal is an active low signal, indicating that an external DMA controller (not shown) is ready to transfer data between the host system and the Ethernet interface buffer memory. The I / O base address, memory base address, and interrupt signal are defined below in conjunction with FIGS. The configuration jumper is connected at one end to a ground or voltage source (VCC) (not shown) and at the other end to the inputs of the configuration jumper buffers 38,39. Alternatively, configuration jumpers 192-195 may be used to define configurations other than those described above. A set of mode jumpers 235 that define which of the EEPROM and the ID PROM store the initial parameters and whether the operation is a jumper operation or a jumperless operation is provided to the interface controller 32. Can be
[0032]
In the jumper mode, the logic level of each configuration jumper is provided on the buffer system data bus 180. When the Ethernet interface module 26 requests to read the state of the configuration jumper, the interface controller 32 sends a Select Configuration Register 1 command (line 196) to the enable (EN) input of the jumper buffer 38 via line 196. SEL12), and jumper buffer 38 in response provides a configuration jumper signal to buffer system data bus 180. The SEL12 instruction is not used in no jumper mode. Alternatively, the jumper buffer 39 is enabled by a Select Configuration Register 2 instruction (SEL13) on line 198 provided by the interface controller 32 to the enable (EN) input of the configuration jumper buffer 39. You. As described below, the SEL13 instruction is used in a jumperless mode to read from shift register / counter 48. The configuration jumper buffers 38, 39 are preferably 74LS244 tri-state buffers. A logic one level switches the corresponding buffered output to a high impedance state and disconnects the jumped input from the output to the bus in both cases of the SEL12 signal on line 196 and the SEL13 signal on line 198. Conversely, a logic 0 level switches the corresponding buffers 38, 39 to either of the SEL12 instruction 196 and the SEL13 instruction 198 to output signals corresponding to the configuration jumpers 188-195 to the buffer system. To the data bus 180.
[0033]
The ID memory 36 stores configuration bytes for the Ethernet interface module 26. The ID memory 36 is preferably a serial EEPROM, such as the National Semiconductor NMC93C06, C26 or C46 series having 256, 512 or 1024 bits, respectively. The serial EEPROM has three inputs from the interface controller 32: a serial data input, a serial data clock or shift clock (SK), and a chip select (CS). The ID memory 36 provides a single output, the serial data output (DO), to the interface controller 32 via line 206. All of the instructions, addresses and write data are provided as inputs to the ID memory 36 via line 200 to the input terminals of the ID memory 36. Data read from the serial EEPROM and status information are output from a serial data output terminal. Interface controller 32 provides a chip select signal to ID memory 36 via line 202. The serial EEPROM shift-in or shift-out the data upon a low-to-high transition of the shift clock (SK) on line 204 from the interface controller 32.
[0034]
In another embodiment, ID PROM 208 provides data to and receives data from buffer system data bus 180 via line 210. Interface controller 32 provides a PROM chip select signal on line 212 to enable ID PROM 208 and a latched address signal on line 213 to address ID PROM 36.
[0035]
Buffer storage memory 138 (also referred to as SRAM 138) and any additional buffer storage memory 138 'receive an address signal 140 from interface controller 32 to select a storage location in that memory. The interface controller 32 provides a buffer chip select signal through lines 224, 226 to each chip enable input terminal on the SRAM 138, 138 'to enable the selected chip. In addition, interface controller 32 provides a write enable (WE bar) signal via line 228 and an output enable (OE bar) signal via line 230 for both SRAMs 138, 138 '. give. Buffer data is bidirectionally communicated between the SRAMs 138, 138 'and the interface controller 32 via the bus 232. Bits 7-0 of the buffer data are provided to SRAM 138. Bits 15-8 of the buffer data are provided to SRAM 138 '.
[0036]
Interface controller 32 and connector interface 30 communicate over lines 124, 126, 132 described above. Connector interface 30 is coupled to Ethernet 27. Interface controller 32 provides system requests to AT bus 14 via line 222 and receives system control signals from AT bus 14 via line 220. Lines 220 and 222 are part of line 102 (FIG. 2).
[0037]
An I / O base address jumper can be connected to line 216 to replace bits 2-0 of the configuration byte to define the I / O base address in jumper mode. Similarly, a memory base address jumper can be connected to line 218 to replace bits 5-3 of the memory base address or bits 7-6 of the interrupt request (described below). Interrupt request 0 is provided to interface controller 32 via line 214.
[0038]
FIG. 5 is a functional block diagram of the address decoding circuit and the constituent byte processing circuit of the interface control device shown in FIG.
[0039]
Jumper mode decoder 44 has first and second inputs (shown collectively as line 235) selectively connected to either ground or a voltage source (VCC) (not shown). And a mode jumper 235 having One output of the jumper mode decoder 44 is a jumper / no jumper (JP / JPLESS) signal on line 237, which signal indicates that the module has a jumper wire change or software (described below). This indicates to the interface control device 32 which of the two will be reconfigured. For example, when connecting the second input 235 to a voltage source (VCC), the JP / JPLES signal on line 237 is a logic one indicating that the module is operating in jumperless mode. Conversely, when connecting the first input 235 to ground, the JP / JPLESS signal is a logic 0 indicating that the module is operating in jumper mode.
[0040]
The serial data output on line 206 from the ID memory 36 is provided to both a first input of a data select multiplexer (MUX) 46 in the interface controller 32 and to the shift register / counter 48. Shift register / counter 48 includes an 8-bit serial input / parallel output shift register having bits 7-0. Bits 2-0 (also called I / O SEL <2: 0>) define the I / O base address. Bits 5-3 (also called MSEL <2: 0>) define the memory base address. Bits 7-6 (also called IRQ <3: 0>) define the interrupt line configuration. The decoding of these bits is described in detail below. The shift register / counter 48 also functions as a counter for bits 2 to 0, as described below.
[0041]
Data selection MUX 46 selectively controls data supplied to BSD bus 180. Further, bits 7-0 of shift register / counter 48 are connected to a second input of data select MUX 46. The system data output high / lower bus, which is an internal bus of the interface controller 32 and interconnects the system interface 146, the control and status register 150, the buffer controller 152, the transmitting circuit 154, and the receiving circuit 156 (FIG. 3). A System Data Output High / Low bus (SDOHL <7: 0>) signal is provided to a third input of the data select MUX 46.
[0042]
The signals provided by data select MUX 46 are controlled by control logic 58. FIG. 6 is a schematic diagram of control logic for controlling the data provided by the data selection MUX 46 to the buffer system data bus. A jumper / jumperless (JP / JPLESS) signal on line 237 is provided by jumper mode decoder 44 to a first input of control logic 58. READ 13 for read address 13 of buffer register 148 (FIG. 3) ₋ An instruction is provided to a second input of control logic 58. JP / JPLESS signal and READ 13 ₋ Is the JPLS provided to the data selection MUX 46 ₋ A NOR operation is performed in the control logic circuit 58 to generate the READ 13 signal.
[0043]
A READ 11 instruction for reading the data output from the ID memory 36 is also provided to the data selection MUX 46. Table I shows a truth table for the outputs selected for data selection MUX 46.

[0044]
The output of the data selection MUX 46 is connected to a bidirectional tri-state buffer 50. The bidirectional input / output port of the bidirectional tristate buffer 50 is connected to the buffer system data bus (BSD <15: 0>) 180 as described above. The bidirectional tri-state buffer 50 selectively controls the direction of data flow between the buffer system data bus 180 and the interface controller 32. The unidirectional output from the bi-directional tri-state buffer 50 is separated by the system data input low (System Data Input Low) (SDAIL <6: 5>) signal and the SDAIL <7> into flip-flops 52 and 54, respectively. Connected to. The direction of the data flow in the bidirectional tri-state buffer 50 is controlled by the control logic 56.
[0045]
FIG. 7 is a schematic diagram of a control logic circuit for controlling a bidirectional tristate buffer. As shown in FIG. 6, the control logic circuit 58 includes the SEL 13 ₋ To generate the signal, the JP / JPLESS signal and READ 13 ₋ The logical product (AND) with the signal is calculated, and this SEL 13 ₋ The signal is provided to configuration jumper buffer 39 and control logic 56. Next, referring to FIG. ₋ The signal is Tri ₋ In order to generate the Out signal, a system least significant bit (System Least Significant Bit) (SYS ₋ LSB ₋ ) The signal is inverted and NANDed, and Tri ₋ The Out signal commands data to flow from the interface controller 32 to the BSD bus 180 in a first logic state (eg, logic “1”), while, conversely, a second logic state (eg, logic “1”). ("0") instructs data to flow from the BSD bus 180 to the interface controller 32. SYS ₋ LSB ₋ The signal is provided by an internal FIFO or register (not shown) and is a qualifier. Accordingly, the data selection MUX 46 is selected to output data on the BSD line 180 from either the ID memory 36, shift register / counter 48, or SDOHL bus.
[0046]
The hardware reset signal on line 236, the JP / JPLESS signal on line 237, and the 20 MHz clock are used to control the first, second, and third of the jumperless state machine 60. Given to the input. Ethernet interface module 26 operates based on a 20 MHz clock signal on line 238 from clock 118 (FIG. 2). The first output signal of the jumperless state machine 60, the Enable Counter (EN CNTR) signal, is used to instruct the shift register / counter 48 to operate as a shift register or counter. The upper part is given to the shift register / counter 48. In addition, a shift register clock (SRCLK) signal is also provided to shift data in shift register / counter 48. The jumperless state machine 60 provides a hardware controlled data in (HARD DI) signal from its second output to the ID memory control MUX 62 via line 239, and the ID memory control MUX 62 The memory 36 is selectively provided with a HARD DI signal via line 200. The jumperless state machine 60 provides a hardware controlled shift clock (HARD SK) signal from its third output to the ID memory control MUX 62 via line 241 and the ID memory control MUX 62 The memory 36 is selectively provided with a HARD SK signal via line 204. The jumperless state machine 60 provides a hardware controlled chip select (HARD CS) signal from its fourth output to the ID memory control MUX 62 via line 242, and the ID memory control MUX 62 The memory 36 is selectively provided with a HARD CS signal via line 202. Jumperless state machine 60 provides a MUX hardware select (MUXHW) signal from its fifth output to ID memory MUX control circuit 69 via line 243.
[0047]
FIG. 8 is a schematic diagram of the ID memory MUX control circuit shown in FIG. The MUXHW control signal is supplied on line 243 to the ID memory MUX control circuit 69, and the ID memory MUX control circuit 69 outputs the MUXHW signal to the SEL. ₋ It is inverted and ANDed with the JP / JPLESS signal to form the MUX signal. Referring again to FIG. 5, SEL is selected to select one of the signal from jumperless state machine 60 to ID memory 36 and the signal from flip-flops 52 and 54. ₋ A MUX signal is provided on line 246 to the ID memory control MUX 62.
[0048]
The software controlled chip selection signal, the software controlled shift clock signal, and the software controlled data-in signal are provided to flip-flops 52 and 54. In particular, SDAIL <6: 5> and SDAIL <7> are separately provided from buffer system data bus 180 to flip-flops 52 and 54 as described above. Further, the WRITE 10 signal and the WRITE 11 signal are separately provided to the flip-flops 52 and 54.
[0049]
Bits 2-0 of shift register / counter 48 are connected to the first input of decoder select MUX 64 as I / OSEL <2: 0>. Bits 5-3 of shift register / counter 48 are provided to the second input of decoder select MUX 64 as signals MSEL <2: 0>. The I / OSEL <2: 0> instruction defined by the jumper is provided on line 216 to the third input of the decoder select MUX 64. A fourth input of the decoder select MUX 64 is connected to a bi-directional tri-state buffer 72. The bidirectional port of the bidirectional tri-state buffer 72 may be connected to a signal line that carries an MSEL <2: 0> instruction defined by a jumper as input or carries an interrupt request (IRQ <3: 0>) signal as output. Connected. The input to the bidirectional tristate buffer 72 is the first output of the interrupt request decoder 70. The second output of interrupt request decoder 70 is interrupt request 0. Bits 7-6 of shift register / counter 48 are also provided to the two inputs of interrupt request decoder 70. The bidirectional tristate buffer 72 is controlled by a JP / JPLESS instruction on line 237 from jumper decoder 44. The output of the decoder selection MUX 64 is connected to a memory address decoder 66 and an I / O address decoder 68. The output of the memory address decoder 66 and the output of the I / O address decoder 68 are connected to an SRAM 138 (FIG. 3). The decoder selection MUX 64 is also controlled by a JP / JPLESS instruction from the jumper decoder 44. The decoder select MUX 64 outputs MSEL <2: 0> from the shift register / counter 48 or the jumper in response to a logical 1 JP / JPLESS instruction or a logical 0 JP / JPLESS instruction, respectively, / OSEL <2: 0> is output.
[0050]
Next, with respect to the hardware defined above, the operation of the Ethernet interface module 26 will be described with reference to FIGS. FIG. 9 is a flow chart of reading configuration bytes from the ID memory to the shift register / counter and resolving memory address conflicts at system power-up or at any other time a System Hardware Reset command is issued. It is. When the system power is turned on (step 300), the CPU 12 sends out a System Hardware Reset command as a start command or an initialization command to each module on the AT bus 14 including the Ethernet interface module 26. After reset, CPU 12 becomes the first AT bus owner. Further, for example, when a user simultaneously presses three control (Ctrl) keys, an ALT key, and a delete (Del) key on the keyboard 25, a Hardware Reset command can be transmitted during normal system operation. . The following description describes the operation of the system with respect to a hardware reset issued at system power up for typical purposes. However, the present invention is not limited to this.
[0051]
At the time of hardware reset, the jumperless state machine 60 determines whether the system configuration indicated by the JP / JPLESS signal from the jumper decoder 44 (FIG. 5) is a jumper system configuration or a jumperless system configuration. The operation of the Ethernet interface module 26 as a jumperless module will be described first first.
[0052]
If the system is a jumperless system, the jumperless state machine 60 (FIG. 5) stores the ID memory 36 in the ID memory control MUX 62 by setting the Chip Select signal on line 202 (FIG. 4) high. Command to select. The Shift Clock instruction on line 204 (FIG. 4) is set to shift data on serial data output 206 from ID memory 36 to shift register / counter 48. In addition, to instruct shift register / counter 48 to operate as a shift register and to clock in serial data output 206 from ID memory 36, a no-jumper state machine 60 provides line 244 ( An instruction is sent to the shift register / counter 48 through FIG. 5).
[0053]
To read the configuration byte from location Ox11 in ID memory 36 and load it into shift register / counter 48, jumperless state machine 60 generates the appropriate signal (step 302). As described above, bits 5-3 determine the memory base address (step 304). FIG. 10 is a map of the memory base address for the AT bus. The memory address is in the range of 0 (00 0000 Hex) to 16384 K (FF FFFF Hex). In practice, the address is 16384K minus one, but for clarity, this -1 is omitted from addresses with the suffix "K". Within this address range, a number of subranges are allocated or reserved for platform memory and BIOS. Address 0 (00 0000 Hex) -512 K (06 FFFF Hex) is a location reserved for platform memory. The address 512 K (07 0000 Hex) -640 K (09 FFFF Hex) is the address range for the platform memory. Address range 100000 (Hex)-FD FFFF (Hex) is reserved for slot memory. Preferably, within this address range, the Ethernet interface module 26 has an address range of C4000-DFFFF. The addresses assigned to the base address bits are shown in Table II below.

[0054]
Referring again to FIG. 9, the Ethernet interface module 26 loads a configuration byte from the ID memory 36, as shown in this figure. The process of reading the configuration bytes from the ID memory 36 starts when the system power is turned on, and is in parallel with the above-described initialization and inspection when the system BIOS is started. Parallel reading of the configuration byte allows the BIOS to scan the ROM location for a valid boot ROM. If the system boots properly (step 306), the boot ROM initialization code initializes its resources, replaces the desired interrupt vector (step 307), returns system control to the system BIOS, and completes its initialization. (Step 308).
[0055]
On the other hand, if the system does not start up properly, it is determined that there is a memory address conflict between the Ethernet interface module 26 in the computer 10 and another extension module (step 306). If there is a memory conflict, the CPU 12 stops during system power-on. To resolve this conflict, the Ethernet interface module 26 is removed from the computer 10 (Step 310) and installed in the second computer system (Step 312). This second system is used to determine whether the Ethernet interface module 26 operates properly by reducing the possibility of memory base address conflicts. This second system has the same basic configuration as the first system, but preferably does not include any additional modules, thereby eliminating memory conflicts between the Ethernet interface module 26 and the additional modules. In addition, in the no-japper mode, a second system is used to reprogram the ID memory 36 with a different memory base address, as described below. After inserting the Ethernet interface module 26 into the second system, the second system is powered on. If the second system boots properly (step 314), the Ethernet interface module 26 is active and the problem with the first system is considered to be a memory conflict. Therefore, to eliminate this conflict, it is necessary to reassign the memory base address location of the Ethernet interface module 26 (step 316).
[0056]
In the jumper mode, the memory base address location is reassigned by changing the memory base configuration jumper 189 (FIG. 4) of the Ethernet interface module 26 by physically adding or changing jumper wires. In contrast, in jumperless mode, the memory base address location is changed, preferably by reprogramming the configuration byte at address 0X13 of ID memory 36. For example, if the memory base address location of the Ethernet interface module 26 initially stored in bits 5-3 of the configuration byte is 000, the address range corresponding to this value 000 is as shown in Table II above. The range is 0XC4000 (Hex)-00XC7FFF (Hex). If there is an address conflict, responding to an address within this range activates both the Ethernet interface module 26 and the second add-on module on the AT bus 14. The memory base address of the Ethernet interface module 26 is reassigned by changing bits 5-3 of the configuration byte. For example, incrementing bits 5 to 3 from 000 to 001 will correspondingly increase the memory base address range to the range 0XC8000 (Hex) -0XCBFFF (Hex) as shown in Table II.
[0057]
To reprogram the ID memory 36, the CPU 12 must first read the configuration byte to know its current state. CPU 12 issues a request for a memory read for the address of the configuration byte at memory location 0X13 of ID memory 36. CPU 12 sends an I / O read (IOR bar) signal to system data bus transceiver 40 to communicate the data address and the requested command to ID memory 36 over the system data bus. The interface controller 32 controls the interface controller 32 to supply data from the system data bus 180 to the flip-flops 52 and 54 in order to supply an address, a shift selection command, and a shift clock command to the ID memory 36. An instruction is given to the state buffer 50 (FIG. 5). The ID memory 36 supplies the requested configuration byte from its data output port to the data select MUX 46, which outputs the data on the buffer system data bus 180 to the Ethernet interface module. 26. The interface control unit 32 instructs the system data bus transceiver 40 to supply data from the buffer system data bus 180 to the system data bus 106 and the CPU 12 via the AT bus 14, and further controls the system data bus transceiver 40. Disable. Thereafter, CPU 12 increments bits 5-3 of the configuration byte, thereby generating a new memory base address, and thereafter, in the manner described above, stores the new configuration in ID memory 36 at location 0X13. It commands the Ethernet interface module 26 to write the byte. In a manner similar to the reading of configuration bytes from ID memory 36 by CPU 12, the CPU writes the incremented configuration bytes to the 0X13 memory location by providing appropriate instructions to ID memory 36 over system data bus 106. To the Ethernet interface module 26.
[0058]
Referring again to FIG. 9, after the Ethernet interface module 26 has been reprogrammed with the configuration byte having the new memory base address, as shown in this figure, the Ethernet interface module 26 is placed in the first computer system. Installed (step 317), the first system is restarted by repeating step 300. This first system completes its startup routine and loads the configuration byte from the ID memory 36 into the shift register / counter 48 as described above with respect to step 302. The interface controller 32 using the decoders 66, 68 decodes its constituent bytes in step 304. If the system boots up properly in step 306, the relocation of memory locations performed in step 316 is correct and the Ethernet interface module 26 proceeds to step 307 as described above. On the other hand, if the reconfigured Ethernet interface module does not properly start up in step 306, remove the Ethernet interface module from the first system (step 310) and test the module in the second system (step 312). ) Is repeated.
[0059]
If the second system does not boot properly at step 314, the configuration bytes of that memory are reconfigured as described at step 316 (step 318). At step 314, the startup of the second system is attempted again. Alternatively, instead of reconfiguring the memory locations in step 318, the Ethernet interface module is inserted into another system (step 320), and the other system is re-launched as described above with respect to step 314. Is also possible.
[0060]
After the Ethernet interface module 26 has been reconfigured to remove any memory base address conflicts, it is determined whether there is an I / O base address conflict. Briefly stated, when the system comes up, if all memory base address conflicts have been resolved as described above, the system will be able to start from some predetermined register locations on the Ethernet interface module 26. The I / O base address is checked by reading the contents and comparing these contents to their expected values. In another embodiment, the Ethernet interface module does not include boot memory. In this embodiment, it is unnecessary to resolve the memory conflict because there is no memory on the Ethernet interface module where a conflict may occur. If the comparison shows a match, there is no I / O base address conflict. On the other hand, the system considers a conflict if the comparison does not show a match. At this time, the system performs a dummy read from a predetermined register position. In response, Ethernet interface module 26 increments its I / O base address. The system reads and compares the contents of the register location at the new address to determine again if there is a conflict. The system repeats this process until no conflicts are detected.
[0061]
Next, I / O address designation will be described with reference to FIG. 11 showing an I / O address base for the AT bus 14. This I / O address ranges from 0 (0000 Hex) to 64 K (FFFF Hex). Within this address range, each 1 K range is divided into two sub-ranges. The first subrange is the lower 256 bytes of memory and is reserved for I / O platform resources such as interrupt controllers and DMA controllers. The second subrange is the remaining high-order 768 bytes, which are available for general purpose I / O dependent modules.
[0062]
In a preferred embodiment, as described below, the Ethernet interface module 26 has an I / O address range from 0x260 (Hex) to 0x3FF (Hex) that falls within the second subrange. As described above, bits 2-0 of the configuration byte (also called I / OSEL <2: 0>) determine the I / O base address. Table III shows the I / O address decoding for the constituent bytes in the address range from 0x260 (Hex) to 0x3FF (Hex).

[0063]
Referring now to FIG. 12, this illustrates the process of an I / O base address conflict routine. At this stage, the memory base address conflict is deemed to have been resolved as described above in FIGS. (Alternatively, in another embodiment where the Ethernet interface module does not have a boot memory, it is not necessary to resolve the memory conflict as described above.) The computer is booted and described above with respect to step 300 of FIG. The initialization routine is performed as described above (step 330). Interface controller 32 loads the configuration byte from ID memory 36 into shift register / counter 48 in a manner similar to step 302 described above with respect to FIG. 9 (step 332). At the completion of this read, shift register / counter 48 is set to counter mode by non-champer state machine 60. In this mode, only bits 2-0 of the configuration byte that determine the I / O base address of the Ethernet interface module 26 are incremented by the counter. The remaining bytes of the configuration byte are left unchanged. Interface controller 32 decodes its constituent bytes into an I / O base address, a memory base address, and an interrupt in a manner similar to that described with respect to step 304 of FIG. 9 (step 334). In addition, a "dirty bit" in a register in the Ethernet interface module 26 is allocated for monitoring the register / counter mode of the special cell. Thereafter, CPU 12 reads from memory within the initial range (step 336). More specifically, CPU 12 enters its I / O program to read the contents of eight registers of interface controller 32. Preferably, each register has 8 bytes. Reading the eight registers is provided only as an example. The invention is not limited to reading only eight registers. The expected expectation that two different add-on modules on the AT bus 14 will not have the same value stored in the register location read by the CPU 12 to determine if there is a conflict from an accidental match. The software programmer can read as many registers as needed to satisfy
[0064]
When the system power is turned on, the eight registers of the interface control device 32 have predetermined values stored as a module identifier or “company code” as part of the utility program recorded on the hard disk 16. Is set to Preferably, the module identifier uniquely identifies the module with respect to other modules on the AT bus 14. This module identifier is preferably an initial value stored in the first eight registers of the Ethernet interface module 26. After these eight registers are read by CPU 12, CPU 12 executes a software utility, which reads the module identifier from hard disk 16 and compares the identifier with the readings from the first eight registers ( Step 338). CPU 12 expects the reading to match the value of this module identifier and interprets the difference between these two values as an I / O base address conflict. When there is a match between the reading and the module identifier (step 340), the CPU 12 determines this match between the Ethernet interface module 26 and other modules on the AT bus 14 by the I / O base address. It interprets that there is no conflict and that the CPU 12 has found a unique I / O base address for the Ethernet interface module 26 (step 342).
[0065]
On the other hand, if the contents of the eight registers read by the CPU 12 differ from the expected values (step 340), the system interprets the mismatch as a conflict of the I / O base address, or The interface module 26 interprets that the CPU 12 is not at the I / O address just read. The system ignores the presence of Ethernet module 26 by ignoring the data provided on AT bus 14, but the software utility continues by attempting to read from a predetermined memory location (step 344). This predetermined memory location is preferably at address 0X12 (Hex). If the CPU 12 attempts to write to some type of storage, a read is preferred because the Ethernet interface module 26 can be physically damaged by conflicting addressing. This read is a "dummy read" because the shift register / counter 48 is set for the counter mode and the CPU 12 does not know what is actually being read. In the counter mode, each time a dummy read is performed, the shift register / counter 48 increments the value of bits 2-0 by one, thereby changing the I / O base address to that value as defined in Table III. Jump to the next address range. The initial I / O base address range is preferably set to 0X300 (Hex) to 0X31F (Hex) defined by bits 2-0 of the configuration byte having the value 111. As the counter is incremented by reading from memory location 0X12, bits 2-0 of the configuration byte change to a value of 000 corresponding to the new address range of 0X260 (Hex) to 0X27F (Hex). The utility program reads the interface controller 32 for an appropriate module identifier each time the shift register / counter counts up to the next base I / O address. This allows the Ethernet interface module 26 to dynamically reconfigure itself to a conflict-free I / O base address. However, after the seventh increment, bits 2-0 return to value 111. After the eighth memory read, either no Ethernet interface module 26 is present in the system, or all I / O base addresses are unavailable. CPU 12 determines whether the module position is within the range of the memory being read (step 346). If the module location is not within the memory range, the value of the configuration byte is not incremented (or counted) and the system increments the I / O base address (step 353) and resets the register at the incremented address. Read (step 348) and loop back to step 338 to compare the reading to the expected value. If no match is obtained at step 340, CPU 12 loops back to step 344. When a match is obtained, the CPU 12 loops back to step 342. The CPU 12 sends a write command to a predetermined address, and the interface control device 32 sets the shift register / counter 48 to the count mode, switches to the user mode, and if necessary, the user To access the ID memory.
[0066]
On the other hand, if the address of the Ethernet interface module is within the range of the memory read in step 346, CPU 12 determines whether it is the last increment of the range (step 350). If so, either the I / O base address range slots are all unusable or the Ethernet interface module 26 is not installed in the system (step 354). On the other hand, if the memory read is not the last memory increment of the memory range, controller chip 32 increases the I / O base address of Ethernet interface module 26 by incrementing bits 2-0 of shift register / counter 48. Increment (step 352). The CPU increments the I / O base address (step 353), and then reads from the eight registers at the incremented I / O base address (step 348). CPU 12 loops back at step 338 to compare the reading with the expected value.
[0067]
Software function inhibition is provided to prevent accidental writing to address 0X12 from accidentally changing configuration bytes in shift register / counter 48. By setting the I / O base unlock bit in the data link register to 0, the shift register / counter 48 is disabled until a system hardware reset is issued again. . This reset instruction sets the unlock bit to one, allowing the Ethernet interface module 26 to dynamically reconfigure itself to a non-conflicting I / O base address.
[0068]
When the I / O address conflict is resolved, the software can continue with the initialization routine. The Ethernet interface module 26 resets the shift register / counter 48 to register mode by setting / resetting a so-called "dirty bit". Immediately thereafter, the utility program can read a new configuration byte from the shift register / counter 48 and reprogram the configuration byte stored in the ID memory 36 with the new base address.
[0069]
Now, an interrupt after the completion of the I / O address program will be described. As mentioned above, bits 7-6 are used only for interrupt line configuration. The interrupt signal enables the expansion card to request the interrupt service by the CPU 12. These bits are programmable to select any one of the four interrupt lines available on the host interface side of the Ethernet interface module 26. The user has the option to connect the interrupt line to any set of four system interrupt lines (interrupts 0-3) available to the system user. The utility tests the interrupt configuration and, if there is a conflict, reprograms the ID memory 36 with the next available interrupt option, restarts the system, and retests the configuration.
[0070]
Table IV below is a list of interrupt bit definitions.

[0071]
After the ID memory 36 has been reprogrammed to resolve memory base address conflicts, I / O base address conflicts, and interrupt conflicts, no further reprogramming of the configuration bytes is required. No conflict will occur when the computer 10 thus configured is subsequently used.
[0072]
While the invention has been described and a preferred embodiment thereof has been described, it is anticipated that other modifications and applications will occur to those skilled in the art. It is therefore intended that the invention be limited only by the claims herein.
[0073]
【The invention's effect】
As described above, according to the present invention, the memory address and the I / O address of the extension module can be changed without a jumper, and the steps in the change can be automated, and the number of steps can be reduced. .
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a computer according to the principle of the present invention.
FIG. 2 is a functional block diagram of an Ethernet interface module for the computer shown in FIG.
FIG. 3 is a functional block diagram of the interface control device shown in FIG. 2;
FIG. 4 is a functional block diagram of a particular embodiment of an Ethernet interface module for the computer shown in FIG.
FIG. 5 is a functional block diagram of an address decoding circuit and a constituent byte processing circuit of the interface control device shown in FIG. 4;
FIG. 6 is a schematic diagram of a control logic circuit for controlling data provided to a buffer system data bus by a data selection MUX.
FIG. 7 is a schematic diagram of control logic for controlling a bidirectional tristate buffer.
FIG. 8 is a schematic diagram of an ID memory MUX control circuit shown in FIG. 5;
FIG. 9 is a flowchart of reading configuration bytes from the ID memory to the shift register / counter and resolving conflicts in the boot memory at system power-up or at other times when the System Hardware Reset command is issued.
FIG. 10 is a map of a memory base address for an AT bus.
FIG. 11 is a map of an I / D base address for an AT bus.
FIG. 12 is a flowchart illustrating a procedure used when reconfiguring an I / O base address of the Ethernet interface module illustrated in FIG. 4;
[Explanation of symbols]
10 ... Computer
12 Central processing unit module
14 ... AT bus
16 ... Hard disk
18. Floppy disk
20: random access memory
22 ... Keyboard interface module
26 ... Ethernet interface (I / F) module
27 ... Ethernet network
32 ... Interface control device

Claims (21)

An interface controller for an addressable interface module, wherein said interface module is adapted to be coupled to a central processing unit via a communication bus with other addressable interface modules, the interface module comprising: A configuration base address unique to the interface module provided on the communication bus by the central processing unit, and a configuration base address on the communication bus by the central processing unit for reading data from the interface module to the communication bus. Or a write command provided by the central processing unit for writing data from the communication bus to the interface module.
The interface control device,
A stored configuration base address for determining a unique configuration base address to which the corresponding interface module must respond;
A decoder for decoding the configuration base address including a modified configuration base address for use by the corresponding interface module upon determining the unique configuration base address for a response by the corresponding interface module; ,
The central processing unit compares the value read from the interface module with a module identifier stored in a hard disk, and as a result of the comparison, based on the fact that the read value and the module identifier do not match, Changing means for automatically changing the stored configuration base address when it is determined that the stored configuration base address is the same as the unique configuration base address for any of the other interface modules. , Including
Means for responding to the configuration base address and the read command provided on the communication bus by the central processing unit to change the stored configuration base address to a different configuration base address. , Including
A mode selector for selectively enabling or disabling the changing means to change the configuration base address, the interface controller corresponding to the interface module when the changing means is disabled; A jumper controller for selecting said unique configuration base address for use by
Interface control unit. 2. The interface control device according to claim 1, wherein the interface control device comprises a single integrated circuit chip. 2. The interface control device according to claim 1, wherein said changing means includes a counter for incrementally adjusting a value represented by said configuration base address. 4. The method of claim 3, wherein the interface controller has a memory for initially storing the configuration base address, and wherein the counter is coupled to receive the configuration base address from the memory before incrementing. An interface controller as described. 5. The interface controller of claim 4, further comprising a state machine for controlling reading of the configuration base address from the memory and loading a signal corresponding to the configuration base address into the counter. The stored configuration base address includes a first base address and a second base address, wherein the first base address is a base address to be changed, and the second address is a memory address space. Wherein the decoder includes means for decoding both the first base address and the second base address to provide separate base addresses for the interface controller. The interface control device according to claim 1. An auto-reconfigurable addressable interface module for coupling between a communication network and a communication bus with other addressable interface modules and a central processing unit, wherein each of the interface modules comprises the central processing unit. A configuration base address unique to the interface module provided on the communication bus by a device, and a read command provided on the communication bus by the central processing unit for reading data from the interface module to the communication bus; Or a write command provided on the communication bus by the central processing unit for writing data from the communication bus to the interface module;
The automatic reconfigurable interface module comprises:
A memory for storing identifier data unique to the auto-reconfigurable interface module;
A register for storing a configuration base address for determining a unique configuration base address to which the auto-reconfigurable interface module has to respond;
Means for responding to the configuration base address provided on the communication bus by the central processing unit and one of the read instructions for changing the configuration base address stored in the register to a different configuration base address;
A decoder for decoding the configuration base address modified by said means for use by said interface module in determining said unique configuration base address for response by said auto-reconfigurable interface module. Including
One of the read instructions on the communication bus for the automatic reconfigurable interface module to read the unique identifier data from the memory to the communication bus for comparison with expected data by the central processing unit. Responds to
The automatic reconfigurable interface module further comprises:
The central processing unit compares the value read from the interface module with a module identifier stored in a hard disk, and as a result of the comparison, based on the fact that the read value and the module identifier do not match, Changing means for automatically changing the stored configuration base address when it is determined that the stored configuration base address is the same as the unique configuration base address for any of the other interface modules. ,
A mode selector for selectively enabling or disabling the changing means to change the configuration base address; and a mode selector for use by the corresponding interface module when the changing means is disabled. A jumper controller for selecting a unique configuration base address.
Automatically reconfigurable interface module. The auto-reconfigurable interface module also has an additional memory for data sent on the communication bus, the register stores an additional base address for the additional memory, and the decoder 8. The automatic reconfigurable interface module according to claim 7, further comprising means for decoding said additional base address in the form of a separate base address to address said additional memory. The auto-reconfigurable interface module according to claim 7, wherein the auto-reconfigurable interface module is adapted to provide an interface between the communication bus and the communication network. The auto-reconfigurable interface module according to claim 9, wherein the auto-reconfigurable interface module is adapted to interface with a local area network. The auto-reconfigurable interface module according to claim 10, wherein the auto-reconfigurable interface module is adapted to interface with an Ethernet network. The auto-reconfigurable interface module according to claim 7, wherein the auto-reconfigurable interface module is adapted to couple to an AT communication bus. A system interface coupled to the communication bus for controlling communication with the communication bus;
A buffer memory for storing data communicated between the auto-reconfigurable interface module and the communication bus or the communication network;
A buffer control device for controlling data transfer from the buffer memory;
A transmission circuit for processing and supplying data to the communication network in response to a command from the buffer control device;
A receiving circuit for receiving and processing data from the communication network;
The auto-reconfigurable interface module according to claim 7, further comprising: A microprocessor system comprising: a communication bus; a plurality of addressable interface modules each coupled to the communication bus; and a central processing unit coupled to the communication bus.
A central processing unit for each of the interface modules to provide a configuration base address unique to each of the interface modules provided on the communication bus by the central processing unit, and to read data from the interface module to the communication bus; And a read command provided on the communication bus by the central processing unit for writing data from the communication bus to the interface module. At least one of the modules includes an auto-reconfigurable interface module;
The automatic reconfigurable interface module comprises:
A memory for storing identifier data unique to the auto-reconfigurable interface module;
A register for storing a configuration base address for determining a unique configuration base address to which the auto-reconfigurable interface module has to respond;
Means for responding to the configuration base address provided on the communication bus by the central processing unit and one of the read instructions for changing the configuration base address stored in the register to a different configuration base address;
Decoding for decoding the configuration base address modified by the means for use by the auto-reconfigurable interface module in determining the unique configuration base address for a response by the auto-reconfigurable interface module; And a vessel,
The auto-reconfigurable interface module is responsive to the read command on the communication bus to read the unique identifier data from the memory to the communication bus for comparison with expected data by the central processing unit. ,
The automatic reconfigurable interface module further comprises:
The central processing unit compares the value read from the interface module with a module identifier stored in a hard disk, and as a result of the comparison, based on the fact that the read value and the module identifier do not match, Changing means for automatically changing the stored configuration base address when it is determined that the stored configuration base address is the same as the unique configuration base address for any of the other interface modules. ,
A mode selector for selectively enabling or disabling the changing means to change the configuration base address; and a mode selector for use by the corresponding interface module when the changing means is disabled. A jumper controller for selecting a unique configuration base address.
Microprocessor system. The automatic reconfigurable interface module comprises:
A data bus coupled to pass data over the communication bus between the central processing unit and the auto-reconfigurable interface module;
An address bus coupled to pass address signals on the communication bus from the central processing unit to the auto-reconfigurable interface module;
The microprocessor system according to claim 14, comprising: The automatic reconfigurable interface module includes an additional memory for data passed over the communication bus, and the register has an additional base address for setting a base for a memory space of the additional memory. 15. The microprocessor of claim 14, wherein the decoder is further adapted to decode the additional base address into another base address to address the additional memory. system. A method for automatically generating a unique configuration base address for an addressable interface module having an interface controller, said addressable interface module including a communication bus with other addressable interface modules. Each of the interface modules is configured to be coupled to the central processing unit via a central processing unit, the configuration base address being unique to the interface module provided on the communication bus by the central processing unit, and the interface module. A read command provided on the communication bus by the central processing unit for reading data from the communication bus to the communication bus, or the central processing unit for writing data from the communication bus to the interface module. A write command given by the apparatus, and is adapted to respond to said method,
Storing a configuration base address in the interface controller;
The central processing unit compares the value read from the interface module with a module identifier stored in a hard disk, and as a result of the comparison, based on the fact that the read value and the module identifier do not match, A configuration base provided on the communication bus by the central processing unit when it determines that the unique configuration base address for the interface module having the interface controller is the same as the configuration base address of the other interface module. Changing the configuration base address stored in the step to a different configuration base address in response to the address and one of the read instructions;
Decoding the modified configuration base address for use by the interface module having the interface controller in determining the unique configuration base address for a response by the interface module. ,
The interface module includes the interface controller including a mode controller and a jumperless controller, and the method further includes:
Selectively enabling or disabling the change of the configuration base address under the control of the mode control device;
Selecting the unique configuration base address under the control of the jumper controller when the change is disabled;
A method that includes 18. The method of claim 17, wherein the step of changing the stored configuration base address further comprises an increment adjustment step of incrementing a value represented by the configuration base address in a counter. The interface controller has a memory, and the method comprises:
First storing the configuration base address in the memory;
Receiving the configuration base address from the memory into the counter prior to the incrementing step;
19. The method of claim 18, further comprising: The interface controller having the interface controller includes a state machine, and the method further comprises providing a signal corresponding to the configuration base address to the counter when the counter performs the incremental adjustment, from the memory. 20. The method of claim 19, further comprising the step of using the state machine to control reading of the configuration base address of the device. The stored configuration base address includes a first base address and a second base address, the first base address is a base address to be changed, and the method further comprises: The method of claim 17, further comprising decoding both the first base address and the second base address to provide.

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