JP3571886B2 - Data processing device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data processing device including a programmable integrated circuit that can implement user logic in a programmable manner.
[0002]
[Prior art]
2. Description of the Related Art There is known a programmable integrated circuit in which circuit data defining circuit functions such as connection information and logic functions is stored in a memory cell or the like so that necessary circuit functions can be programmed. In such a programmable integrated circuit, the circuit function can be changed by rewriting the circuit data. In particular, the circuit function can be easily changed without repeating trial production when designing a digital circuit such as a logic circuit. . As such a programmable integrated circuit, a PLD (Programmable Logic Device) and a PGA (Programmable Gate Array) are known. An FPGA (Field Programmable Gate Array) is an example of PGA.
[0003]
In general, in the case of a system using a central processing unit (referred to as a “CPU”) and a programmable integrated circuit of an SRAM type, a program ROM (read only memory) for storing a CPU program and a user logic for an FPGA are stored. ROMs are implemented separately from each other.
[0004]
As an example of a document describing a programmable integrated circuit, there is JP-A-2-130023.
[0005]
[Problems to be solved by the invention]
At present, most large-scale FPGAs are of the SRAM type, and have a form in which user logic is read from a ROM dedicated to the FPGA at the time of system boot and initialized. However, the central processing unit also has a ROM for storing programs, and the interface format is different, and two types of ICs having the same function exist in one system. Since the capacity is not so subdivided into 4 Mbits after 1 Mbits, there is much waste in considering that a relatively large number of unused storage areas often remain.
[0006]
An object of the present invention is to reduce the size and power consumption of a data processing device including a programmable integrated circuit.
[0007]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0009]
That is, a data processing device includes a CPU (10) for executing a program, a memory (12) for storing a program executed by the CPU, and a programmable integrated circuit (11) for programmably realizing user logic. When the user logic information is stored in the memory together with the program executed by the CPU, the CPU is provided with means for transferring the user logic information in the memory to the programmable integrated circuit.
[0010]
According to the above-described means, since the user logic of the programmable integrated circuit is stored in the memory storing the program of the CPU, a dedicated memory for storing the user logic of the programmable integrated circuit can be omitted. Thereby, the size and power consumption of the data processing device can be reduced. Further, since the user logic information is transferred to the programmable integrated circuit by the CPU, the formation of a dedicated loader circuit for transferring the user logic information to the programmable integrated circuit can be omitted.
[0011]
At this time, the central processing unit and the programmable integrated circuit are connected by a serial signal transmission system, and the user logic information read from the memory in a parallel format is converted into a serial format by the central processing unit and the programmable integrated circuit is converted to a serial format. It can be configured to be transmitted to a circuit.
[0012]
Further, the CPU, the programmable integrated circuit, and the memory may be connected by a bus, and the user logic information may be transmitted from the memory to the programmable integrated circuit in a parallel format.
[0013]
Further, the programmable integrated circuit has first setting means (114) capable of setting a transfer command indicating transfer of user logic information, and second setting capable of setting a start address of writing user logic information to the programmable integrated circuit. Means (117) and a third setting means (115) capable of setting the number of transfer bytes of the user logical information.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a data processing device according to the present invention.
[0015]
As shown in FIG. 1, this data processing device is composed of, but not limited to, a CPU 10, an FPGA 11, and a ROM 12. The CPU 10, the FPGA 11, and the ROM 12 are each formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The ROM 12 originally stores programs to be executed by the CPU 10. In this data processing apparatus, the ROM 12 stores user logic information set in the FPGA 11 together with the programs of the CPU 10. The setting of the user logic information is performed by the CPU 10.
[0016]
The CPU 10 has a built-in serial controller capable of exchanging signals in a serial format. The CPU 10 is provided with an SCK0 terminal for outputting a synchronous clock, a TXD0 terminal for transmitting commands and user logic information, and an RXD0 terminal for receiving status. A SCK1 terminal for capturing a clock, an RXD1 terminal for capturing a command from the CPU 10, user logic information, and the like, a TXD1 terminal for outputting a status to the CPU 10, and a signal input / output of a set logic are enabled. An input / output terminal I / O is provided. Further, the CPU 10 is provided with a ROM-CS0 terminal for outputting a chip select signal for selecting the ROM 12, an RD0 terminal for outputting a read signal, and a DATA0 terminal for taking in read data from the ROM 12. Are provided with a CS2 terminal for taking in a chip select signal from the CPU 10, an OE2 terminal for taking in a read signal from the CPU 10, and a DATA2 terminal for outputting stored information to the CPU 10.
[0017]
FIG. 7 shows a configuration example of the FPGA 11.
[0018]
In synchronization with a synchronization clock input from the SCK1 terminal, a reception register 111 for sequentially taking in commands and user logic information from the RXD1 terminal and converting it into a parallel format, and a synchronization clock input from the SCK1 terminal. A transmission register 112 is provided for converting the parallel data from the serial interface control unit 113 into serial data and outputting the serial data externally via the TXD1 terminal. A command register 114 for holding a command, a transfer counter 115 for counting the number of transfer bytes, a data register 116 for temporarily holding data, an address register 117 for temporarily holding an address, An FPGA memory cell 119 capable of implementing a desired logic is provided. A memory cell rewrite bus for enabling logic rewriting of the FPGA memory cell 119 and a user logic bus for enabling access to user logic of the FPGA memory cell 119 are provided. Is provided with a bus selection circuit 118 for selecting. By the bus selection of the bus selection circuit 118, a user logic rewrite mode and a user logic access mode are realized. This bus selection operation is controlled by the serial interface control unit 113 based on the contents held in the command register 114.
[0019]
The memory cell rewrite bus and the user logic bus include an address bus and a data bus, respectively. In the user logic rewrite mode, the memory cell rewrite bus is selectively connected to the data register 116 and the address register 117 by the bus selection circuit 118. In this state, the CPU 10 can rewrite the FPGA memory cell 119. In the user logic access mode, the user logic bus is selectively connected to the data register 116 and the address register 117 by the bus selection unit 118. In this state, the CPU 10 can access the user logic in the FPGA memory cell 119. Is done.
[0020]
FIG. 2 shows a user logical transfer protocol viewed from the CPU 10 having the configuration shown in FIG.
[0021]
The transfer of the user logic information to the FPGA 11 is performed as follows.
[0022]
The transfer of the user logic information is performed at the initial setting stage after the power is turned on, but can be performed as many times as necessary.
[0023]
First, a command indicating the start of user logical transfer is output from the TXD0 terminal of the CPU 10, followed by a start address indicating where to start writing in the FPGA memory cell 119 and a transfer byte number indicating how much to rewrite. As a result, the FPGA 11 enters the user logic rewrite mode, and thereafter, the received data of the transfer byte number is written into the FPGA memory cell 119.
[0024]
Specifically, when a transfer command, a start address, and a transfer byte number are sequentially transmitted from the CPU 10 to the FPGA 11, the FPGA 11 outputs a command reception, address reception, and byte number reception status. After outputting the transfer byte number to the FPGA 11, the CPU 10 selects the ROM 12 by asserting the output signal from the ROM_CS0 terminal to a low level, and asserts the output signal from the RD0 terminal to a low level. Instruct output of stored data. According to this instruction, data D0 is output from the ROM 12 to the CPU 10, and the data D0 is converted into a serial format in the CPU 10 and then output from the TXD0 terminal, so that the data D0 is transmitted to the FPGA 11. Similarly, data following data D0, such as data D1, is read from ROM 12 and transferred to FPGA 11. In the FPGA 11, when a transfer command is input, it is held in the command register 114, and the mode is transited to the user logic rewrite mode. In this mode, the memory rewriting bus is selected by the bus selection unit 118. Since the start address, the number of transfer bytes, and the data are transferred in the order of the transfer command, the serial interface control unit 113 sets the start address in the address register 117, sets the transfer byte number in the transfer counter 115, and Is set in the data register 116. Every time data is transferred, the content held in the data register 116 is updated, the address set in the address register 117 is incremented, and the data held in the data register 116 is written to the FPGA memory cell 119. . Each time data is written, the transfer counter 115 is counted down. The write address is an output address of the address register 117. This data writing is performed until the count output value of the transfer counter 115 becomes zero. When the value becomes zero, all specified user logic information has been written to the FPGA memory cell 119.
[0025]
In the FPGA 11, when a command or data is received, a status corresponding to the command or data is output from the TXD1 terminal of the FPGA 11. That is, each time a command or data is input via the reception register 111, the serial interface control unit 113 in the FPGA 11 externally outputs a corresponding status via the transmission register 112. The CPU 10 monitors the status output from the TXD1 terminal of the FPGA 11, and if the status is determined to be abnormal, the user logic cannot be normally transferred to the FPGA 11 as it is. The serial interface unit 113 in the FPGA 11 is reset. Thereby, the FPGA 11 is initialized, and the transfer processing is performed again.
[0026]
FIG. 3 shows a user logical access protocol viewed from the CPU 10 having the configuration shown in FIG.
[0027]
When an FPGA is used, communication between the CPU 10 and the FPGA 11 such as user logic mode setting and external data capture is very common. Usually, an interface for this communication is created by user logic and realized by using a limited number of I / O pins. However, in the case of this device, a dedicated interface between the CPU 10 and the FPGA 11 is provided. So, use this.
[0028]
The write operation to the user logic of the FPGA memory cell 119 is performed as follows.
[0029]
When writing to the user logic of the FPGA memory cell 119, a write command, an address, and write data are transmitted from the CPU 10 to the FPGA 11 in the command waiting state of the FPGA 11. The write command is held in the command register 114, and the mode is shifted to the write mode for the user logic. The address and write data following the write command are written to the address register 117 and the data register 116, respectively. Under the control of the serial interface control unit 113, the bus selection unit 118 selectively connects the user logical bus to the data register 116 and the address register 117. Thereby, the information held in the data register 116 can be written to the user logic of the FPGA memory cell 119. Also in this write operation, the status is output from the TXD 1 of the FPGA 11, and the status is checked by the CPU 10. If there is any abnormality in this status, the CPU 10 can reset the serial interface control unit 113 and transmit again from the write command.
[0030]
The read operation from the user logic of the FPGA memory cell 119 is performed as follows.
[0031]
When reading is performed from the user logic of the FPGA memory cell 119, the read command, the address, and the dummy command are transmitted from the CPU 10 to the FPGA 11 in the command waiting state of the FPGA 11. The read command is held in the command register 114, and the mode is shifted to the read mode from the user logic. The address following the read command is written to the address register 117. The reason why the dummy command is required is as follows. That is, a synchronous clock is necessary when the data read from the user logic of the FPGA memory cell 119 is taken into the CPU 10, and a dummy command is output from the CPU 10 in order to output this synchronous clock from the SCK0 terminal of the CPU 10. I have to. Thereby, the data read from the user logic of the FPGA memory cell 119 can be taken into the CPU 10 in synchronization with the transmission of the dummy command.
[0032]
According to the above example, the following operation and effect can be obtained.
[0033]
(1) Since the user logic of the FPGA 11 is stored in the program ROM 12 of the CPU 10, a dedicated memory for storing the user logic of the FPGA 11 can be omitted. This makes it possible to reduce the size and power consumption of the data processing device. Further, since the user logic information is transferred to the FPGA 11 by the CPU 10, it is not necessary to form a dedicated loader circuit for transferring the user logic information to the FPGA.
[0034]
(2) By managing the transfer of the user logic of the FPGA 11 by the CPU 10, it is possible to dynamically change the necessary logic for each phase, and it is possible to reduce the gate size of the FPGA 11. For example, in a digital still camera, a DCT (Discrete Cosine Transform) operation for JPEG (color still image) compression is performed when photographing, and an inverse DCT operation for JPEG decompression is required when browsing. The logic of both operation units is not necessarily required at the same time. The logic of the DCT operation unit may be transferred from the ROM 12 to the FPGA 11 as needed when photographing, and the logic of the inverse DCT operation unit may be transferred to the FPGA 11 as needed, so that the DCT operation function for JPEG compression and the JT decompression In comparison with the case where the inverse DCT operation function is realized at the same time, the scale of the FPGA is about 1/2.
[0035]
In the system development stage, conventionally, every time the logic of the FPGA was changed, user logic information had to be written and exchanged in a dedicated ROM. Logic information can be changed simply by downloading to the emulator.
[0036]
FIG. 4 shows another configuration example of the data processing device according to the present invention.
[0037]
As shown in FIG. 4, this data processing device is composed of, but not limited to, a CPU 15, an FPGA 16, and a ROM 17. The CPU 15, the FPGA 16, and the ROM 17 are each formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.
[0038]
The CPU 15 selects an FPGA_CS5 terminal for outputting a chip select signal for selecting the FPGA 16, an RD5 terminal for outputting a signal for instructing reading, an ADRn5 terminal for outputting an address, a DATA5 terminal for data input / output, and the ROM 17. And a ROM_CS5 terminal for outputting a chip select signal to be output.
[0039]
The FPGA 16 is output from the CS6 terminal for receiving the chip select signal output from the FPGA_CS5 terminal of the CPU 15, the OE6 terminal for receiving the read instruction signal output from the RD5 terminal of the CPU 15 as an output enable signal, and output from the ADRn5 terminal of the CPU 15. It has an ADRn6 terminal for taking in an address signal and a DATA6 terminal for inputting / outputting data.
[0040]
The ROM 17 stores the user logic information of the FPGA 16 together with the program executed by the CPU 15. The ROM 17 has a DATA7 terminal for data output, a CS7 terminal for taking in a chip select signal output from the ROM_CS5 terminal of the CPU 15, and a read instruction signal output from the RD5 terminal of the CPU 15 as an output enable signal. An OE7 terminal for taking in is provided.
[0041]
The data input / output terminal DATA5 of the CPU 15, the data input / output terminal DATA6 of the FPGA 16, and the data output terminal DATA7 of the ROM 17 are connected to each other via a bus BUS so that signals can be exchanged. The program executed by the CPU 15 is transferred from the ROM 17 to the CPU 15 via the bus BUS. Further, the user logic information in the ROM 17 is also transferred to the FPGA 16 via the bus BUS.
[0042]
FIG. 8 shows a configuration example of the FPGA 16.
[0043]
A memory interface control unit 161 for controlling a memory interface is provided. The memory interface control unit 161 has an input signal from the CS6 terminal, an input signal from the OE6 terminal, an input signal from the WE6 terminal, and an input from the ADRn6 terminal. The signal is taken in. A command register 162 for holding a command, a transfer counter 163 for counting the number of transfer bytes, an address register 164 for holding an input address, and a bus selector 165 for selecting a memory rewrite bus and a user logical bus are provided. Provided.
[0044]
The memory rewrite bus and the user logic bus have a data bus and an address bus, respectively. The address bus is selectively coupled to the address register 164 by the bus selector 165, and the data bus is selectively internal by the bus selector 165. Coupled to bus IBUS.
[0045]
FIG. 5 shows a user logical transfer protocol viewed from the CPU 15 having the configuration shown in FIG.
[0046]
Since commands, addresses and data are transferred via the bus BUS, only one of the address buses of the CPU 15 is used to distinguish between a command register for command input and a data register for other access. Are used as ADRn5 terminals. That is, if the output logical value of the ADRn5 terminal is "0", it indicates a command input, and if the logical value is "1", it indicates a data input. The data here is a start address and a transfer address.
[0047]
The transfer command, the start address, and the number of transfer bytes are transferred in this order via the DATA5 terminal. Each time the WR5 terminal is asserted low, the transfer command, the start address, and the number of transfer bytes are written. The transfer command is set in the command register 162, the start address is set in the address register 164, and the number of transfer bytes is set in the transfer counter 163.
[0048]
When the ROM_CS5 terminal is asserted low and the ROM 17 is selected and the RD5 terminal of the CPU 15 is asserted low, data stored in the ROM 17 is read out and each time the WR5 terminal of the CPU 15 is asserted low. An instruction to fetch data of the bus BUS into the FPGA 16 is issued, and the instruction is written to the FPGA memory cell 166. Each time data is transferred, the address set in the address register 164 is incremented, and the transfer counter 163 counts down.
[0049]
FIG. 6 shows a user logical access protocol viewed from the CPU 10 having the configuration shown in FIG.
[0050]
First, the read operation will be described.
[0051]
The WR5 terminal of the CPU 15 is asserted low, an access command is written to the command register 162, and a read address is written to the address register 163. By writing the access command, the FPGA 16 is shifted to the user logical access mode. The address bus in the user logical bus is selectively coupled to the address register 164 by the bus selecting unit 165. The data bus in the user logic bus is connected to the internal bus IBUS by the bus selection unit 165. When an address signal is given from the DATA5 terminal, it is held in the address register 164, and data corresponding to the address is read from the FPGA memory cell 166 and transmitted to the CPU 15 via the DATA6 terminal.
[0052]
The write operation will be described.
[0053]
When writing, the WR5 terminal of the CPU 15 is asserted low, the write address is written to the address register 164, and the write data is output from the DATA5 terminal of the CPU 15 at the next timing when the WR5 terminal of the CPU 15 is asserted low. Then, the write data is written to the FPGA memory cell 166 in the FPGA 16.
[0054]
As described above, also in the data processing apparatus shown in FIGS. 4 and 8, since the user logic of the FPGA is stored in the program ROM of the CPU, a dedicated memory for storing the user logic of the FPGA can be omitted. Accordingly, the same effects as those of the data processing apparatus shown in FIGS. 1 and 7 can be obtained, such as reduction in size and power consumption of the data processing apparatus.
[0055]
Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention.
[0056]
For example, a CPU and an SRAM-type FPGA can be integrated into one chip and provided as programmable built-in peripheral functions. Further, it can be used as an evaluation chip for a CBIC development customer including a CPU core.
[0057]
Symbol level compatibility is provided between the FPGA user logic and the source program of the CPU so that only a part of the user logic can be dynamically rewritten.
[0058]
An SRAM-type FPGA is built in the CPU core, and a user-defined CPU instruction can be added and executed.
[0059]
One FPGA may have both SRAM logic and EEPROM logic cells, and the logic used fixedly or the logic used immediately after power-on may be stored in the EEPROM, and the logic used dynamically changed and used may be stored in the SRAM.
[0060]
In the above description, the case where the invention made by the inventor is mainly applied to a data processing device having an FPGA, which is the field of application as the background, has been described. However, the present invention is not The present invention can be widely applied to a data processing device including an integrated circuit.
[0061]
The present invention can be applied on the condition that it includes at least a programmable integrated circuit.
[0062]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
[0063]
That is, since the user logic of the programmable integrated circuit is stored in the memory in which the program of the central processing unit is stored, the dedicated memory for storing the user logic of the programmable integrated circuit can be omitted. Thereby, the size and power consumption of the data processing device can be reduced. In addition, since the user logic information is transferred to the programmable integrated circuit by the CPU, the formation of a dedicated loader circuit for transferring the user logic information to the programmable integrated circuit can be omitted.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a data processing device according to the present invention.
FIG. 2 is a timing chart for explaining a user logical transfer protocol as viewed from a CPU having the configuration shown in FIG. 1;
FIG. 3 is a timing chart for explaining a user logical access protocol viewed from a CPU having the configuration shown in FIG. 1;
FIG. 4 is a block diagram showing another configuration example of the data processing device according to the present invention.
FIG. 5 is a timing chart for explaining a user logical transfer protocol viewed from a CPU having the configuration shown in FIG. 4;
6 is a timing chart for explaining a user logical access protocol as viewed from the CPU having the configuration shown in FIG. 4;
FIG. 7 is a block diagram showing a configuration example of the FPGA shown in FIG. 1;
FIG. 8 is a block diagram illustrating a configuration example of the FPGA illustrated in FIG. 4;
[Explanation of symbols]
10,15 CPU
11,16 FPGA
12, 17 ROM
111 Receive register
112 Transmission register
113 Serial interface control section
114,162 Command register
115,163 transfer counter
116 Data Register
117,164 address register
118,165 bus selection circuit
119,166 FPGA memory cell
161 Memory interface control unit

Claims (8)

A central processing unit for executing the program;
A memory for storing a program executed by the central processing unit;
A data processing device including a programmable integrated circuit for programmably realizing user logic,
Said memory stores programs to be executed by the central processing unit, and stores the user logic information, the central processing unit, viewed contains a transfer means for transferring the user logic information in the memory in the programmable integrated circuit, the A data processing device , wherein the transfer means reads the user logic information from the memory and transfers the user logic information to the programmable integrated circuit . The central processing unit and the programmable integrated circuit are coupled by a serial signal transmission system, and the user logic information read in a parallel format from the memory is converted to a serial format by the central processing unit and transmitted to the programmable integrated circuit. The data processing apparatus according to claim 1, wherein the data processing is performed. 2. The data processing apparatus according to claim 1, wherein the central processing unit, the programmable integrated circuit, and the memory are connected by a bus, and user logic information is transmitted to the programmable integrated circuit in a parallel format. A central processing unit for executing the program;
A memory for storing a program executed by the central processing unit;
A programmable integrated circuit for programmably realizing user logic,
Transfer means for transferring user logic information to the programmable integrated circuit,
The memory stores the user logic information together with the program executed by the central processing unit, and the transfer unit reads the user logic information from the memory in accordance with an instruction from the central processing unit, and stores the user logic information in the programmable integrated circuit. A data processing device for transferring data to a circuit. The transfer means and the programmable integrated circuit are coupled by a serial signal transmission system, and the user logic information read in a parallel format from the memory is converted to a serial format by the transfer means and transmitted to the programmable integrated circuit. The data processing device according to claim 4. 5. The data processing device according to claim 4, wherein said transfer means, said programmable integrated circuit, and said memory are connected by a bus, and user logic information is transmitted to said programmable integrated circuit in a parallel form. The programmable integrated circuit has first setting means for setting a transfer command indicating transfer of user logic information, second setting means for setting a start address of writing of user logic information to the programmable integrated circuit, and user logic information. 7. The data processing apparatus according to claim 1, further comprising a third setting unit that sets the number of transfer bytes. A central processing unit for executing the program;
A programmable integrated circuit for programmably realizing user logic,
In a data processing device including a transfer unit that transfers user logic information to the programmable integrated circuit,
The transfer means reads the user logic information from the same memory as that for storing a program to be executed by the central processing unit according to an instruction from the central processing unit, and transfers the user logic information to the programmable integrated circuit. Data processing device.

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