JP3425920B2 - Clock tree designing apparatus, clock tree designing method, and recording medium - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock tree designing device for designing clock wiring. The present invention also relates to a clock wiring design method. Furthermore, the present invention relates to a recording medium in which a program for designing clock wiring is recorded.

[0002]

2. Description of the Related Art To design a fine circuit such as a large scale integrated circuit (LSI), Japanese Patent Laid-Open No. 6-187391,
JP-A-9-26988 and JP-A-9-232438.
Japanese Patent Laid-Open No. 11-8314 and Japanese Patent No.
Various techniques have been developed as disclosed in Japanese Patent No. 877083.

In the technique disclosed in Japanese Patent Laid-Open No. 6-187391, timing analysis is performed after the wiring data is determined by the placement and wiring. Then, the unnecessary buffer found by the timing analysis is removed from the logic circuit, and the cell having the excessive driving capability is replaced with the cell having the low driving capability, thereby reducing the power consumption of the logic circuit. In this technique, in order to reduce the circuit design process, the timing analysis is performed after designing a clock tree for supplying a clock signal to each cell.

The technique disclosed in Japanese Unexamined Patent Publication No. 9-26988 uses a correspondence table of wiring lengths and cell driving capabilities created in advance and is optimal for wiring loads obtained from temporary placement and wiring. A semiconductor integrated circuit is designed in a short time by using a cell having driving capability.

The technique disclosed in Japanese Unexamined Patent Publication No. 9-232438 has a redundant cell arranged in a wiring area where a critical path is formed, and an arbitrary buffer cell among functional cells arranged on the critical path. Is replaced by a drivability variable cell whose drive capability can be changed. Then, the delay time of signal propagation is adjusted using the redundant cell and the drivability variable cell.

The technique disclosed in Japanese Patent Application Laid-Open No. 11-8314 discloses a clock tree depth (number of stages), that is, a buffer arranged in the clock tree in order to minimize power consumed in the clock tree. The number is calculated by numerical calculation. The technique disclosed in Japanese Patent No. 2877083 occurs in a critical path by replacing a cell existing on a critical path of a circuit with a cell having a small driving ability or inserting a new cell on the critical path. The signal delay is improved.

[0007]

However, the above-mentioned Japanese Unexamined Patent Application Publication No.
No. 26988, JP-A-9-232438,
Further, the technology disclosed in Japanese Patent No. 2877083 does not consider clock wiring (clock tree) for supplying a clock signal to each cell at all, and thus the power consumption of the clock wiring may be large. .

The technique disclosed in Japanese Patent Laid-Open No. 6-187391 performs timing analysis after designing a clock tree, but does not consider power consumption in the clock tree at all. Therefore, power consumption in the clock tree may be large.

The technique disclosed in Japanese Patent Laid-Open No. 11-8314 is a technique for reducing the power consumption of the clock tree, but the types of buffers (inverter type and non-inverter type) are taken into consideration. Absent. Therefore, it may not be possible to obtain a clock tree having an optimum configuration for reducing power consumption. In addition, since this technology does not consider the influence of power consumption due to wiring other than the clock tree at all, the power consumption of the actually formed clock tree may be larger than the value obtained by numerical calculation. is there.

From the above, the above-mentioned JP-A-6-1873.
91, JP-A-9-26988, JP-A-9-
Even if the techniques disclosed in Japanese Patent No. 232438, Japanese Patent Laid-Open No. 11-8314, and Japanese Patent No. 2877083 are combined, it may not be possible to design a clock wiring with low power consumption. Therefore, an object of the present invention is to provide a clock tree designing apparatus and a clock tree designing method for designing clock wiring of low power consumption. Another object of the present invention is to provide a recording medium recording a program for designing low power consumption clock wiring.

[0011]

In order to achieve the above object, a clock tree designing apparatus according to a first aspect of the present invention is a clock for supplying a clock signal from a clock signal supply circuit to a plurality of circuit blocks. Wiring design means for designing wiring; buffer placement means for designing clock wiring having a first configuration by placing a buffer of one of an inverter type and a non-inverter type at a predetermined position of the clock wiring; Buffer replacement means for designing a clock wiring having a second configuration by replacing a predetermined number of buffers with another type of buffer, an inverter type and a non-inverter type, and the first configuration and the second configuration. Calculating means for calculating the power consumed by the entire clock wiring of the configuration, and the calculating means The determined power consumption of the clock wiring having the first configuration and the power consumption of the clock wiring having the second configuration are compared to determine which power consumption is smaller, and according to the determination result of the determination means, And a configuration determining unit that determines the configuration of the clock wiring to the one with lower power consumption. According to the present invention, clock wirings having different configurations are designed, the power consumed by each clock wiring is obtained, and the configuration having the smaller power consumption is determined, so that the clock wiring with low power consumption can be designed. it can.

The buffer arranging means arranges the buffer at a branch point of the clock wiring, and the buffer replacing means arranges the buffer in units of stages indicating the same branch point from the clock signal supply circuit toward each circuit block. You may substitute. The buffer replacement unit may replace the buffer in units of even stages so that the logical value of the clock signal input to each circuit block is not inverted. The wiring designing means designs a signal wiring for supplying a processing signal other than a clock signal to each circuit block, and the computing means adds an increase in power consumption caused by a parasitic capacitance of the clock wiring and the signal wiring. The power consumption may be obtained.
Error verifying means for verifying a timing error after the configuration determining means determines the configuration of the clock wiring, and insertion and replacement of a buffer in the signal wiring to remove the timing error detected by the error verifying means. Circuit modification means for performing the above may be further provided.

A clock tree designing method according to a second aspect of the present invention is a wiring design process for designing a clock wiring for supplying a clock signal from a clock signal supply circuit to a plurality of circuit blocks, and a predetermined clock wiring. A buffer arranging step of designing a clock wiring having a first configuration by arranging a buffer of one of an inverter type and a non-inverter type at a position; A buffer replacement step of designing a clock wiring having a second configuration by substituting the other type of buffer for the type, and an operation for obtaining the power consumed by the entire clock wiring of the first configuration and the second configuration, respectively. And the clock wiring having the first configuration obtained in the calculation step. The power consumption and the power consumption of the clock wiring having the second configuration are compared to determine which power consumption is lower, and the power consumption of the clock wiring configuration is lower according to the determination result of the determination step. And a configuration determining step of determining the configuration of.

The buffer arranging step includes a step of arranging the buffer at a branch point of a clock wiring, and the buffer replacing step shows a step unit indicating the same branch point from the clock signal supply circuit toward each circuit block. The step of replacing the buffer with may be provided. The buffer replacing step may include a step of replacing the buffer in units of even stages so that the logical value of the clock signal input to each circuit block is not inverted. The wiring designing step includes a step of designing a signal wiring for supplying a processing signal other than a clock signal to each circuit block, and the computing step includes
The method may include a step of obtaining the power consumption by increasing the power consumption caused by the parasitic capacitance of the clock wiring and the signal wiring. An error verifying step of verifying a timing error after the configuration of the clock wiring is determined in the configuration determining step, and a buffer insertion into the signal wiring to remove the timing error detected in the error verifying step. And a circuit modification step of performing replacement.

A computer-readable recording medium according to a third aspect of the present invention includes wiring design means for designing clock wiring for supplying a clock signal from a clock signal supply circuit to a plurality of circuit blocks in a computer. A buffer arranging means for designing a clock wire having a first configuration by arranging one of an inverter type buffer and a non-inverter type buffer at a predetermined position of the clock wiring, and a predetermined number of the buffers among the buffers. Buffer replacement means for designing the clock wiring having the second configuration by replacing the buffer with the other type of the inverter type and the non-inverter type, and the entire clock wiring of the first configuration and the second configuration is consumed. Computation means for obtaining electric power and the first structure obtained by the computation means The power consumption of the clock wiring having the second configuration is compared with the power consumption of the clock wiring having the second configuration, and the configuration of the clock wiring is determined according to the determination means that determines which power consumption is smaller, and the determination result of the determination means. A program for functioning as a clock tree designing device having a configuration determining unit that determines the configuration with lower power consumption is recorded.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a clock tree designing device according to a first embodiment of the present invention will be described with reference to the drawings. The clock tree designing apparatus according to the first exemplary embodiment includes a wiring unit 11 as shown in FIG.
The wiring information unit 12, the calculation unit 13, the comparison unit 14, and the configuration determination unit 15 are configured. The wiring unit 11 includes a known placement and routing tool, and according to a circuit specification given in advance, a placement position of a circuit block and a clock wiring (clock tree) for supplying a clock signal from a clock signal supply circuit to each circuit block. To design. Also,
The wiring unit 11 arranges a non-inverter type buffer at each branch point of the designed clock wiring. This allows
The wiring unit 11 generates a clock wiring diagram showing the arrangement positions of circuit blocks, the formation positions of clock wirings, and the like.

The wiring information unit 12 obtains the capacitance value and resistance value of the clock wiring from the clock wiring diagram generated by the wiring unit 11. Further, the wiring information unit 12 generates a netlist showing the connection relation (arrangement position etc.) of the buffer as shown in FIG. 2A from the clock wiring diagram generated by the wiring unit 11. The buffer shown in the netlist is
Of the branch points of the clock wiring existing from the clock signal supply circuit to the circuit block, the first branch is classified into the first branch, the second branch, etc., depending on the branch point. For example, in FIG. 2A, the buffer 21 is in the first stage,
The buffer 22 and the buffer 23 are the second stage, and the buffer 24
~ 27 are classified in the third row. After generating such a netlist, the wiring information unit 12 changes the buffer type to the inverter type and generates a temporary netlist as shown in FIG. 2B, for example. The wiring information section 1
2 replaces the buffer in units of even stages so that the logic value of the clock signal input to each circuit block is not inverted. For example, in FIG. 2B, the buffers 22 and 23 arranged in the second stage of the netlist shown in FIG. 2A are provided in the inverter type buffers 32 and 33 and the buffers 24 to 27 arranged in the third stage. Is an inverter type buffer 3
4 to 37.

The operation unit 13 obtains the power consumed by the entire clock wiring before and after replacing all or part of the non-inverter type buffer with the inverter type buffer. Specifically, the calculation unit 13
The delay time of the signal generated in the clock wiring is obtained from the netlist (temporary netlist), the wiring capacitance, and the wiring resistance from the wiring information unit 12, and the dullness of the signal waveform input to each buffer is obtained from the delay time. Then, the calculation unit 13 calculates the power consumption of the entire clock wiring generated when the signal output from the buffer makes one round trip to “010” from the obtained signal waveform bluntness and the wiring capacitance.

The comparison unit 14 compares the power consumptions calculated by the arithmetic unit 13 before and after the buffer replacement, determines which power consumption is smaller, and the determination result is sent to the configuration determination unit 15. Output. The configuration determining unit 15
The configuration of the clock wiring is determined according to the determination result supplied from the comparison unit 14. Specifically, before replacing the buffer, that is, when it is determined that the power consumption is smaller when the inverter type buffer is not used, the configuration determination unit 15
Determines a clock wiring configuration using only non-inverter type buffers. On the other hand, when it is determined that the power consumption after replacing the buffer is smaller, the configuration determining unit 15 determines the configuration of the clock wiring after replacing the buffer with the inverter type in units of even stages.

FIG. 3 is an input waveform blunt (TRF) -power consumption characteristic diagram of the non-inverter type buffer and the inverter type buffer. Since the non-inverter type buffer is formed by connecting two inverter type buffers formed of a CMOS circuit in series, the number of elements such as transistors forming the non-inverter type buffer is larger than that of the inverter type buffer. . Therefore, as shown in FIG.
In F, the power consumption of the inverter type buffer is smaller than the power consumption of the non-inverter type buffer.

On the other hand, since the inverter type buffer is composed of a single-stage CMOS circuit, the dullness of the input waveform is greatly affected by the load connected to the output side. In other words, when the buffer is changed from the non-inverter type to the inverter type, the bluntness of the input waveform increases slightly or greatly depending on the configuration of the circuit block. Therefore, as shown in FIG. 3, if the increase in TRF is small as indicated by AB in FIG. 3, power consumption is reduced when the buffer is changed from the non-inverter type to the inverter type. On the other hand, TR
If the increase of F is large like AC in FIG. 3, the power consumption will be large when the buffer is changed from the non-inverter type to the inverter type. However, as described above, the comparison unit 14 compares the magnitudes of power consumption, and the configuration determination unit 15 selects the configuration with the smaller power consumption, whereby clock wiring with low power consumption can be realized. .

Next, the operation of the clock tree designing device configured as described above will be described. In the following description, in order to facilitate understanding, a case where there are four circuit blocks will be described as an example. FIG. 4 is a flowchart showing a clock tree designing process of the clock tree designing apparatus. First, the wiring unit 11 designs the layout position of the circuit block and the formation position of the clock wiring according to the circuit specifications given in advance. After that, the wiring section 11
A clock wiring diagram in which a number of non-inverter type buffers corresponding to the number of circuit blocks are inserted at each branch point of the clock wiring is generated (step S101). In the clock wiring diagram, for example, as shown in FIG. 5, four circuit blocks 40a to 40d are arranged at predetermined positions, a clock wiring CL symmetrically extending from each branch point is formed, and each branch point of the clock wiring is Non-inverter type buffer 51-
57 is inserted.

Next, the wiring information unit 12 obtains the wiring capacitance and wiring resistance of the clock wiring from the clock wiring diagram generated by the wiring unit 11 (step S102). Subsequently, the wiring information unit 12 generates a netlist as shown in FIG. 6A from the clock wiring diagram generated by the wiring unit 11 (step S103). Then, the wiring information unit 12 replaces the buffer type in units of an even number of stages to generate a temporary netlist. Specifically, the wiring information unit 12 first replaces the buffers 54 to 57 of the third stage, which is the lowest stage, with the buffers 64 to 67 of the inverter type. Then, the wiring information unit 12 holds the logical value of the clock signal,
The second stage buffers 52 and 53 are replaced with inverter type buffers 62 and 63 to generate a temporary netlist as shown in FIG. 6B (step S104).

Next, the calculation unit 13 supplies the netlist, the temporary netlist, the wiring capacitance, which are supplied from the wiring information unit 12,
Then, the power consumed by the entire clock wiring is calculated from the wiring resistance before and after the replacement of the non-inverter type buffer with the inverter type buffer (step S105). Then, the comparison unit 14
The calculation unit 13 determines which of the power consumptions calculated before and after the replacement of the buffer is smaller (step S106), and outputs the determination result to the wiring determination unit 15.

The configuration determining unit 15 determines the configuration of the clock wiring according to the determination result supplied from the comparing unit 14 (step S107). For example, when it is determined that the power consumption is smaller before the buffer is replaced, that is, when the inverter type buffer is not used, the wiring determination unit 15
Determines the configuration shown in the clock wiring diagram of FIG.
On the other hand, when it is determined that the power consumption after replacing the buffer is smaller, the configuration determining unit 15 replaces the second-stage and third-stage buffers with inverter-type buffers as shown in FIG. Determine the configuration. Thus, the clock tree designing device ends the clock tree designing process. As described above, by comparing the power consumption when the inverter type buffer is used for the clock wiring and the power consumption when it is not used, and adopting the configuration with the smaller power consumption, the clock with the smaller power consumption is used. Wiring (clock tree) can be designed.

Next, a clock tree designing apparatus according to a second embodiment of the present invention will be described with reference to the drawings. In addition to the clock wiring design shown in the first embodiment, the clock tree designing apparatus according to the second embodiment supplies processing signals (control signals, data, etc.) other than clock signals to each circuit block. Design signal wiring for this purpose. The clock tree designing apparatus according to the second embodiment, as shown in FIG. 8, for example, has a wiring unit 71, a wiring information unit 72, a first calculation unit 73, a comparison unit 74, and a clock wiring determination unit 75. And a second calculation unit 76 and a correction unit 77.
It consists of and.

The wiring section 71 is provided with a known placement and routing tool, and designs all wirings according to circuit specifications given in advance. Specifically, the wiring unit 71 designs the layout position of the circuit block, the clock wiring, and the signal wiring according to the circuit specifications given in advance. And the wiring part 7
In No. 1, the number of non-inverter type buffers corresponding to the number of circuit blocks is inserted in the clock wiring, and the non-inverter type and / or inverter type buffers are inserted in the signal wiring to generate a circuit layout / wiring diagram. . The wiring information unit 72 obtains the wiring capacitance and wiring resistance of the clock wiring and the signal wiring from the layout wiring diagram generated by the wiring unit 71. The wiring information unit 72 also generates a netlist and a temporary netlist similar to those in the first embodiment. In addition,
Similar to the first embodiment, the wiring information unit 72 replaces the buffer in even-numbered stages so that the logical value of the clock signal input to each circuit block is not inverted when the temporary netlist is generated. To do.

Similar to the first embodiment, the first arithmetic unit 73 is consumed by the entire clock wiring before and after replacing all or part of the non-inverter type buffer with the inverter type buffer. To obtain the required power. However, in the second embodiment, the first calculation unit 73
Calculates the power consumption including the influence of parasitic capacitance generated between the clock wiring and the signal wiring (for example, increase in power consumption). The comparison unit 74 is substantially the same as the comparison unit 14 described in the first embodiment, and compares the power consumption calculated before and after the buffer replacement by the first calculation unit 73, It is determined whether the power consumption is low, and the determination result is output to the clock wiring determination unit 75. The clock wiring determination unit 75 is substantially the same as the configuration determination unit 15 shown in the first embodiment, and the comparison unit 74
The configuration of the clock wiring is determined according to the determination result supplied from Specifically, the clock wiring determination unit 75
Decide the configuration with the smaller power consumption.

The second arithmetic unit 76 is a clock wiring determining unit 7.
Using the clock wiring having the configuration determined in 5, it is verified whether or not a timing error has occurred in the entire clock wiring and signal wiring. Specifically, the second calculation unit 76
The delay time of the signal generated in the entire clock wiring and signal wiring is obtained, and it is verified whether the setup time, the hold time, etc. of the flip-flop circuit satisfy predetermined values. Then, the second calculation unit 76 outputs the result of the timing verification to the correction unit 77. The correction unit 77 corrects the layout / wiring diagram generated by the wiring unit 71 by inserting a buffer at a position where a timing error occurs according to the verification result supplied from the second calculation unit 76. As a result, the correction unit 77 disperses the load on the buffer at the location where the timing error has occurred or reduces the delay time.

Next, the operation of the clock tree designing device configured as described above will be described. FIG. 9 is a flowchart showing a wiring design process of the clock tree designing device. First, the wiring unit 71 designs the layout positions of the circuit blocks and the clock wirings in accordance with the circuit specifications given in advance, and inserts as many non-inverter type buffers into the clock wirings as the number of circuit blocks ( Step S201). Subsequently, the wiring unit 71 generates a circuit layout and wiring diagram by designing signal wirings and inserting as many non-inverter type and / or inverter type buffers as the number of circuit blocks into the signal wirings. (Step S202).

Next, the wiring information unit 72 obtains the wiring capacitance and wiring resistance of the clock wiring and the signal wiring from the layout wiring diagram generated by the wiring unit 71 (step S203). Subsequently, the wiring information unit 72 generates a netlist in the case where only the non-inverter type buffer is used, from the layout and wiring diagram generated by the wiring unit 71 (step S204), as in the first embodiment. . Then, the wiring information section 72
In the same manner as in the first embodiment, replaces the buffer type in units of even stages and generates a temporary netlist (step S205). After that, the first calculation unit 73 replaces all or part of the non-inverter type buffer with the inverter type buffer from the netlist, the temporary netlist, the wiring capacitance, and the wiring resistance supplied from the wiring information unit 72. Before and after, the power consumed by the entire clock wiring is calculated (step S206).
At this time, the first calculation unit 73 obtains the power consumption including the influence of the parasitic capacitance generated between the clock wiring and the signal wiring as described above.

Then, the comparison section 74 determines which of the power consumptions calculated by the first calculation section 73 before and after the buffer replacement is smaller (step S20).
7), and outputs the determination result to the clock wiring determining unit 75. The clock wiring determination unit 75 determines the configuration of the clock wiring according to the determination result supplied from the comparison unit 74, as in the first embodiment (step S208). Next, the second calculation unit 76 uses the clock wiring determined by the clock wiring determination unit 75 to obtain the delay time of the signal generated in the entire clock wiring and the signal wiring, and the timing error and the like in the entire clock wiring and the signal wiring. It is verified whether it does not occur (step S209).

Then, the correction unit 77 corrects the layout / wiring diagram generated by the wiring unit 71 by inserting a buffer at the position where the timing error occurs in accordance with the verification result of the second operation unit 76 (step S210). , The wiring design process ends. As described above, the clock tree designing apparatus according to the second embodiment calculates the power consumption of the clock wiring after forming the clock wiring and the signal wiring. Therefore, the influence of the parasitic capacitance or the like generated between the clock wiring and the signal wiring can be considered, and the power consumption can be obtained more accurately. That is,
The clock tree designing device can efficiently design low power consumption clock wiring.

In the above embodiment, an example in which the buffers of the second and third stages inserted in the clock wiring are changed from the non-inverter type to the inverter type has been described. Buffers other than may be replaced. For example, the buffers in the first and third stages may be replaced, and the buffers in the first and second stages may be replaced. If there are a plurality of replacement patterns, the power consumption of all or some of them may be obtained, and the configuration of the clock wiring with the lowest power consumption may be adopted. Further, the clock tree designing apparatus shown in the second embodiment performs the processing from step S203 to step S210 of the wiring design processing shown in FIG.
It may be repeated until the timing error is not detected in 209.

Further, in the above-described embodiment, an example is shown in which a non-inverter type buffer is first inserted in the clock wiring and then the buffer is replaced with an inverter type buffer in units of even stages. However, an inverter type buffer may be first inserted in the clock wiring, and then the buffer may be replaced with a non-inverter type buffer in units of even stages. If the logical value of the clock signal may be inverted, the buffer type may be replaced in units of stages, regardless of whether it is in units of even stages or units of odd stages, and the configuration with the lowest power consumption may be adopted. Good.

Further, the device of the present invention does not need to use a dedicated device and can be realized by an ordinary computer. For example, by recording a program and data for executing each of the above processes on a computer in a recording medium (floppy disk, CD-ROM, etc.), distributing the program, installing the program, and executing the program on the OS, the present invention can be realized. The device can be realized. Further, the distribution of the program and data is not limited to the CD-ROM or the like, but may be performed via a communication line or the like.

[0037]

As is apparent from the above description, the present invention enables the design of low power consumption clock wiring.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a clock tree designing apparatus according to a first embodiment.

FIG. 2 is a diagram showing a netlist showing a connection relationship between clock wirings and buffers.

FIG. 3 shows the input waveform blunting (TRF) of a non-inverter type buffer and an inverter type buffer.
It is a figure which shows a power consumption characteristic.

FIG. 4 is a flowchart showing a clock tree designing process performed by the clock tree designing apparatus according to the first embodiment.

FIG. 5 is an example of a layout and wiring diagram of a circuit generated by the clock tree designing device.

FIG. 6 is a diagram showing a netlist generated from the layout and wiring diagram of FIG. 5;

7 is a layout and wiring diagram in which the type of the buffer shown in the layout and wiring diagram of FIG. 5 is changed.

FIG. 8 is a configuration diagram of a clock tree designing device according to a second embodiment.

FIG. 9 is a flowchart showing a wiring design process performed by the clock tree designing apparatus according to the second embodiment.

[Explanation of symbols]

11 Wiring part 12 Wiring information section 13 Operation part 14 Comparison section 15 Configuration determination unit 71 Wiring part 72 Wiring information section 73 First Operation Unit 74 Comparison Department 75 Clock wiring determination unit 76 Second operation unit 77 Correction Department

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Claims (11)

(57) [Claims] 1. A wiring design means for designing a clock wiring for supplying a clock signal from a clock signal supply circuit to a plurality of circuit blocks, and one of an inverter type and a non-inverter type at a predetermined position of the clock wiring. By arranging a buffer, buffer arranging means for designing a clock wiring having the first configuration, and by replacing a predetermined number of the buffers with another type of buffer of the inverter type and the non-inverter type among the buffers, A buffer replacement means for designing a clock wiring having a second configuration; a computing means for determining the power consumed by the entire clock wiring of the first configuration and the second configuration; and a first configuration determined by the computing means. Comparing the power consumption of the clock wiring having it with the power consumption of the clock wiring having the second configuration In comparison, a determining unit that determines which of the power consumptions is smaller, and a configuration determining unit that determines the configuration of the clock wiring to the configuration with the smaller power consumption according to the determination result of the determining unit are provided. Clock tree design device. 2. The buffer arranging means arranges the buffer at a branch point of a clock wiring, and the buffer replacing means is in units of stages indicating the same branch point from the clock signal supply circuit toward each circuit block. The clock tree designing device according to claim 1, wherein the buffer is replaced. 3. The buffer replacing means replaces the buffer in units of even stages so that the logical value of the clock signal input to each circuit block is not inverted. Clock tree design device. 4. The wiring design means designs a signal wiring for supplying a processing signal other than a clock signal to each circuit block, and the computing means calculates a power consumption caused by a parasitic capacitance between the clock wiring and the signal wiring. The clock tree designing device according to any one of claims 1 to 3, wherein the power consumption is calculated by adding an increase. 5. An error verifying means for verifying a timing error after the structure determining means determines a structure of a clock wiring, and an error verifying means for removing the timing error detected by the error verifying means. The clock tree designing apparatus according to claim 4, further comprising: a circuit modifying unit that inserts and replaces a buffer. 6. A wiring design process for designing a clock wiring for supplying a clock signal from a clock signal supply circuit to a plurality of circuit blocks, and one of an inverter type and a non-inverter type at a predetermined position of the clock wiring. By arranging the buffers, a buffer arranging step of designing a clock wiring having the first configuration, and by replacing a predetermined number of the buffers with the other type of buffers of the inverter type and the non-inverter type among the buffers, A buffer replacement step of designing a clock wiring having a second configuration, an operation step of obtaining electric power consumed by the entire clock wirings of the first configuration and the second configuration, and a first configuration obtained in the operation step. Of the clock wiring having the second configuration and the power consumption of the clock wiring having the second configuration And a configuration determining step of determining the configuration of the clock wiring to the configuration with the smaller power consumption according to the determination result of the determination step. Characteristic clock tree design method. 7. The buffer arranging step includes a step of arranging the buffer at a branch point of a clock wiring, and the buffer replacing step indicates the same branch point from the clock signal supply circuit toward each circuit block. 7. The clock tree designing method according to claim 6, further comprising a step of replacing the buffer in units of stages. 8. The buffer replacing step comprises a step of replacing the buffer in units of an even number of stages so that a logic value of a clock signal input to each circuit block is not inverted. Clock tree design method described in. 9. The wiring designing step comprises a step of designing a signal wiring for supplying a processing signal other than a clock signal to each circuit block, and the computing step is caused by a parasitic capacitance of the clock wiring and the signal wiring. 9. The clock tree designing method according to claim 6, further comprising a step of obtaining the power consumption by adding an increase in power consumption. 10. An error verifying step of verifying a timing error after the configuration of the clock wiring is determined in the configuration determining step, and the signal wiring to remove the timing error detected in the error verifying step. 10. The clock tree designing method according to claim 9, further comprising: a circuit modification step of inserting and replacing the buffer of. 11. A wiring design means for designing a clock wiring for supplying a clock signal from a clock signal supply circuit to a plurality of circuit blocks, and one of an inverter type and a non-inverter type at a predetermined position of the clock wiring. Arranging a buffer of this type, a buffer arranging means for designing a clock wiring having the first configuration, and a predetermined number of buffers of the buffers are replaced with another type of buffer, an inverter type and a non-inverter type. Thus, the buffer replacement means for designing the clock wiring having the second configuration, the computing means for respectively determining the power consumed by the entire clock wiring of the first configuration and the second configuration, and the Power consumption of clock wiring having one configuration and clock having second configuration A determining unit that compares the power consumption of the lines and determines which of the power consumptions is smaller; and a configuration determining unit that determines the configuration of the clock wiring to the one with the smaller power consumption according to the determination result of the determining unit. A computer-readable recording medium having a program recorded thereon for functioning as a clock tree designing device.