JP3412155B2 - Switching power supply - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device, and more particularly to a flyback type switching power supply device which operates as a ringing choke converter (RCC).

[0002]

2. Description of the Related Art FIG. 6 shows a flyback type switching power supply device which operates a ringing choke converter (RCC) which has been widely used conventionally. The switching power supply device shown in FIG. 6 includes a DC power supply (1) composed of a rectifier circuit or a battery (storage battery) connected to an AC power supply, a primary winding (2a), a secondary winding (2b), and A transformer (2) having a reset detection winding (2c), a MOS-FET (MOS field effect transistor) (3) as a main switching element, a rectifier having a rectifier diode (4) and a smoothing capacitor (5). Smoothing circuit (6) and MOS-FET
A control circuit (7) for controlling ON / OFF of (3), detecting the voltage V _O of the load (8) and detecting it via the light emitting part (9a) and the light receiving part (9b) of the photocoupler (9). An output voltage detection circuit (10) for applying a signal to the control circuit (7) as a voltage control signal is provided. Primary winding (2a) of transformer (2) and MOS-FET
(3) is connected in series to the DC power supply (1). The rectifying / smoothing circuit (6) is connected between the secondary winding (2b) of the transformer (2) and the load (8) and supplies the load (8) with DC power of the voltage V _O.

The control circuit (7) is a light receiving part of the photocoupler (9).
A current mirror circuit (11) that outputs a current corresponding to the control current flowing in (9b), and an on-time setting capacitor (12) that is charged by the current output from the current mirror circuit (11) and that generates a voltage V _CP. ), A reference power source (13) for generating a reference voltage V _REF , and a level of the voltage V _CP of the non-inverting input terminal (+) connected to the on-time setting capacitor (12) and the reference power source (13) Reference voltage V _{REF of} the inverted input terminal (-)
A high voltage (H) level comparison output signal when it exceeds the level of the reference voltage V _REF of - level voltage V _CP of comparison between the level the non-inverting input terminal (+) of the inverting input terminal () Voltage rise to detect rise of flyback voltage V _FB generated in reset detection winding (2c) of transformer (2) when the generated comparator (14) and MOS-FET (3) are turned off An oscillator circuit (16) driven by the detection signal from the detection circuit (15) and the voltage rise detection circuit (15) and generating an output signal in synchronization with the fall of the detection signal.
And a high voltage (H) level ON signal V _{FF1 is applied} to the gate terminal of the MOS-FET (3) via the drive circuit (18) and a comparator (14 ), A reset state is brought about by the comparison output signal and a low voltage (L) level off signal V _FF1 is supplied to the drive circuit (18)
The reset priority RS flip-flop (17) is provided to the gate terminal of the MOS-FET (3) via the. The on-time setting capacitor (12), the reference power supply (13) and the comparator (14) form an on-time determination circuit (19). Also,
In FIG. 6, reference numerals (20) and (21) denote backflow prevention diodes,
(22) indicates resistance.

The operation of the switching power supply device shown in FIG. 6 is as follows. When power supply is started from the DC power supply (1) and the oscillator circuit (16) in the control circuit (7) starts operating, an output signal is given to the set terminal (S) of the reset priority RS flip-flop (17). It As a result, the reset-priority RS flip-flop (17) is set, and a high voltage (H) level ON signal V _FF1 is applied to the gate terminal of the MOS-FET (3) via the drive circuit (18) to turn on the MOS. -
The FET (3) is turned on. At this time, MOS-FET
The voltage V _DS between the drain and source terminals of (3) becomes approximately 0 V as shown in FIG. 7 (A), and the current _ID flowing in the MOS-FET (3) is linear as shown in FIG. 7 (B). And the energy is stored in the transformer (2). Along with this, FIG. 7 (C)
As shown in, a negative voltage V _FB is generated in the reset detection winding (2c) of the transformer (2), and the on-time is determined by the current output from the current mirror circuit (11) in the control circuit (7). The on-time setting capacitor (12) in the circuit (19) is charged, and the voltage V _CP across it is linearly increased as shown in FIG. 7 (D).

On-time setting capacitor (12) voltage V _CP
Is input to the non-inverting input terminal (+) of the comparator (14),
As shown in FIG. 7 (D), when the level of the voltage V _CP of the on-time setting capacitor (12) exceeds the level of the reference voltage V _REF of the reference power source (13), the high voltage (H) from the comparator (14). A level comparison output signal is generated and applied to the reset terminal (R) of the reset priority RS flip-flop (17). As a result, the reset priority RS flip-flop (17) is in a reset state, and the MOS-FET is driven via the drive circuit (18).
A low voltage (L) level off signal V _{FF1 is} applied to the gate terminal of (3).
Is added to turn off the MOS-FET (3). At this time, as shown in FIG. 7 (B), the current _ID flowing in the MOS-FET (3) becomes substantially 0, and the voltage V _DS between the drain and source terminals changes from 0V as shown in FIG. 7 (A). Energy accumulated in the transformer (2) that rises rapidly and is stored in the secondary winding (2b)
Is supplied to the load (8) through the rectifying / smoothing circuit (6), and the transformer (2) is reset. At the same time, the transformer (2)
The polarity of the flyback voltage V _FB generated in the reset detection winding (2c) changes from negative to positive as shown in FIG. 7C, and the non-inverting input of the voltage rising detection circuit (15) and the comparator (14) Input to the terminal (+). Voltage rise detection circuit
When the level of the voltage V _CP input to (15) exceeds the level of the rising detection voltage V _UP as shown in FIG. 7 (D), a detection signal is output from the voltage rising detection circuit (15) and the oscillation circuit ( 16) is driven. The voltage rise detection circuit
The level of the rising detection voltage V _UP of (15) is the reference power supply (13).
The reference output voltage of the comparator (14) is higher than the reference voltage V _REF.
(H) Holds the level. This enables reset priority RS
The reset state of the flip-flop (17) is held and the MO
The off state of the S-FET (3) is held.

When the reset period of the transformer (2) ends and the polarity of the flyback voltage V _FB of the reset detection winding (2c) of the transformer (2) changes from positive to negative as shown in FIG. 7 (C). , The voltage V input to the non-inverting input terminal (+) of the comparator (14) after a delay time due to the on-time setting capacitor (12) and the resistor (22) connected in parallel with the on-time setting capacitor (12) _As shown in FIG. 7D, _CP becomes equal to or lower than the level of the reference voltage V _REF of the reference power source (13), and the comparator (14)
Generates a low voltage (L) level comparison output signal. Therefore, nothing is input to the reset terminal (R) of the reset priority RS flip-flop (17), and the set terminal is synchronized with the fall of the detection signal of the voltage rise detection circuit (15).
The reset priority RS flip-flop (17) is set by the output signal of the oscillation circuit (16) input to (S).
As a result, a high voltage (H) level ON signal V _FF1 is applied to the gate terminal of the MOS-FET (3) from the reset priority RS flip-flop (17) through the drive circuit (18), and the transformer (2) MOS-FET synchronized with the fall of the flyback voltage V _FB generated in the reset detection winding (2c)
(3) is turned on. At this time, energy is not transmitted to the secondary winding (2b) side of the transformer (2), and the MOS-FE
Smoothing capacitor of the rectifying and smoothing circuit (6) during the off period of T (3)
The electric charge charged in (5) is supplied to the load (8). As described above, the MOS-FET (3) is on / off controlled, and the DC output is supplied from the secondary winding (2b) of the transformer (2) to the load (8) via the rectifying and smoothing circuit (6). To be done. In addition, MOS-FET
When the delay time by the on-time setting capacitor (12) and the resistor (22) is adjusted so that the voltage V _DS between the drain and source terminals of (3) becomes the minimum value, the time when the MOS-FET (3) is turned on is adjusted. Switching loss is reduced and conversion efficiency is improved.

The voltage V _O of the load (8) is the output voltage detection circuit (10)
The light intensity of the light emitting part (9a) of the photocoupler (9) is changed by the detection signal output from the output voltage detection circuit (10), and the control current flowing in the light receiving part (9b) is accordingly changed. Change. As a result, the current output from the current mirror circuit (11) is controlled, and the on-time setting capacitor (1
The rising speed of the voltage V _CP of 2) is controlled. The voltage V _CP of the on-time setting capacitor (12) is input to the non-inverting input terminal (+) of the comparator (14) and the reference voltage V _{REF of} the reference power supply (13) connected to the inverting input terminal (-). Compared to.

As the impedance of the load (8) increases,
Since the voltage of the detection signal of the output voltage detection circuit (10) increases, the light intensity of the light emitting section (9a) of the photocoupler (9) increases and the control current flowing through the light receiving section (9b) increases. For this reason, the current of the current mirror circuit (11) increases and the rising speed of the voltage V _CP of the on-time setting capacitor (12) becomes faster.
The voltage V _{CP of the} on-time setting capacitor (12) is
The time required to reach the level of the reference voltage V _REF of 3) becomes short. Therefore, the reset priority RS flip-flop
The pulse width of the control pulse signal given from (17) to the gate terminal of the MOS-FET (3) via the drive circuit (18) becomes narrow, and the time width of the current flowing in the MOS-FET (3) becomes narrow. . On the contrary, when the impedance of the load (8) becomes low, the operation opposite to the above operation is performed, and the MOS-FE is reset from the reset priority RS flip-flop (17) through the drive circuit (18).
The pulse width of the control pulse signal applied to the gate terminal of T (3) becomes wider. As described above, the MOS-FET (3) from the reset-priority RS flip-flop (17) via the drive circuit (18) according to the change in the voltage or impedance of the load (8).
The pulse width of the control pulse signal applied to the gate terminal of is controlled, and the DC voltage V _O applied to the load (8) is maintained at a constant level.

[0009]

In the conventional switching power supply device shown in FIG. 6, when the load (8) is in a light load state where the impedance is high, as shown in FIGS.
OS-FET (3) drain-source voltage V _DS and drain current I _D , transformer (2) reset detection winding
The intervals of the waveforms of the voltage V _FB of (2c) and the voltage V _CP of the non-inverting input terminal (+) of the comparator (14) are compared with those in the case of heavy load shown in FIGS. 7 (A) to (D). Since it becomes narrower, MOS-F
The switching frequency of ET (3) becomes high. Therefore, as the load (8) becomes lighter, the number of times the MOS-FET (3) is turned on and off increases, which increases switching loss and lowers the conversion efficiency under light load.

Therefore, an object of the present invention is to provide a switching power supply device capable of reducing switching loss under light load and improving conversion efficiency in a wide load range.

[0011]

A switching power supply device according to the present invention comprises a primary winding (2a) of a transformer (2) and a main switching element (3) connected in series to a DC power supply (1).
A rectifying / smoothing circuit (6) connected to the secondary winding (2b) of the transformer (2) and supplying a DC output (V _O ) to the load (8), and the primary or secondary winding (2a, A reset detection winding (2c) electromagnetically coupled to 2b) and a control circuit (7) for on / off controlling the main switching element (3) are provided. The control circuit (7) is a winding for reset detection after the main switching element (3) is turned off.
The voltage (V _FB ) generated in (2c) detects the reset period of the transformer (2), turns on the main switching device (3) after the reset period, and turns on the voltage (V _O ) of the load (8). When the level exceeds the level of the reference voltage (V _REF ), the main switching element (3) is turned off to keep the level of the DC output (V _O ) constant. In addition, the control circuit (7)
Load (8) voltage (V _O ) or load (8) current (I _O )
The load state detection means (51) for detecting the light load state or the state other than the light load of (8) and the voltage (V
_FB ) counter means for counting the number of falling times (52),
After the load state detection means (51) detects a light load state and the reset period of the transformer (2) ends, the counter means (52) detects the flyback voltage (V _FB ) of the reset detection winding (2c) from the second time onward. When the number of falling edges is counted or load state detection means
(51) detects a state other than light load and counter means (52)
Is the main switching element when counts the first falling of the flyback voltage (V _FB ) of the reset detection winding (2c)
The control terminal of (3) is provided with an ON signal generating means (53) for applying an ON signal (V _FF1 ).

After the load state detecting means (51) detects the light load state and the reset period of the transformer (2) ends, the counter means (52) detects the second voltage (V _FB ) of the reset detecting winding (2c). When counting the subsequent falling edges, turn on signal generation means (5
3) from the ON signal (V
_Since the main switching element (3) is switched from the off state to the on state by applying _FF1 ), the off period of the main switching element (3) is extended and the switching frequency of the main switching element (3) is reduced. Therefore, the main switching element
Since the number of times of on / off of (3) is reduced, it is possible to reduce the switching loss at the time of a light load, and it is possible to improve the conversion efficiency of the switching power supply device in a wide load range.
That is, when the load state detecting means (51) detects a light load state, the flyback energy of the transformer (2) is changed to a secondary value within a relatively short period after the main switching element (3) is turned off. Load from winding (2b) through rectifying and smoothing circuit (6)
Since it is supplied to (8), the reset period of the transformer (2) is shortened. As a result, a narrow voltage pulse including free vibration is generated in the reset detection winding (2c) of the transformer (2), and the counter means (52) causes the narrow voltage pulse to fall after the second time. ON signal generation means when counting (53)
From the ON signal to the control terminal of the main switching element (3)
By adding (V _FF1 ), the main switching element (3)
The OFF period is extended and the switching frequency of the main switching element (3) is lowered. In addition, load state detection means (5
When 1) detects a state other than light load, the flyback energy of the transformer (2) stays in the secondary winding (2b) for a relatively long period after the main switching element (3) is turned off. Since it is supplied to the load (8) via the rectifying / smoothing circuit (6), the reset period of the transformer (2) becomes long. As a result, a wide voltage pulse is generated in the reset detection winding (2c) of the transformer (2), so that when the counter means (52) counts the first falling edge of the wide voltage pulse, the ON signal generating means is generated. By applying an ON signal (V _FF1 ) from the (53) to the control terminal of the main switching element (3), the main switching element (3) is switched from the OFF state to the ON state after the reset period of the transformer (2) ends. Normal ringing choke converter (RCC) operation is performed.

In one embodiment of the present invention, the load state detecting means (51) has a hysteresis characteristic with respect to the voltage (V _O ) of the load (8) or the current (I _O ) flowing through the load (8). . As a result, when switching from the heavy load state to the light load state or from the light load state to the heavy load state, the level of the voltage (V _O ) of the load (8) becomes the first reference voltage (V _R1 ) and the first reference voltage. The output signal (V _FF2 ) of the load state detection means (51) is generated even when a period of intermediate level with the second reference voltage (V _R2 ) higher than (V _R1 ) occurs.
Since the voltage level of is maintained at the previous voltage level, it is possible to avoid unnecessary switching between the heavy load state and the light load state in the load state. Therefore, it is possible to smoothly switch between the heavy load state and the light load state, and
There is an advantage that the noise due to the vibration of the core of (2) can be prevented.

A control circuit according to an embodiment of the present invention
(7) outputs an ON signal (V _FF1 ) to the control terminal of the main switching element (3) when the count signal is not output from the counter means (52) within the switching cycle after the main switching element (3) is turned off. Since the maximum off-time setting means (54) is provided, the flyback voltage (V _FB ) generated in the reset detection winding (2c) of the transformer (2) during start-up is extremely small and the flyback voltage When the falling edge of (V _FB ) cannot be detected, the ON signal (V _FF1 ) is applied to the control terminal of the main switching element (3) from the maximum off time setting means (54), and the main switching element (3) is forced. From the off state to the on state. As a result, the voltage (V _O ) of the load (8) rises, and thereafter, the voltage of the reset detection winding (2c) of the transformer (2) increases.
Since the operation shifts to the normal ringing choke converter (RCC) operation synchronized with the falling of (V _FB ), there is an advantage that the switching power supply device can be smoothly started. Further, the control circuit (7) controls the voltage of the reset detection winding (2c) (V
_FB ) has a delay circuit (56) that delays the falling edge of the main switching element (3) and the lowest point of the voltage (V _{D S} ) applied between the main terminals of the main switching element (3) and the reset detection winding ( 2c) voltage (V
_Since it is set so that the falling time of ( _FB ) is almost the same,
When the voltage (V _DS ) between both main terminals of the main switching element (3) is minimized, the main switching element (3) can be switched to the ON state, and the switching loss can be minimized. Therefore, there is an advantage that the conversion efficiency of the switching power supply device can be improved.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a switching power supply device according to the present invention will be described below with reference to FIGS. However, in these drawings, substantially the same parts as those in FIGS. 6 to 8 are designated by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 1, the switching power supply device of the present embodiment has a load state detection circuit (51) as load state detection means for detecting the state of the load (8) by a detection signal of an output voltage detection circuit (10). And a counter circuit (52) as counter means for counting the number of times the flyback voltage V _FB of the reset detection winding (2c) falls, and a load state detection circuit (51) detects a light load state and a transformer. When the counter circuit (52) counts the second falling of the flyback voltage V _FB of the reset detection winding (2c) after the reset period of (2) ends, or the load state detection circuit (51) is in a heavy load state. Of the MOS-F when the counter circuit (52) counts the first falling edge of the flyback voltage V _FB of the reset detection winding (2c).
An ON signal generating circuit (53) as ON signal generating means for generating an output signal V _W1 for turning on the ET (3), and a MOS.
-Switching cycle (several tens of μs after turning off FET (3))
Output signal V that turns on the MOS-FET (3) when the count signal is not output from the counter circuit (52)
The output signal V of the maximum off-time setting circuit (54) as the maximum off-time setting means for generating _W2 and the on-signal generation circuit (53)
Reset priority RS flip-flop (17) for OR signal V _F1S of _W1 and output signal V _{W2 of} maximum off-time setting circuit (54)
Of the OR gate (55) applied to the set terminal (S) of the reset detection coil, the reset detection winding (2c) and the counter circuit (52), and the flyback voltage V of the reset detection winding (2c). voltage rise detection circuit (15) and the oscillation circuit of the control circuit shown in FIG. 6 and a delay circuit (56) which delays the fall time of the _FB to generate a delayed signal V _DL flyback voltage V _FB and (7) ( 1
It is added in place of 6). Load status detection circuit (5
1) has a hysteresis characteristic with respect to the level of the detection signal of the output voltage detection circuit (10). The delay time of the delay circuit (56) can be set by appropriately selecting the resistance value of the resistor or the electrostatic capacitance of the capacitor forming the delay circuit (56).
It is set so that the lowest point of the voltage V _DS between the drain and source terminals of T (3) coincides with the falling point of the flyback voltage V _FB of the reset detection winding (2c). Note that FIG.
In the on-time determination circuit (19) shown in, the resistor (22) shown in FIG.
High voltage input from the reset priority RS flip-flop (17) to the gate terminal via the inverter (24) instead of
Discharge MOS-which is turned on by (H) level signal
The FET (23) is connected in parallel with the on-time setting capacitor (12). The current mirror circuit (11) is the same as FIG. 6 except that it produces two current outputs. Further, the reset priority RS flip-flop (17), the drive circuit (18) and the backflow prevention diode (20) are the same as those in FIG.

As shown in FIG. 2, the load state detection circuit (51)
Is a load state detecting resistor (57) for converting the current of the current mirror circuit (11) into a load state detecting voltage V _RL , a first reference power source (58) for generating a first reference voltage V _R1 , and A first load state in which a comparative output signal V _CP1 having a high voltage (H) level is generated when the level of the detection voltage V _RL of the load state detection resistor (57) exceeds the level of the first reference voltage V _R1. Detection comparator (59) and first load state detection comparator (59)
_Inverter for outputting a signal obtained by inverting the comparison output signal V _CP1 of
(60) and a second reference power source for generating a second reference voltage V _R2
(61) and a comparative output signal V _CP2 of high voltage (H) level is generated when the level of the detection voltage V _RL of the load state detection resistor (57) exceeds the level of the second reference voltage V _R2. The second load state detection comparator (62) and the high voltage (H) level inversion output signal of the inverter (60) input to the set terminal (S) cause a set state and a high voltage (H) level output. Second signal for generating signal V _FF2 and input to reset terminal (R)
And an RS flip-flop (63) for generating a low voltage (L) level output signal V _FF2 by being reset by a high voltage (H) level comparison output signal V _CP2 of the load state detection comparator (62). There is. In this example, the first reference voltage V _R1 of the first reference power source (58) is set to 1 [V], and the second reference voltage V _R2 of the second reference power source (61) is set to 2 [V]. ing. Accordingly, when the load (8) is in a heavy load state and the level of the detection voltage V _RL of the load state detection resistor (57) is V _{R 1} = 1 [V] or less, a high voltage (from the RS flip-flop (63) ( H) level output signal V _FF2 is generated, the load (8) is in the light load state, and the level of the detection voltage V _RL of the load state detection resistor (57) is V _R2
= 2 [V] or more, the RS flip-flop (63) generates a low voltage (L) level output signal V _FF2 . That is,
When a high voltage (H) level output signal V _FF2 is generated from the load state detection circuit (51), the load (8) indicates a heavy state, and the load state detection circuit (51) outputs a low voltage (L) level. When the signal V _FF2 is generated, it means that the load (8) is light. Further, since the load state detection circuit (51) has a hysteresis characteristic with respect to the level of the detection voltage V _RL of the load state detection resistor (57), the level of the detection voltage V _RL of the load state detection resistor (57) is When the level is higher than V _R1 = 1 [V] and lower than V _R2 = 2 [V], the previous voltage level of the output signal V _FF2 of the RS flip-flop (63) is held.

The counter circuit (52) is a reset circuit for the transformer (2).
Flyback voltage V of the winding (2c) for detecting_FBDetection level of
Reference voltage V_THGenerating a reference power source (64),
From the reset detection winding (2c) of the transformer (2) to the delay circuit (5
Delayed signal V input via 6)_DLThe voltage of the reference voltage (6
4) Reference voltage V_THHigh voltage (H) when exceeding the level of
Level comparison output signal V_CKEdge detection controller
Input to the parameter (65) and clock input pin (CK).
Output signal V of the comparator for detecting the wedge (65)_CKThe fall of
Signal V output in synchronization with the edge_TF1Voltage level
Is inverted and input to the clear input terminal (CLR).
Output signal V of set priority RS flip-flop (17)_FF1
Signal V output in synchronization with the rising edge of_TF1of
First T flip-flop whose voltage level is reset
(66) and the first T-input input to the clock input terminal (CK)
Output signal V of the lip flop (66)_TF1Falling edge
Signal V output in synchronization with_TF2Voltage level is inverted
Reset and input to the clear input terminal (CLR)
Output signal V of priority RS flip-flop (17)_FF1Standing
Signal V output in synchronization with the rising edge_TF2Voltage level
With a second T flip-flop (67) that resets the bell
Is equipped with. That is, the first and second T flip flocks
(66,67) is the output signal of the first T flip-flop (66).
Issue V_TF1The lower bit, the second T flip-flop (67)
Output signal V_TF22-bit biner with upper bits as
Form a binary counter. In addition, the reference power supply (64)
Reference voltage V _THIs set to about 0.5 [V], for example. This
This causes the reset detection winding (2c) of the transformer (2) to be activated.
Flyback voltage V generated_FBThe number of falling edges of
Be done.

The ON signal generation circuit (53) outputs the output signal V _FF2 of the load state detection circuit (51) and the first T of the counter circuit (52).
A first AND gate (68) that outputs a logical product signal V _S1 of the output signal V _TF1 of the flip-flop (66) and an inverter that outputs an inverted signal of the output signal V _FF2 of the load state detection circuit (51). (69) and a second AND gate (which outputs an AND signal V _S2 of the output signal of the inverter (69) and the output signal V _TF2 of the second T flip-flop (67) of the counter circuit (52) ( It includes a 70), and an OR gate (71) for outputting a logical sum signal V _W1 and the output signal V _S2 of the output signal V _S1 of the first aND gate (68) second aND gate (70) There is. The logical sum signal V _W1 of the OR gate (71) is the output signal V of the maximum off-time setting circuit (54).
It is input to the OR gate (55) together with _W2 . As a result, the output signal V _FF2 of the load state detection circuit (51) is at a low voltage (L) level (light load state) and the counter circuit (52) causes the reset detection winding ( The second fall of the voltage V _{FB in} 2c) is counted to determine the first and second
Output signals V _TF1 and V _TF2 of the T flip-flops (66, 67) of
Of the reset-priority RS flip-flop () because the OR gate (71) outputs a logical sum signal V _W1 of a high voltage (H) level when each of them becomes a low voltage (L) level and a high voltage (H) level. 17) is in the set state and high voltage (H)
The ON signal V _{FF1 of the} level is transferred to the MOS-
MOS-FET (3) is added to the gate terminal of FET (3).
Turns on. Further, the output signal V _{FF2 of} the load state detection circuit (51) is at a high voltage (H) level (heavy load state) and after the reset period of the transformer (2) ends, the counter circuit (52)
Counts the first falling of the voltage V _FB of the reset detection winding (2c) and counts the first and second T flip-flops (66, 6).
Even when the output signals V _TF1 and V _{TF2 in} 7) become the high voltage (H) level and the low voltage (L) level, respectively, the logical sum of the high voltage (H) level from the OR gate (71) is obtained as described above. Signal V
_{Since W1} is output, the MOS-FET (3) is turned on.

In the configuration shown in FIG. 2, when the supply of DC power from the DC power supply (1) is started at time t ₀ shown in FIG. 3, the output signal from the maximum off-time setting circuit (54) is passed after several tens μs. V _W2 is generated, and the set terminal (S) of the reset priority RS flip-flop (17) is supplied to the set terminal (S) of the OR gate (55) as shown in FIG.
The set pulse signal V _F1S shown in is _added . As a result, the reset priority RS flip-flop (17) enters the set state, and as shown in FIG. 3 (J), the high voltage (H) level is applied to the gate terminal of the MOS-FET (3) via the drive circuit (18). The ON signal V _FF1 is given and the MOS-FET (3) is turned on. At this time, as shown in FIG.
The voltage V _DS between the drain and source terminals of ET (3) is approximately 0V
Then, as shown in FIG. 3B, the current I _D flowing through the MOS-FET (3) increases linearly and energy is stored in the transformer (2). At the same time, a negative voltage V _FB is generated in the reset detection winding (2c) of the transformer (2), and the control circuit (7)
The current output from the current mirror circuit (11) therein charges the on-time setting capacitor (12) through the backflow prevention diode (20), and the voltage V _CP across the capacitor is increased. The negative voltage V _FB generated in the reset detection winding (2c) of the transformer (2) is input to the edge detection comparator (65) in the counter circuit (52) via the delay circuit (56),
It is compared with the reference voltage V _TH of the reference power supply (64). At this time,
Since the voltage of the delay signal V _DL of the delay circuit (56) is lower than the level of the reference voltage V _TH of the reference power source (64) as shown in FIG. 3 (C), the comparison output signal of the edge detection comparator (65). V _CK
Becomes a low voltage (L) level as shown in FIG.

Time t₁Input the non-inversion of comparator (14)
ON-time setting capacitor (12) input to the input terminal (+)
Voltage V_CPIs the reference voltage V of the reference power supply (13)_REFThe level of
When it exceeds, the high voltage (H) level from the comparator (14)
A comparison output signal is generated and reset priority RS flip flow
Reset pin (R) shown in Fig. 3 (I)
Pulse signal V_F1RIs given. This will reset
The priority RS flip-flop (17) is in the reset state,
As shown in FIG. 3 (J), the MOS-F is connected via the drive circuit (18).
Off signal of low voltage (L) level at the gate terminal of ET (3)
V_FF1Is added to turn off the MOS-FET (3).
It At this time, the current I flowing through the MOS-FET (3)_DIs a figure
As shown in 3 (B), it becomes almost 0 and the drain-source
Voltage V between terminals_{D S}As shown in Fig. 3 (A),
The energy stored in the transformer (2)
It is supplied to the load (8) from the line (2b) through the rectifying and smoothing circuit (6).
Then, the transformer (2) is reset. At the same time,
Fly generated in reset detection winding (2c) of lance (2)
Back voltage V_FBDelays from rising from negative to positive
Delay signal V output from circuit (56)_DLThe voltage of Fig. 3 (C)
As shown in, it goes from negative to positive. Also, reset priority RS
Low voltage (L) level off signal of flip-flop (17)
V _FF1Is a high voltage (H) level signal due to the inverter (24)
And the discharge MOS-FET (23) is turned on.
The voltage V of the on-time setting capacitor (12)_CPIs almost 0
It descends to [V]. This allows the ratio of the comparator (14) to
The comparison output signal becomes a low voltage (L) level.

Time t_1AAt the delay signal V of the delay circuit (56)_DL
Of the voltage in the counter circuit (52) as shown in FIG.
Reference voltage V of quasi power source (64)_THHigher than the level of
As shown in FIG. 3D, the edge detection comparator (65)
Comparative output signal V_CKFrom low voltage (L) level to high voltage
(H) level. At this time, the first and second T flips
Output signal V of the flip-flop (66,67)_TF1, V_TF2Is shown in Fig. 3 (E)
And keep low voltage (L) level as shown in (F).
It Where the load (8) impedance is low and
For load status detection, load status detection circuit (51)
The voltage V of the resistor (57) _RLIs the first reference of the first reference power supply (58)
Voltage V_R1= 1 [V] or less, the first and second loads
Each output signal V of the status detection comparator (58, 61)_CP1, V
_CP2Are both low voltage (L) levels. By this,
The inverted output signal of high voltage (H) level from the converter (60) is RS
It is given to the set terminal (S) of the flip-flop (63) and
Since it is in the ON state, as shown in FIG.
High voltage (H) level output signal V from the flip-flop (63)
_FF2Is output. Therefore, the ON signal generation circuit (53)
Output signals of the first and second AND gates (67, 69) in the
V_S1, V_S2Both become low voltage (L) level, so
Low voltage (L) level OR signal V from the gate (71)_{W 1}But
Is output. Also, the maximum off time setting circuit (54) outputs
Force signal V_W2Is not generated, so
Reset priority RS flip-flop (17) set terminal
Set pulse signal V applied to (S)_F1SIs shown in Fig. 3 (H)
So that the low voltage (L) level is maintained.

Time t₂At the transformer (2) reset period
When completed, the reset detection winding (2c) of the transformer (2)
Generated flyback voltage V_FBGoes from positive to negative
Input to the counter circuit (52) as shown in FIG.
Delay signal V of the delay circuit (56) _DLThe voltage of the reference power supply (64)
Reference voltage V_THWhen it becomes lower than the level of, it is shown in Fig. 3 (D).
Output signal of edge detection comparator (65)
V_CKChanges from high voltage (H) level to low voltage (L) level
It At this time, the output signal of the first T flip-flop (66)
Issue V_TF1Is a low voltage (L) level as shown in FIG.
Becomes higher voltage (H) level and the second T flip-flop
(67) output signal V_TF2Is a low voltage as shown in Fig. 3 (F).
Hold the pressure (L) level. The first T flip-flop (6
6) High voltage (H) level output signal V_TF1Is under load
High voltage (H) level output input from the detection circuit (51)
Signal V_FF2(Fig. 3 (G)) together with ON signal generation circuit (53)
Input to the first AND gate (68) of
_S1Becomes a high voltage (H) level. In addition, the second T
Low voltage (L) level output signal V of the flip-flop (67) _TF2
Is in the ON signal generation circuit (53) from the load state detection circuit (51).
Of low voltage (L) level input through the inverter (69) of
It is input to the second AND gate (70) together with the inverted signal, and
Output signal V_S2Becomes a low voltage (L) level. According to
From the OR gate (71) in the ON signal generation circuit (53)
Voltage (H) level OR signal V_W1Is output. to this
From the OR gate (55), reset priority RS flip
The high voltage shown in Fig. 3 (H) is applied to the set terminal (S) of the rope (17).
(H) level set pulse signal V_F1SIs entered. This
At the same time, the reset priority RS flip-flop (17)
The reset terminal (R) is shown in Fig. 3 (I) from the comparator (14).
Low voltage (L) level reset pulse signal V shown_F1RBut
The reset priority RS flip-flop (1
7) is set. As a result, as shown in Fig. 3 (J).
Drive from reset priority RS flip-flop (17)
A high voltage is applied to the gate terminal of the MOS-FET (3) via the path (18).
Pressure (H) level ON signal V_FF1Is given, MOS-FE
T (3) is turned on. At this time, as shown in FIG.
Voltage between the drain and source terminals of MOS-FET (3)
V_DSBecomes almost 0V, and as shown in Fig. 3 (B), MOS-F
Current I flowing through ET (3)_DLinearly increases and the transformer
Energy is stored in (2). Reset priority RS flick
High voltage (H) level output from the flip-flop (17).
Signal V_FF1Is a low voltage (L) level due to the inverter (24)
Converted to a signal and the discharge MOS-FET (23) is off
Becomes Also, reset priority RS flip-flop (17)
High voltage (H) level ON signal V_FF1The counter times
First and second T flip-flops (66,67) in the path (52)
Input to each clear input terminal (CLR) of each
The lops (66, 67) are reset and the first and second T
Each output signal V of the flip-flop (66,67)_TF1, V_TF2Is Figure 3
As shown in (E) and (F), both are low voltage (L) level.
It At this time, energy is not supplied to the secondary winding (2b) side of the transformer (2).
During the off period of the MOS-FET (3), the transmission of Rugi is not performed.
The rectification smoothing circuit (6) smoothing capacitor (5)
The load is supplied to the load (8).

In the light load state in which the load (8) has a high impedance, the voltage V _CP of the on-time setting capacitor (12) of the control circuit (7) is the reference voltage of the reference power supply (13) at time t ₁ . V
_When the level of _REF is reached and the MOS-FET (3) is turned off, the current _ID flowing through the MOS-FET (3) becomes substantially 0 as shown in FIG. The voltage V _DS rapidly rises from 0 V as shown in FIG. 4 (A), and the energy stored in the transformer (2) is transferred to the secondary winding (2b).
Is supplied to the load (8) through the rectifying / smoothing circuit (6), and the transformer (2) is reset. At this time, the flyback voltage V _FB is generated in the reset detection winding (2c) of the transformer (2), and the counter circuit (52) is fed to the counter circuit (52) through the delay circuit (56).
The delay signal V _DL of the flyback voltage V _FB as shown in FIG. Then, at time t _1A , when the voltage of the delay signal V _DL of the delay circuit (56) becomes higher than the level of the reference voltage V _TH of the reference power source (64) as shown in FIG. ), The comparison output signal V of the edge detection comparator (65)
_CK changes from a low voltage (L) level to a high voltage (H) level. At this time, the first and second T flip-flops (66,
The output signals V _TF1 and V _TF2 of 67) both hold a low voltage (L) level as shown in FIGS. 4 (E) and 4 (F). On the other hand, the voltage V of the load state detection resistor (57) in the load state detection circuit (51)
_RL is the second reference voltage V _R2 = 2 [V] of the second reference power source (61).
Therefore, the output signals V _CP1 and V _CP2 of the first and second load state detection comparators (58, 61) are both high voltage.
(H) level. As a result, a low voltage (H) is output from the first load state detection comparator (59) via the inverter (60).
The inverted output signal of the level is applied to the set terminal (S) of the RS flip-flop (63), and the output signal V _{CP of the} high voltage (H) level from the second load state detection comparator (62) is applied to the RS flip-flop. Since the RS flip-flop (63) is put in the reset state by being applied to the reset terminal (R) of the flip-flop (63), as shown in FIG.
A low voltage (L) level output signal V _FF2 is output from (63). Therefore, since the output signals V _S1 and V _S2 of the first and second AND gates (67, 69) in the ON signal generation circuit (53) are both at a low voltage (L) level, the OR gate (71). Outputs a logical sum signal V _W1 of low voltage (L) level. Further, since the output signal V _W2 is not generated from the maximum off time setting circuit (54), the reset priority R is set through the OR gate (55).
The set pulse signal V _{F1S applied} to the set terminal (S) of the S flip-flop (17) holds a low voltage (L) level as shown in FIG. 4 (H).

Time t_1BAt transformer (2) reset period
Is completed, the primary winding (2a) of the transformer (2) and the reset
Vibration wavy ringing generated in the winding for detection (2c)
Depending on the voltage, the drain-source terminal of the MOS-FET (3)
Voltage V between_DSAnd the delay signal V of the delay circuit (56)_DLVoltage of
It decreases as shown in FIGS. 4 (A) and 4 (C). And lyce
From the input detection winding (2c) through the delay circuit (56)
Non-inverting input of edge detection comparator (65) in circuit (52)
Delay signal V input to the input terminal (+)_DLThe voltage of Fig. 4 (C)
As shown in, the reference voltage V of the reference power supply (64)_THThan the level
When it also becomes lower, the edge detection controller is set as shown in FIG.
Comparison output signal V of the palrator (65)_CKHas a high voltage (H) level
To a low voltage (L) level. At this time, the first T
Output signal V of the lip flop (66)_TF1Is shown in Fig. 4 (E)
From low voltage (L) level to high voltage (H) level
The output signal V of the second T flip-flop (67)_TF2Is
A low voltage (L) level is maintained as shown in FIG.
As a result, the high voltage of the first T flip-flop (66)
(H) level output signal V_TF1Is a load condition detection circuit (51)
Output signal V of low voltage (L) level input from
_FF2(FIG. 4 (G)) and the first in the ON signal generating circuit (53)
Input to the AND gate (68) of the output signal V_S1Is low
Voltage (L) level. In addition, the second T flip flow
Output signal V of low voltage (L) level of the top (67)_TF2Is negative
Inversion in load signal detection circuit (51) to ON signal generation circuit (53)
High voltage (H) level inversion signal input through the device (69)
Signal is input to the second AND gate (70) and its output
Signal V_S2Becomes a low voltage (L) level. Therefore,
Voltage from the OR gate (71) in the signal generator (53)
(L) level OR signal V_W1Is output and maximum
Output signal V from the time setting circuit (54) _W2Does not occur
Then, reset priority RS flip through OR gate (55)
Set pulse applied to the set terminal (S) of the flop (17)
Signal V_F1SIs a low voltage (L) level as shown in FIG.
Hold Le. This turns off the MOS-FET (3)
Hold the state.

On the reset detection winding (2c) of the transformer (2)
Due to the ringing voltage of the damped oscillation wave generated, the time t
_1CAt the reset detection winding (2c) through the delay circuit (56)
Delay signal V input to the counter circuit (52)_DLVoltage of
As shown in FIG. 4C, the reference voltage V of the reference power source (64)_THNore
When it is higher than the bell, edge detection is performed as shown in FIG.
Comparison output signal V of output comparator (65)_CKIs low again
The pressure (L) level changes to a high voltage (H) level. This and
Output signal V of the first T flip-flop (66) _TF1Is
As shown in FIG. 4 (E), the high voltage (H) level is maintained and
Output signal V of T flip-flop (67) of 2_TF2Is Figure 4
The low voltage (L) level is maintained as shown in (F).

As shown in FIG. 4C, the transformer (2)
From the set detection winding (2c) through the delay circuit (56)
Delay signal V input to the input circuit (52)_DLVoltage at time t₂
At the reference voltage V of the reference power supply (64)_THLower than the level of
Then, as shown in FIG. 4D, a comparator for edge detection
Comparative output signal V of (65)_CKIs low from high voltage (H) level
It becomes the voltage (L) level. At this time, the first T flip
Output signal V of the lop (66) _TF1Is high as shown in Fig. 4 (E).
From a high voltage (H) level to a low voltage (L) level
Output signal V of the T flip-flop (67) of_TF2Is shown in Fig. 4 (F)
As shown in, low voltage (L) level to high voltage (H) level
It will be Le. As a result, the first T flip-flop (66)
Low voltage (L) level output signal V_TF1Is the load condition detection
Low voltage (L) level output signal input from the output circuit (51)
Issue V_FF2(Fig. 4 (G)) and in the ON signal generating circuit (53)
Input to the first AND gate (68) and its output signal V_S1
Becomes a low voltage (L) level. Also, the second T flip
High voltage (H) level output signal V of flop (67)
_TF2From the load state detection circuit (51) to the ON signal generation circuit (5
3) High voltage (H) level input via the inverter (69) in
Input to the second AND gate (70) together with the inverted signal of
And its output signal V_S2Becomes a high voltage (H) level. Shi
Therefore, the OR gate (71) in the ON signal generation circuit (53)
Higher voltage (H) level OR signal V_W1Is output
Both output signals V from the maximum off time setting circuit (54) _W2From
Reset priority R via OR gate (55)
It is given to the set terminal (S) of the S flip-flop (17).
Set pulse signal V_F1SIs low as shown in Fig. 4 (H).
The pressure (L) level changes to a high voltage (H) level. Same as this
Sometimes, reset priority RS flip-flop (17) reset
The comparator (14) is connected to the low terminal (R) as shown in Fig. 4 (I).
Voltage (L) level reset pulse signal V_F1RIs entered
Reset priority RS flip-flop (17)
It will be in a state of shutting down. As a result, as shown in FIG.
Set priority RS flip-flop (17) to drive circuit (18)
High voltage (H) to the gate terminal of MOS-FET (3) via
Level ON signal V_FF1Is added, MOS-FET (3)
Turns on. At this time, as shown in FIG.
Voltage V between the drain and source terminals of OS-FET (3)_DSBut
It becomes almost 0V, and as shown in Fig. 4 (B), MOS-FET (3)
Current I flowing through_DIs increased linearly to the transformer (2).
Rugi is accumulated. Reset priority RS flip-flop
High voltage (H) level ON signal V output from (17)
_FF1Is the first and second T-flip in the counter circuit (52).
Input to each clear input terminal (CLR) of the flip-flop (66, 67).
Reset each T flip-flop (66, 67),
And each output signal V of the second T flip-flop (66, 67)
_TF1, V_TF2Is low, as shown in FIGS. 4 (E) and (F).
It becomes the pressure (L) level. At this time, the secondary winding of the transformer (2)
Energy is not transmitted to the line (2b) side, and MOS-FE
Smoothing capacitor of the rectifying and smoothing circuit (6) during the off period of T (3)
The electric charge charged in (5) is supplied to the load (8).

Here, the load state in the load state detection circuit (51)
Voltage V of resistance (57) for state detection_RLIs the first reference power source
The first reference voltage V of (58)_R1Higher than = 1 [V] and second
Second reference voltage V of the reference power source (61) of_R2= Lower than 2 [V]
The output of the first load condition detection comparator (59)
Force signal V_CP1Becomes high voltage (H) level and the second
Output signal V of load status comparator (62)_CP2Is low
Voltage (L) level. 1st load condition detection computer
High voltage (H) level output signal V of the transmitter (59) _CP1Is anti
Converted to a low voltage (L) level by the converter (60)
It is input to the set terminal (S) of the lip flop (63) and the second
The low voltage (L) level of the load condition detection comparator (62)
Output signal V_CP2Is the reset of the RS flip-flop (63)
Input to the input terminal (R). At this time, RS flip
Output signal V of the rope (63)_FF2Is a resistance for load condition detection (57)
Voltage V_RLIs the first reference voltage V of the first reference power source (58)_R1
The previous voltage level, that is, low voltage until = 1 [V] or less
Hold the pressure (L) level. Also, contrary to the above, heavy load
Resistance for load status detection in the load status detection circuit (51)
Voltage V of (57)_RLRises to the first of the first reference power supply (58)
Reference voltage V_R1Higher than = 1 [V] and the second reference power source (6
Second reference voltage V of 1)_R2= 2 [V] lower than
Output signal V of RS flip-flop (63)_FF2Is the load
Voltage V of status detection resistor (57)_RLOf the second reference power source (61)
Second reference voltage V_R2= Previous voltage until it exceeds 2 [V]
The level, that is, the high voltage (H) level is held. In addition, negative
DC voltage V applied to the load (8)_OTo stabilize the
As for the conventional switching power supply device shown in FIG.
The description is omitted because it is substantially the same as the case.

In the present embodiment, the load state detection circuit (51)
When a heavy load state is detected by outputting a high voltage (H) level output signal V _FF2 from the transformer, the flyback energy of the transformer (2) is relatively long after the MOS-FET (3) is turned off. Rectifying and smoothing circuit (6) from secondary winding (2b)
Since it is supplied to the load (8) via the, the reset period of the transformer (2) becomes long. As a result, a wide voltage pulse is generated in the reset detection winding (2c) of the transformer (2), so that when the counter circuit (52) counts the first falling edges of the wide voltage pulse, that is, the counter circuit ( 52) 1st
And each output signal V of the second T flip-flop (66, 67)
_TF1 and V _TF2 are high voltage (H) level and low voltage, respectively
When it goes to the (L) level, the ON signal generation circuit (53) outputs O
R gate (71), reset priority RS flip-flop (17)
By applying the high voltage (H) level ON signal V _FF1 to the gate terminal of the MOS-FET (3) through the drive circuit (18), the MO-FET is turned on after the reset period of the transformer (2).
A normal ringing choke converter (RCC) operation for switching the S-FET (3) from the off state to the on state is performed. Further, when the low-voltage (L) level output signal V _FF2 is output from the load state detection circuit (51) and the light load state is detected, the transformer (2) is turned off after the MOS-FET (3) is turned off. Since the flyback energy is supplied to the load (8) from the secondary winding (2b) through the rectifying and smoothing circuit (6) within a relatively short period, the reset period of the transformer (2) is shortened. This allows the reset detection winding (2
Since a narrow voltage pulse including the ringing voltage is generated in c), when the counter circuit (52) counts the second falling edge of the narrow voltage pulse, that is, the first in the counter circuit (52). And an ON signal generation circuit (53) when the output signals V _TF1 and V _{TF2 of} the second T flip-flops (66, 67) become a low voltage (L) level and a high voltage (H) level, respectively.
From the OR gate (71), the reset priority RS flip-flop (17) and the drive circuit (18) to the ON terminal V _FF1 of high voltage (H) level to the gate terminal of the MOS-FET (3) , The off period of the MOS-FET (3) is extended and the switching frequency of the MOS-FET (3) is lowered. Therefore, the number of times the MOS-FET (3) is turned on and off is reduced, and the impedance of the load (8) is high.
Since the switching loss generated in the OS-FET (3) can be reduced, it is possible to improve the conversion efficiency of the switching power supply device in a wide load range. Further, the level of the voltage V _RL of the load state detection resistor (57) in the load state detection circuit (51) is changed from the level of the first reference voltage V _R1 or the second reference voltage V _R2 to the first reference voltage V _{R2. Since} the hysteresis characteristic holds the voltage level of the output signal V _FF2 of the load state detection circuit (51) at the previous voltage level even when a period in which the level is between _R1 and the second reference voltage V _R2 occurs, There is an advantage that the heavy load state and the light load state can be smoothly switched, and the noise due to the vibration of the core of the transformer (2) can be prevented. Further, when the flyback voltage V _FB generated in the reset detection winding (2c) of the transformer (2) is extremely small at the time of startup and the falling of the flyback voltage V _FB cannot be detected, the maximum off-time setting circuit (54) to MOS-FET
ON signal MO of high voltage (H) level is applied to the gate terminal of (3).
The S-FET _{F F1} is added, and the MOS-FET (3) is forcibly changed from the off state to the on state. As a result, the voltage V _O of the load (8) rises, and thereafter, the normal ringing choke converter (RCC) synchronized with the fall of the flyback voltage V _FB of the reset detection winding (2c) of the transformer (2). )
Since the operation is shifted to the operation, there is an advantage that the switching power supply device can be smoothly started. Further, by delaying the falling point of the voltage V _FB of the reset detection winding (2c) with the delay circuit (56), the lowest point of the voltage V _DS between the drain and source terminals of the MOS-FET (3). And reset detection winding (2c)
Since the fall time of the voltage V _FB of the MOS-FET (3) is matched with the fall time of the flyback voltage V _FB of the reset detection winding (2c) of the transformer (2), the MOS-FET (3) is changed from the OFF state to the ON state. Therefore, when the voltage V _DS between the drain and source terminals of the MOS-FET (3) becomes the minimum, it is switched to the ON state. Therefore, it is possible to minimize the switching loss and improve the conversion efficiency.

The embodiment of the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the load is detected by the detection signal of the output voltage detection circuit (10).
Although the form using the load state detection circuit (51) for detecting the state of (8) is shown, as shown in FIG. 5, a current detector (72) for detecting the current I _O flowing through the load (8) is provided. , Current detector (7
The detection output of 2) is converted to the load state detection voltage V _RL by the load state detection resistor (57) in the load state detection circuit (51) and the load
The state of (8) may be detected. Further, in the above embodiment, two reference power sources (58, 61) and comparators (59, 62) and
The inverter (60) and the RS flip-flop (63) form a 1-bit load state detection circuit (51) and the T flip-flops (66, 67) are connected in two stages to form a counter circuit (52). However, the number of bits of the load state detection circuit (51) may be increased and two or more stages of T flip-flops may be connected to perform more precise control of the switching frequency. In the above embodiment, the transformer (2) in which the primary winding (2a), the secondary winding (2b) and the reset detecting winding (2c) are independently formed is used. However, it is also possible to configure the reset detection winding (2c) as a part of the primary winding (2a) or the secondary winding (2b). Furthermore,
In the above embodiment, the main switching element is a MOS-
Although the form using the FET is shown, a bipolar transistor, an IGBT (insulated gate type bipolar transistor), a J-FET (junction type field effect transistor) or a thyristor can also be used as the main switching element.

[0030]

According to the present invention, when the load impedance becomes high and the load state becomes light, the switching frequency decreases and the number of times the main switching element is turned on and off decreases, so that the switching loss at light load can be reduced. It is possible to improve the conversion efficiency in a wide load range. Also, since the main switching element is switched from the off state to the on state when the voltage of the transformer reset detection winding falls, it may be switched to the on state when the voltage between both main terminals of the main switching element becomes the minimum. Therefore, the switching loss can be minimized. Furthermore, according to the present invention, since the control circuit can be configured mainly by a logic integrated circuit (logic IC) such as an OR gate, an AND gate, an inverter, a comparator, and various flip-flops, a CMOS-IC (which consumes extremely little power) CMOS
It is possible to reduce the power loss of the switching power supply device by configuring the control circuit with a die integrated circuit).

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of a switching power supply device according to the present invention.

FIG. 2 is an electric circuit diagram showing details of the configuration of FIG.

FIG. 3 is a waveform diagram showing the voltage and current of each part of FIG. 2 under heavy load.

FIG. 4 is a waveform diagram showing the voltage and current of each part of FIG. 2 under a light load.

5 is an electric circuit diagram showing a modified embodiment of FIG.

FIG. 6 is an electric circuit diagram showing a conventional switching power supply device.

FIG. 7 is a waveform diagram showing the voltage and current of each part of FIG. 6 under heavy load.

FIG. 8 is a waveform diagram showing the voltage and current of each part of FIG. 6 under a light load.

[Explanation of symbols]

(1) ・ ・ DC power supply, (2) ・ ・ Transformer, (2a) ・ ・ Primary winding, (2b) ・ ・ Secondary winding, (2c) ・ ・ Reset detection winding, (3) ・・ MOS-FET (main switching element), (4) ・ ・ Rectifying diode, (5) ・ ・ Smoothing capacitor, (6) ・ ・ Rectifying and smoothing circuit, (7) ・ ・ Control circuit,
(8) ・ ・ Load, (9) ・ ・ Photocoupler, (9a) ・ ・ Light emitting part, (9b) ・ ・ Light receiving part, (10) ・ ・ Output voltage detection circuit,
(11) ・ ・ Current mirror circuit, (12) ・ ・ On-time setting capacitor, (13) ・ ・ Reference power supply, (14) ・ ・ Comparator, (15) ・ ・ Voltage rising detection circuit, (16)
・ ・ Oscillation circuit, (17) ・ ・ Reset priority RS flip-flop, (18) ・ ・ Drive circuit, (19) ・ ・ On-time determining circuit, (20,21) ・ ・ Backflow prevention diode, (22) ・
・ Resistance, (23) ・ ・ Discharge MOS-FET, (24) ・ ・
Inverter, (51) .. Load state detection circuit (load state detection means), (52) .. Counter circuit (counter means), (5
3) .. ON signal generating circuit (ON signal generating means), (54)
..Maximum off-time setting circuit (maximum off-time setting means)
(55) ・ ・ OR gate, (56) ・ ・ Delay circuit, (57) ・
・ Load state detection resistor, (58) ・ ・ First reference power supply,
(59) ... First load condition detection comparator, (60)
・ Inverter, (61) ・ ・ Second reference power source, (62) ・ ・ Second
Load state detection comparator, (63) .. RS flip-flop, (64) .. reference power supply, (65) .. edge detection comparator, (66) .. first T flip-flop, (67).・ Second T flip-flop, (68) ・ ・
1st AND gate, (69) .. inverter, (70) .. 2nd AND gate, (71) .. OR gate, (72) .. current detector

Claims (4)

(57) [Claims] 1. A primary winding and a main switching element of a transformer connected in series to a DC power source, and a rectifying / smoothing circuit connected to a secondary winding of the transformer and supplying a DC output to a load. A reset detection winding electromagnetically coupled to the primary or secondary winding, and a control circuit for ON / OFF controlling the main switching element are provided, and the control circuit is provided after the main switching element is turned off. When the reset period of the transformer is detected by the voltage generated in the reset detection winding, the main switching element is turned on after the reset period ends, and the level of the voltage of the load exceeds the level of the reference voltage. In the switching power supply device that keeps the level of the DC output constant by turning off the main switching element, Load state detection means for detecting a light load state of the load or a state other than the light load based on a voltage of the load or a current flowing through the load; and a counter means for counting the number of times the voltage of the reset detection winding falls. When the load state detecting means detects a light load state and the counter means counts the second and subsequent falling edges of the flyback voltage of the reset detecting winding after the reset period of the transformer is finished, or the load state An ON signal is given to the control terminal of the main switching element when the detection means detects a state other than the light load and the counter means counts the first falling of the flyback voltage of the reset detection winding. A switching power supply device comprising an ON signal generating means. 2. The switching power supply device according to claim 1, wherein the load state detecting means has a hysteresis characteristic with respect to a voltage of the load or a current flowing through the load. 3. The maximum off-time for which the control circuit gives an ON signal to the control terminal of the main switching element when the count signal is not output from the counter means within the switching cycle after the main switching element is turned off. The switching power supply device according to claim 1, further comprising setting means. 4. The control circuit has a delay circuit that delays the falling time of the voltage of the reset detection winding, and is the lowest point of the voltage applied between both main terminals of the main switching element. The switching power supply device according to any one of claims 1 to 3, wherein a time point when the voltage of the reset detection winding falls is substantially the same.