JP3488208B2 - Active bias circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to active bias circuits, and more specifically to Wilson.
Type bias current circuit and a Widlar type constant current circuit are combined.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional structure of an active bias circuit which is a combination of a Wilson type constant current circuit and a Widlar type constant current circuit. As shown in FIG.
This conventional active bias circuit 10 has four n
-Channel field effect transistors M11, M12, M1
3, M14 and a resistor R11.

The transistors M11 and M14 have what is called a diode connection, and their gates and drains are connected to each other at points P1 and P2. The drain of the transistor M11 is connected to the terminal T1 via the resistor R11.
, Whose gate is further connected to the gate of transistor M13. The source of the transistor M11 is connected to the drain of the transistor M12 below it. The gate and the source of the transistor M12 are connected to the gate and the source of the transistor M14, respectively. The sources of the transistors M12 and M14 connected to each other are grounded. Thus, the transistors M11 and M12 on the input side (reference voltage supply side) are cascode-connected.

The drain of the transistor M13 has a terminal T
Connected to 2. The source of the transistor M13 is
It is connected to the drain of the transistor M14 at the connection point P2. The gate and drain of the transistor M14 are also connected to each other at the connection point P2. The output terminal T3 of the active bias circuit 10 is connected to the connection point P2. In this way, the transistors M13 and M14 on the output side are also cascode-connected.

A reference voltage V ₁ is applied to the terminal T1, which causes a reference current I _REF to flow through the resistor R11. In other words, the reference current I _REF is generated by the reference voltage V ₁ and the resistor R11. Transistors M11 and M12
Assuming that no current flows through the gate of, the reference current I _REF becomes equal to the drain currents I _D11 and I _D12 of the transistors M11 and M12, respectively.

A bias voltage V ₂ is applied to the terminal T2. As a result, a constant drain current I _D13 flows through the transistor M13, but the current value of the drain current I _D13 has a predetermined ratio with respect to the reference current I _REF . That is, the current value of the drain current I _D13 is a times the current value of the reference current I _REF (a is a positive constant). Considering that no current flows through the gates of the transistors M13 and M14, the drain current I _D13 becomes equal to the drain current I _D14 of the transistor M14.

The output bias voltage V _OUT of the conventional bias circuit 10 is generated at the output terminal T3, and its voltage value is a connection point between the gate and drain of the transistor M14 (that is, the drain of the transistor M14 and the transistor M13). Point of connection with the source) of P2) equal to the voltage value of P2.

The biased circuit 20 to which a desired bias voltage V _OUT is applied by the bias circuit 10 is an n-channel enhancement type field effect transistor M.
Includes 15. The gate of the transistor M15 is connected to the output terminal T3 of the bias circuit 10, and the output bias voltage V _OUT is applied. Transistor M15
Has a drain connected to the terminal T4 and is applied with the voltage V _D. The source of the transistor M15 is grounded. Therefore, the gate-source voltage of the transistor M15 becomes equal to the output bias voltage V _OUT , and as a result, the drain current I _D15 of the transistor M15 increases / decreases according to the value of the output bias voltage V _OUT .

The biased circuit 20 has a function of inputting a high frequency signal (in input terminal), amplifying and outputting (out output terminal), and includes an active element and a passive element in addition to the field effect transistor M15. However, it is omitted here.

The operation of the conventional bias circuit 10 shown in FIG. 6 will be briefly described as follows.

By properly setting the resistance value of the reference resistor R11 with respect to a predetermined reference voltage V ₁ (for example, 2 V), the value of the reference current I _REF flowing through the transistor M11 can be set to a desired value. Further, as a result, the connection point between the gate and the drain of the transistor M11 (that is, the connection point between the resistor R11 and the drain of the transistor M11).
The value of the voltage V _P1 occurring at _P1 is determined. At this time, the voltage V at the connection point P2 (that is, the output terminal T3) between the source of the transistor M13 and the drain of the transistor M14
_P2 is equal to the value of the bias voltage V ₂ applied to the terminal T2 _minus the forward voltage drop V _FM13 of the transistor M13. That is, the following expression (1) is established.

V _P2 = V _OUT = V ₂ −V _FM13 (1) On the other hand, when the value of the reference voltage V ₁ applied to the terminal T _1, that is, the reference current I _REF is changed, the current value of the drain current _ID 13 of the transistor M 13 is changed. _Changes , and the voltage value of the forward voltage drop V _FM13 of the transistor M13 changes accordingly. Therefore, as is clear from the equation (1), by changing the value of the reference voltage V ₁ , it is possible to change the value of the output bias voltage V _OUT while keeping the value of the bias voltage V ₂ constant.

Transistor M15 of biased circuit 20
The value of the drain current I _D15 of the transistor changes according to the value of the output bias voltage V _OUT applied to the gate of the transistor M15. Since the transistor M15 is an enhancement type, if the absolute value of the output bias voltage V _OUT is set below the threshold voltage of the transistor M15, the value of its drain current I _D15 can be zero, that is, the transistor M15 is cut. It is possible to turn it off.

The conventional active bias circuit 1 of FIG.
The operation of 0 is caused by the manufacturing process of the transistor M1.
It hardly changes with respect to the fluctuation (variation) of the threshold voltage _Vth of 1, M12, M13, and M14 and the fluctuation of the ambient temperature. That is, even if these variations occur, the value of the drain current I _D15 flowing in the transistor M15 of the biased circuit 20 hardly changes and is kept substantially constant unless the parameters of the circuit 10 are changed.

For example, transistors M11, M12, M
When the absolute value of the threshold voltage _Vth of M13 and M14 decreases, the value of the reference current I _REF increases accordingly, and the voltage V _{P1 at the} point P1 decreases. On the other hand, the reference current I
_Since the value of the drain current I _D13 of the transistor M13 increases as the value of _REF increases, the transistor M13 increases.
The value of the voltage drop due to increases, as a result, the value of the voltage V _P2 that is, the output bias voltage V _OUT at the point P2 is reduced. Conversely, transistors M11, M12, M1
3, when the absolute value of the threshold voltage V _th of M14 becomes large, the value of the reference current I _REF becomes small accordingly, so that the voltage VP1 at the point P1 rises. On the other hand, the reference current I
_Since the value of the drain current I _D13 of the transistor M13 decreases as the value of _REF decreases, the transistor M13
The value of the voltage drop due to decreases, so that the value of the voltage V _P2 that is, the output bias voltage V _OUT at the point P2 increases. Thus, the circuit 10 keeps the drain currents I _D13 and I _D14 flowing through the transistors M13 and M14 and the drain current I _D15 of the biased circuit transistor M15 constant against variations in the absolute value of the threshold voltage V _th. .

Further, even when the ambient temperature changes, the same operation as when the threshold voltage V _th changes is performed, so that the value of the drain current I _D15 of the transistor M15 is kept constant in this case as well.

[0017]

However, the conventional active bias circuit 10 shown in FIG. 6 has the following problems.

That is, in the conventional bias circuit 10,
The power consumption of the biased circuit 20, that is, the transistor M15 can be adjusted by changing the value of the reference voltage V ₁ applied to the terminal T1. This is because when the value of the reference voltage V ₁ is changed, the value of the output bias voltage V _OUT changes accordingly, and as a result, the value of the drain current I _D15 flowing through the transistor M15 also changes.

The bias circuit 10 is used, for example, to apply a desired bias voltage to an amplifier in a mobile phone. In this case, the biased circuit 20 serves as a high frequency amplifier in the mobile phone.

Generally, in a mobile phone, during normal operation, the voltage V _D is supplied to the transistor M15 through the terminal T4, and the bias circuit 10 outputs the output bias voltage V _OUT of a desired value to the transistor M15.
As a result, the biased circuit 20 (ie, high frequency amplifier)
Is supplied to. On the other hand, in the power saving operation, in order to stop the operation of the transistor M15 (that is, the circuit 20),
A separate switch (so-called drain switch,
(Not shown) allows the voltage V
Supply of _D is stopped. Therefore, there is a problem that the number of circuit components increases due to the provision of the switch. There is also a problem that electric power is required to operate the switch.

Therefore, the voltage value of the output bias voltage V _OUT of the bias circuit 10 is made lower than the threshold voltage of the transistor M15 so that the operation of the transistor M15 and by extension the biased circuit 20 is stopped, and thus the drain switch is turned on. It is expected to be unnecessary.
However, in portable electric appliances, there are cases where the value of the reference voltage V ₁ applied to the terminal T1 cannot be set to 0 V due to the circuit configuration, and in that case, the output bias voltage V _OUT
There is a problem that the life of the battery in the mobile phone is shortened because it is not possible to save power by cutting off the value of the value lower than the threshold voltage of the transistor M15 and cutting it off.

Further, since the value of the output bias voltage V _OUT cannot be made sufficiently low, the RF output cannot be sufficiently reduced when the transistor M15 is operated at a low RF output. In other words, there is a problem that the range in which the RF output of the transistor M15 can be changed is narrow depending on the value of the reference voltage V ₁ .

The present invention has been made in view of the above circumstances, and an object thereof is to provide an output even if the absolute value of the reference voltage applied to generate the reference current does not reach 0V. An object of the present invention is to provide an active bias circuit capable of setting the absolute value of the bias voltage to almost 0V.

Another object of the present invention is to provide an active bias circuit which can further widen the variable range of the RF output of the biased circuit which can be changed by changing the value of the reference voltage.

Still another object of the present invention is to provide an active bias circuit capable of reliably interrupting a current flowing through a biased circuit including an enhancement type active element without providing a dedicated switch for interrupting the current. Especially.

Still another object of the present invention is to provide an active bias circuit which eliminates the need for an external switch for the biased circuit, reduces the number of parts in the mobile phone handset set as a whole, and reduces the cost and the volume of the device. To provide.

Still another object of the present invention is to provide an active bias circuit which can reduce the number of parts and suppress power consumption, thereby extending the talk time and waiting time of a portable telephone handset. Especially.

Still another object of the present invention is to provide an active bias circuit which widens the variable range of the output power by reducing the current consumption of the biased circuit and controlling the output power by the reference voltage. is there.

[0029]

(1) A first active bias circuit according to the present invention comprises a diode-connected first transistor, to which a reference current is supplied via a first resistor, and the first active bias circuit. A third transistor having a second transistor cascode-connected to the transistor and a control terminal connected to the control terminal of the first transistor, through which a constant current having a current value of a predetermined ratio with respect to the reference current flows, A diode-connected fourth transistor which is cascode-connected to the third transistor and has a control terminal connected to the control terminal of the second transistor, and which is provided at a connection point of the third transistor and the fourth transistor. An output bias voltage is output from the formed output terminal, and the output bias voltage is cascode-connected to the first transistor. A second bias connected between the control terminal of the first transistor and the control terminal of the third transistor in an active bias circuit that changes according to the value of a reference voltage applied to the transistor and the second transistor. A resistor is provided, and the absolute value of the output bias voltage is reduced according to the value of the voltage drop by using the voltage drop caused by the current flowing through the second resistor. .

(2) In the first active bias circuit of the present invention, the second resistor is connected between the control terminal of the first transistor and the control terminal of the third transistor, and the second resistor is connected. The absolute value of the output bias voltage is reduced according to the value of the voltage drop by utilizing the voltage drop caused by the current flowing through the container.

Therefore, for example, when the first and third transistors are field effect transistors, a leakage current flows between the gate of the first transistor and the gate of the third transistor, so that the second resistor is connected. A voltage drop occurs in the container depending on the value of its leakage current. Also, when the first and third transistors are bipolar transistors, a base current flows between the base of the first transistor and the base of the third transistor, so that the second resistor is connected to the base current. A voltage drop occurs according to the value of the base current. Therefore, the absolute value of the output bias voltage decreases according to the value of the voltage drop.

As a result, even if the absolute value of the reference voltage applied to generate the reference current does not reach 0V, the absolute value of the output bias voltage can be almost 0V. As a result, the current flowing in the biased circuit including the enhancement-type voltage-driven active element can be cut off without providing a dedicated switch for cutting off the current.

The absolute value of the output bias voltage is
Since it becomes smaller according to the value of the voltage drop caused by the second resistor, the variable range of the power consumption of the biased circuit that can be changed by the value of the reference voltage can be expanded to the lower side.

Since the second resistor is connected between the control terminal of the first transistor and the control terminal of the third transistor, the first active resistor of the present invention is connected.
The operation of the bias circuit (ie stable supply of bias voltage) is not affected by the addition of the second resistor.

(3) In a preferred example of the first active bias circuit of the present invention, when the absolute value of the reference voltage approaches 0V from a predetermined value, the absolute value of the reference voltage reaches 0V. First, the absolute value of the output bias voltage is set to 0V.

In another preferred example of the first active bias circuit of the present invention, the output bias voltage is designed to be applied to a control terminal of an enhancement type and voltage driven active element. When the absolute value of the reference voltage approaches 0V from a predetermined value, the output bias voltage reaches a value capable of cutting off the active element before the absolute value of the reference voltage reaches 0V. .

(4) In the second active bias circuit of the present invention, a diode-connected first transistor, to which a reference current is supplied via a first resistor, and a cascode connection to the first transistor. A third transistor having a second transistor and a control terminal connected to the control terminal of the first transistor, through which a constant current having a current value of a predetermined ratio with respect to the reference current flows, and a cascode connection to the third transistor. And a diode-connected fourth transistor having a control terminal connected to the control terminal of the second transistor.
The output bias voltage is output from the output terminal formed at the connection point of the transistor and the fourth transistor,
The first output bias voltage is cascode-connected.
In an active bias circuit that changes according to the value of a reference voltage applied to a transistor and the second transistor, one terminal is commonly connected to the control terminal of the second transistor and the control terminal of the fourth transistor. A second resistor, and by shunting a part of the current flowing through the third transistor to the second resistor, the value of the voltage drop generated by the fourth transistor is reduced. The absolute value of the output bias voltage is reduced according to the value of the voltage drop.

(5) In the second active bias circuit of the present invention, a second resistor having one terminal commonly connected to the control terminal of the second transistor and the control terminal of the fourth transistor is provided. There is. Then, by shunting a part of the current flowing through the third transistor to the second resistor, the value of the voltage drop generated by the fourth transistor is reduced, and thus the absolute value of the output bias voltage is reduced to the voltage. I am trying to decrease according to the value of the descent. Therefore, even if the absolute value of the reference voltage applied to generate the reference current does not reach 0V, the absolute value of the output bias voltage can be approximately 0V. As a result, the current flowing in the biased circuit including the enhancement-type voltage-driven active element can be cut off without providing a dedicated switch for cutting off the current.

The absolute value of the output bias voltage is
Since the voltage decreases with the decrease in the voltage drop generated by the fourth transistor, the variable range of the power consumption of the biased circuit that can be changed according to the value of the reference voltage can be expanded to the lower side.

It should be noted that one terminal of the second resistor is commonly connected to the control terminal of the second transistor and the control terminal of the fourth transistor, and a part of the current flowing in the third transistor is part of the current. The operation of the second active bias circuit of the present invention (i.e., stable supply of bias voltage) is not affected by the addition of the second resistor because it only diverts to the second resistor.

(6) In a preferred example of the second active bias circuit of the present invention, the resistance value of the second resistor is set smaller than the resistance value of the fourth transistor.

In another preferable example of the second active bias circuit of the present invention, before the absolute value of the reference voltage reaches 0V when the absolute value of the reference voltage approaches 0V from a predetermined value. And the absolute value of the output bias voltage is 0
Set to V.

In still another preferred example of the second active bias circuit of the present invention, the output bias voltage is designed to be applied to a control terminal of an enhancement type and voltage driven active element. When the absolute value of the reference voltage approaches 0V from a predetermined value, the output bias voltage reaches a value capable of cutting off the active element before the absolute value of the reference voltage reaches 0V. To do.

(7) In the third active bias circuit of the present invention, the drain and gate are short-circuited in the active bias circuit that supplies a bias voltage to the biased circuit that inputs, amplifies and outputs a high frequency signal. A first MOS transistor having a drain connected to a reference power source through a reference resistor, and the first MO transistor.
A second MOS transistor whose drain is connected to the source of the S transistor and whose source is grounded; and a third MOS transistor whose drain is connected to a bias power supply and whose gate is connected to the gate of said first MOS transistor; and drain , The gate is short-circuited, the drain is connected to the source of the third MOS transistor, and the source is connected between the fourth MOS transistor having the source grounded and the gates of the second and fourth MOS transistors and the ground. A shunt resistor, a bias circuit output section for extracting the bias voltage from the connection point of the third and fourth MOS transistors, an input terminal for the high frequency signal is connected to the bias circuit output section, and the biased circuit of the biased circuit is connected. A switch for shunting leakage current to the shunt resistor. It is characterized by having a block.

(8) In the switching block of the active bias circuit according to the present invention, a sixth MOS transistor having a drain connected to the bias circuit output section and a source grounded, and a drain and a gate having the sixth MOS transistor are provided. A seventh MOS transistor having a source connected to the gate and a drain connected to the gate of the sixth MOS transistor.
An OS transistor, a first resistor connected between the drain of the eighth MOS transistor and the drain of the fifth MOS transistor in the biased circuit, and a source connected to the ground of the eighth MOS transistor and ground. It can be formed by a second resistor and a third resistor connected between the reference power source and the gate of the eighth MOS transistor.

[0046]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 shows the configuration of an active bias circuit 1 according to the first embodiment of the present invention. This active bias circuit 1 has a configuration in which a Wilson type constant current circuit and a Widlar type constant current circuit are combined, and has four n-channel field effect transistors M1.
It is provided with M2, M3, M4, a resistor R1, and a resistor R2. The resistor R1 is used to generate the reference current. Resistor R2 is used to lower the gate voltage of transistor M3 below that of transistor M1.

The transistors M1 and M4 have their gates and drains connected to each other and have what is called a diode connection. The drain of the transistor M1 is connected to the terminal T1 via the resistor R1. The gate of the transistor M1 is connected to the gate of the transistor M3 via the resistor R2. The source of the transistor M1 is connected to the drain of the transistor M2 below it. The gate and the source of the transistor M2 are connected to the gate and the source of the transistor M4, respectively. The sources of the transistors M2 and M4, which are connected to each other, are grounded. Thus, the transistors M1 and M2 on the input side (reference voltage supply side) are cascode-connected. The resistance value of the resistor R2 is 1 kΩ here.
There is.

The drain of the transistor M3 is connected to the terminal T2.
It is connected to the. The source of the transistor M3 is connected to the drain of the transistor M4 at the connection point P2. The gate and drain of the transistor M4 are also connected to each other at the connection point P2. The connection point P2
Is connected to the output terminal T3 of the active bias circuit 10. In this way, the output transistor M
13 and M14 are also cascode-connected.

The reference voltage V ₁ is applied to the terminal T1 connected to the drain of the transistor M1 via the resistor R1, whereby the reference current I _REF flows through the resistor R1. In other words, the reference voltage V ₁ and the resistor R1 generate the reference current I _REF . Assuming that no current flows through the gates of the transistors M1 and M2, this reference current I
_REF becomes equal to the drain currents I _D1 and I _D2 of the transistors M1 and M2, respectively.

A bias voltage V ₂ is applied to the terminal T2 connected to the drain of the transistor M3. Accordingly, the drain current I _D3 having a current value of a predetermined ratio (a times) with respect to the reference current I _REF can flow through the transistor M3. Considering that no current flows through the gates of the transistors M3 and M4, the drain current I _D3 becomes equal to the drain current I _D4 of the transistor M4. The output bias voltage V _OUT generated at the output terminal T3 of the bias circuit 1 is equal to the voltage V _P2 at the connection point P2 between the drain and gate of the transistor M4.

The biased circuit 2 to which a desired bias voltage is applied by the active bias circuit 1 is n-
It includes a channel enhancement type field effect transistor M5. The gate of the transistor M5 is connected to the output terminal T3 of the bias circuit 1, and the output bias voltage V _OUT is applied. The drain of the transistor M5 is connected to the terminal T4, and the voltage V _D is applied. The source of the transistor M5 is grounded. Therefore, the gate-source voltage of the transistor M5 becomes equal to the output bias voltage V _OUT , and as a result, the drain current I _D5 of the transistor M5 becomes equal to the output bias voltage V _OUT.
Increases / decreases according to the value of.

The biased circuit 2 has a function of inputting a high frequency signal (in input terminal), amplifying and outputting (out output terminal), and includes an active element and a passive element in addition to the field effect transistor M5. However, it is omitted here.

The operation of the active bias circuit 1 shown in FIG. 1 will be briefly described below.

For a given reference voltage V1, resistor R1
By properly setting the resistance value of
The reference current I _REF flowing through 1 can be determined to a desired value. This also determines the value of the voltage V _P1 generated at the connection point P1 between the resistor R1 and the drain of the transistor M1. In this bias circuit 1, since the resistor R2 is inserted between the gate of the transistor M1 and the gate of the transistor M3, leakage current flows from the gate of the transistor M1 to the gate of the transistor M3 through the resistor R2, and results in a drop V _R. Thus, the gate voltage of transistor M3, than the gate voltage of the transistor M1 becomes lower by that voltage drop V _R. As a result, the voltage V _{P2 at the} point P2, that is, the output bias voltage V _{OUT at the} output terminal T3 is reduced by the voltage drop V _{R as} compared with the case of the conventional bias circuit 10 represented by the equation (1). That is, the following expression (2) is established.

V _OUT = V _P2 = V ₂ −V _FM3 −V _R (2) where V _FM3 is the forward voltage drop of the transistor M ₃ .

Therefore, the reference voltage applied to the terminal T1 is
Pressure V₁ That is, the reference current I_REF If you change the value of
Drain current I of transistor M3_D3Changes accordingly
Voltage drop V of transistor M3_FM3 The voltage value of changes
And output bias voltage V_OUTThe value of changes. Thus
As in the case of the conventional bias circuit 10, the reference voltage V ₁ 
Output bias voltage V_OUT The value of the
Can be changed.

The drain current I _D5 of the transistor M5 of the biased circuit 2 changes according to the value of the output bias voltage V _OUT applied to the gate of the transistor M5. Since the transistor M5 is an enhancement type, if the absolute value of the output bias voltage V _OUT is set to about 0 V (that is, less than the threshold voltage of the transistor M5), the value of the drain current I _D5 can be zero, that is, , The transistor M5 can be cut off.

In the active bias circuit 1 shown in FIG.
Since the resistor R2 does not affect its operation, the variation (variation) of the threshold voltage V _th of the transistors M1, M2, M3, M4 due to the manufacturing process is the same as in the conventional bias circuit 10 of FIG. And stable operation with respect to fluctuations in ambient temperature. That is, even if these fluctuations occur, the value of the drain current I _D5 flowing in the transistor M5 of the biased circuit 2 hardly changes and is kept substantially constant. Since this point is the same as the case of the conventional bias circuit 10 of FIG. 6, detailed description thereof will be omitted.

As described above, in the active bias circuit 1 of the first embodiment, the resistor R2 which causes the voltage drop V _{R due} to the gate leakage current is connected between the gate of the transistor M1 and the gate of the transistor M3. Therefore, the value of the output bias voltage V _OUT that increases / decreases in accordance with the increase / decrease in the value of the reference voltage V ₁ applied between the cascode-connected transistors M1 and M2 is shown in FIG.
As compared with the conventional bias circuit 10, by the voltage drop V _R of the resistor R2 can be further reduced. Therefore, even if the absolute value of the reference voltage V ₁ applied to generate the reference current V _REF does not reach 0V, the bias circuit 1
Of the output bias voltage V without affecting the substantial operation of the
The value of _OUT can be made almost 0V. As a result, the current flowing through the transistor M5 of the biased circuit 2 can be reliably cut off without providing a dedicated switch (that is, a drain switch) for cutting off the current.

[0061] The lower limit of the output bias voltage V _OUT, becomes lower by the voltage drop V _R of the resistor R2 than that of the resistor R2 is not a conventional active bias circuit 10, the reference voltages V ₁ The variable range of the RF output of the biased circuit 2 that can be changed depending on the value can be expanded to the lower side.

As a specific example, V ₁ = 2V, V ₂ = V
_{When D} = 4V, in the bias circuit 1 of the first embodiment, the output bias voltage V _OUT becomes about 0.5V, and a desired bias voltage can be applied to the transistor M5 of the biased circuit 2. As a result, the transistor M5 can properly exhibit the function of amplifying a predetermined high frequency signal (signal input terminal in, signal output terminal out).

On the other hand, only the reference voltage V ₁ is changed from 2V to 0.2V.
When lowered to V (that is, V ₁ = 0.2 V, V ₂ = V
_D = 4V), the conventional bias circuit 10 of FIG.
Then, the output bias voltage V _OUT becomes about 0.1V.
In contrast, in the bias circuit 1 of the first embodiment, the voltage drop V _R of the resistor R2, the output bias voltage V _{OU T}
Decreases to about 0.02V. As a result, the reference voltage V
_The output bias voltage V _OUT can be reduced to almost 0 V without setting the value of ₁ to zero.

Since the threshold voltage V _th of the transistor M5 of the biased circuit 2 is, for example, about 0.15 V, in the bias circuit 1 of the first embodiment, the value of the reference voltage V ₁ is 0.
When the voltage drops to about 2V, the drain current I _D5 of the transistor M5 can be set to zero and the transistor M5 can be cut off without fail.

(Second Embodiment) FIG. 2 shows the configuration of an active bias circuit 1A according to a second embodiment of the present invention.
In this active bias circuit 1A, a resistor R3 for current shunting is provided in place of the resistor R2 for voltage drop in the first embodiment. The resistor R3 is connected between the gate and the source of the transistor M4.
As described above, since the gate of the transistor M4 is connected to its drain, this resistor R3 is connected in parallel between the drain and source of the transistor M4. Since the other configurations are the same as those of the bias circuit 1 of the first embodiment, the same reference numerals as those in FIG.

The resistance value of the resistor R3 is the drain-source resistance R _M4 of the transistor M4 when the resistor R3 is not provided.
It is preferably smaller than the value of. In this case, a majority of the drain current I _D3 of the transistor M3 flows through the resistor R3, so that the drain current I _D4 of the transistor M4 is significantly reduced as compared with the case without the resistor R3. As a result, the value of the forward voltage drop V _FM4 generated by the transistor M4 becomes sufficiently large, and the output bias voltage V _FM4 becomes large.
It becomes easy to reduce the absolute value of _OUT to a desired value. Here, the resistance value of the resistor R3 is set to 1 kΩ.

The operation of this active bias circuit 1A is as follows.

By properly setting the resistance value of the reference resistor R1 with respect to a predetermined reference voltage V ₁ (for example, 2V), the reference current I _REF flowing through the transistor M1 can be determined to a desired value. As a result, the value of the voltage V _P1 generated at the connection point P1 between the resistor R1 and the drain of the transistor M1 is determined. At this time, the voltage V _{P2 at} the connection point P2 between the source of the transistor M3 and the drain of the transistor M4 is
Since it is equal to the forward voltage drop V _FM4 of the transistor M4, the output bias voltage V _OUT can be expressed by the following equation (3).

V _OUT = V _P2 = V _FM4 (3) In this bias circuit 1A, since the resistor R3 is inserted in parallel with the transistor M4, the drain current I _D3 of the transistor M3 is from the point P2 to the transistor M3. M
4 and resistor R3. That is, the drain current I
_D3 is the drain current I _D4 of the transistor M4 and the resistor R
It splits into a shunt current I _{S of} 3 and flows to the ground terminal. As a result, the following equation (4) is established.

[0070]             I_D4  = I_D3  -I_S                         (4) In the case of the conventional bias circuit 10 without the resistor R3,
Ignoring the gate current, the drain of transistor M4
Current I_D4Is the drain current I of the transistor M3 _D3Equal to
Yes i_D4= I_D3Is. In contrast, the second implementation
In the active bias circuit 1A of the form,
As is clearer, the drain current of the transistor M4
I_D4Is the shunt current I_S Is decreased by the value of
Drain-source resistance R of transistor M4_M4The value of the
Is reduced, in other words, the forward current of the transistor M4 is reduced.
Pressure drop V_FM4 The voltage value itself decreases. Therefore, the formula
From (3), output bias voltage V_OUT Is also the forward voltage
Descent V_FM4 Is reduced by the amount of decrease.

As described above, the active / active state of the second embodiment is
Also in the bias circuit 1A, as in the case of the first embodiment, even if the absolute value of the reference voltage V ₁ applied to generate the reference current V _REF does not reach 0V, the bias circuit 1A substantially operates. It is possible to make the value of the output bias voltage V _OUT almost 0V without affecting the above. as a result,
The current flowing in the transistor M5 of the biased circuit 2 can be cut off without providing a dedicated switch (that is, a drain switch) for cutting off the current.

Since the lower limit value of the output bias voltage V _OUT becomes lower as the forward voltage drop V _FM4 by the transistor M4 decreases, the RF of the biased circuit 2 which can be changed by the value of the reference voltage V _1. The variable range of the output can be expanded to the lower side.

As a specific example, V ₁ = 2V, V ₂ = V
_{When D} = 4V, the bias circuit 1A of the second embodiment
Also, the output bias voltage V _OUT is about 0.5 V, and a desired bias voltage can be applied to the transistor M5 of the biased circuit 2.

On the other hand, when only V ₁ is lowered from 2V to 0.2V (that is, V ₁ = 0.2V, V ₂ = V _D = 4V)
In the bias circuit 1A of the second embodiment,
The output bias voltage V _OUT drops to about 0.02V. As a result, even if the value of the reference voltage V ₁ is not zero,
The output bias voltage V _OUT can be reduced to almost 0V. That is, even if the value of the reference voltage V ₁ can be reduced only to about 0.2 V, the drain current I _D5 of the transistor M5 in the biased circuit 2 can be set to zero and the transistor M5 can be cut off reliably. .

(Third Embodiment) FIG. 3 shows the configuration of an active bias circuit according to a third embodiment of the present invention. This active bias circuit 1B is the same as the active bias circuit 1 of the first embodiment shown in FIG. 1, except that the field effect transistors M1 to M4 are replaced by bipolar transistors Q1 to Q1.
Q4 is replaced respectively, and other configurations are the same. Therefore, the same reference numerals as those in FIG. 1 are attached to the same components, and the description thereof will be omitted.

In FIG. 3, I _C1 , I _C2 , I _C3 , I
_C4 indicates the collector currents of the transistors Q1, Q2, Q3, Q4, respectively.

Also in the third embodiment, substantially the same operation as in the first embodiment is performed. Therefore, also in the active bias circuit 1B of the third embodiment, the same effect as that of the first embodiment can be obtained.

(Fourth Embodiment) FIG. 4 shows the configuration of an active bias circuit 1C according to a fourth embodiment of the present invention.
This active bias circuit 1C is obtained by replacing the field effect transistors M1 to M4 with the bipolar transistors Q1 to Q4 in the active bias circuit 1A of the second embodiment shown in FIG. 2, and the other configurations are the same. is there. Therefore, the same reference numerals as those in FIG. 2 are attached to the same components, and the description thereof will be omitted.

Also in the fourth embodiment, substantially the same operation as in the second embodiment is performed. Therefore, also in the active bias circuit 1C of the fourth embodiment, the same effect as that of the second embodiment can be obtained.

(Modification) The present invention is not limited to the above embodiment. For example, as the resistors R2 and R3, resistors having arbitrary configurations can be used as long as they cause a predetermined voltage drop depending on the flowing current.

As the field effect transistor, M
ES (MEtal-Semiconductor) type and MOS (Metal-Oxid)
Any field effect transistor of the e-Semiconductor type can be used. Further, instead of the n-channel field effect transistor, a p-channel field effect transistor is replaced by npn.
It is needless to say that a pnp type bipolar transistor may be used instead of the type bipolar transistor.

Further, although the biased circuit 2 uses the enhancement type field effect transistor M5, the present invention is not limited to this. Output bias voltage V
_{If the} element to which _OUT is applied is an enhancement-type and voltage-driven type active element, any device can be used instead of the transistor M5. Furthermore, the transistor M
It goes without saying that other elements may be included in addition to the voltage-driven active element such as 5.

(Fifth Embodiment) In each of the above-described embodiments, in particular, in the bias circuit in which the shunt resistor is provided in the circuit combining the Wilson type circuit and the Widlar type circuit described in FIG. 2, the MOS transistors M1 to M are provided.
4 for the purpose of compensating for variations in the threshold voltage V _th and temperature characteristics. That is, it means that the gate bias supplied to the FET is changed in association with variations in V _th and temperature, and the current flowing through the FET is made constant.

For example, when the reference voltage V ₁ is 2 V, the bias voltage V ₂ and the FET drain voltage V _D are 4 V, the reference current I _REF flowing through the bias circuit input side FET is determined by selecting the reference resistor R _2. To do. Then, a voltage dropped by the forward voltage (VF) of the transistor M3 as the Wilson FET is generated as the voltage V _OUT of the bias circuit output section (terminal T3) and is supplied to the gate of the transistor M5. As described above, the current I _D5 flowing through the transistor M5 is determined by this.

Here, for example, when the threshold voltage V _th increases to the negative side, the reference current I _REF increases and the voltage V _OUT of the bias circuit output portion T3 decreases, and the current flowing through the FET 5 is kept constant. Works like. Further, even when the temperature changes, each FET changes in the same manner as when the respective threshold voltage V _th changes.
The bias circuit 1A operates similarly to the above, and the current is kept constant.

Further, when the output power amplified by the transistor M5 forming the biased circuit 2 is varied, the reference voltage V ₁ is increased or decreased.
However, due to the limitation on the mobile phone system, the voltage V ₁
It may not be possible to lower the lower limit value of 0V to 0V.
That is, it may only be possible to reduce the voltage to about 0.2V. In this case, the purpose was to provide the shunt resistor R3 to reduce the voltage V _OUT of the bias circuit output portion T3 to near 0 V and sufficiently reduce the drain-source current I _D5 .

The bias circuit 1A as shown in FIG. 2 has the following problems. That is, when the drain voltage V _D of the transistor M5 is higher, for example, about 6 V, the gate-drain leak current of the transistor M5 increases and the shunt resistance R3 is increased.
It is conceivable that the voltage V _OUT of the bias circuit output section T3 rises due to the flow of the current to the drain circuit to increase the drain-source current. Therefore, a dedicated drain switch interlocked with the on / off of the transistor M5 of the biased circuit 2 may be required. In that case, there is a problem that the number of parts of the mobile phone set is increased or the battery life is shortened.

The fact that the current flowing between the drain and the source of the transistor M5 cannot be reduced means that the power cannot be sufficiently reduced when the transistor is subjected to a high frequency signal amplification operation (power operation). This means that the problem of narrowing the variable power range by the reference voltage V ₁ occurs.

The fifth embodiment, which will be described below, further improves these problems.
_{Even when 1} drops to only about 0.2 V and the drain voltage V _D rises, the bias circuit generator T
3 is to lower the voltage V _OUT of 3 to sufficiently pinch off the drain-source current in the transistor M5 of the biased circuit 2.

FIG. 5 is a circuit diagram showing the structure of an active bias circuit according to the fifth embodiment of the present invention, which uses field effect transistors. As shown in FIG. 5, in the present embodiment, a bias circuit combining the Wilson type circuit and the Widlar type circuit of FIG. 2 described above, that is, the gate and source of the Wilson type field effect transistor M2 and the Wilson type field effect transistor M4. A switching block 3 including a field-effect transistor M6, a diode-connected transistor M7, a field-effect transistor M8, and resistors R4 to R6 is provided for the circuit having the shunt resistor R2 provided therebetween.
Is added between the bias circuit output section T3 and the biased circuit 2.

That is, the switching block 3 includes the bias circuit output section T3 (that is, the signal input terminal in).
A MOS transistor (FET) M6 whose drain is connected to the source and whose source is grounded, and whose drain and gate are MO
Connected to the gate of S transistor M6 (diode connection)
And a grounded source MOS transistor (FET)
M7, a MOS transistor (FET) M8 whose drain is connected to the gate of the MOS transistor M6, and a MOS
The resistor R4 connected between the drain of the transistor M8 and the drain of the MOS transistor M5 in the biased circuit 2, the resistor R5 connected between the source of the MOS transistor M8 and the ground, the terminal T1 of the reference power source V ₁ and the MOS transistor M8. It is formed by a resistor R6 connected between the gates.

In FIG. 5, when the reference voltage V ₁ is, for example, 2 V, and the bias voltage V ₂ and the drain voltage V _D are, for example, 4 V, the bias circuit output section T3.
Voltage V _OUT of becomes about 0.5V, the bias circuit 2
The field effect transistor M5 of is set to a desired bias condition, the high frequency signal inputted from the signal input in is amplified,
It can be output to the output out. Further, under such a normal amplification condition, the voltage V _OUT of the bias circuit output portion T3 when the reference voltage V ₁ is lowered to, for example, about 0.1 V is set to 0 without affecting the amplification output characteristic.
It can be sufficiently lowered to near V. Therefore, when using the FET M5 which can be expected to be driven by a single power source such as a complete enhancement mode device, it is not necessary to turn off the drain voltage V _D , and the drain-source current I _D5 is sufficiently lowered to about several mA. Moreover, the output power out can be reduced. However, it is generally known that when the drain voltage of a field effect transistor rises, the leak current I _L between the gate and the drain rises. Therefore, when the drain voltage V _D rises to, for example, about 6 V, a partial current I1 of the gate-drain leak current I _L flows into the shunt resistor R3 of the bias circuit 1D, and the voltage of the bias circuit output portion T3 increases. V _OUT rises and field effect transistor M5
Drain-source current I _DS flowing through the rises.

To improve this, the reference voltage V
When ₁ is, for example, 2V, and the impedance of the switching block 3 as viewed MOS transistor M6 from the bias circuit output unit T3 is cut off between the gate and the drain leakage current I _L to the high-impedance, high-frequency signal amplifying operation (RF) Does not affect Further, when the reference voltage V ₁ is, for example, 0.1 V, the FE
TM6 turns on and the gate-drain leakage current I
_L flows through current paths I2, by reducing the current I1 flowing through the shunt resistor R3, it is possible to suppress the increase in the voltage V _{OU T} of the bias circuit output unit T3. As a result, a wide dynamic range can be obtained by sufficiently reducing the drain-source current I _DS of the FET M5 to about several mA and sufficiently reducing the output power thereof.

Next, an example of this embodiment will be described.
This will be specifically described. As described above, this embodiment is
Output the high frequency signal supplied from the input terminal in
To the gate of the MOS transistor M5 which amplifies and outputs
With the bias circuit 1D that determines the bias point for
is there. In this bias circuit 1D, for example,
Pressure V_thTurn off the FET M5 of about 0.15V
The reference voltage V₁ For example, 0.
2V, bias voltage V₂ And drain voltage V_D For example
When 4V is applied, the shunt resistance R3 has an effect.
Voltage V of the ear circuit output T3_OUT Lower to around 0V
The drain current I of the FET M5_D5Enough
You can pinch off. However, the drain voltage V
_D Rises to 6V, for example,
Gate-drain leakage current I _L Will increase. to this
The voltage V of the bias circuit output section T3_OUT The rise of
To do this, connect the switching block 3 to the output section T3.
To do.

First, the reference voltage of the bias circuit 1D.
Pressure V₁ To the biased circuit 2 by applying, for example, 0.2 V to
If you want to turn off FETM5, turn off FETM8
And drain voltage V_D Via resistor R4, for example
The FET M6 is turned on by the voltage adjusted to 0.4V.
It That is, compared with the shunt resistor R3, the on-state
Gate width by choosing a gate width with low impedance
・ Drain leakage current I_L Is current I2> current I
The voltage of the bias circuit generator T3 is branched so as to be 1.
Pressure V_OUT Can be suppressed. At this time, die
The FET M7 connected in ode is only in the biased circuit 2.
FETM5 threshold voltage V_thIs from 0V to 0.3
Even when it fluctuates to about V, the gate voltage of FET M6
Constant so that it does not exceed the VF of FET M6,
Voltage V of bias circuit output T3 _OUT Prevent rising
It

Next, for example, 2V is applied to the reference voltage V ₁ of the bias circuit 1D and F of the biased circuit 2 is applied.
When the ETM5 is to be turned on, the FETM6 is turned off by turning on the FETM8 so that the FETM6 is cut off sufficiently. As a result, when viewed from the bias circuit output section T3, the added switching block 3 becomes high impedance and does not affect the normal high frequency amplification output characteristic.

The resistors R4 to R6 in the switching block 3 need to be selected at optimum values so as to set the bias so that they operate when the FET M5 is on or off.

As described above, in the fifth embodiment, the FET M5 of the biased circuit 2 is turned off and the bias power supply is higher than usual, that is, the reference voltage V _{1 is} , for example, 0.2 V, and the bias voltage V ₂ is set. For example, by applying, for example, 4V and 6V to the drain voltage V _D, and by inserting the switching block 3 that turns on / off at the level of the reference voltage V ₁ ,
It is possible to form a path through which the leak current I _L between the gate and the drain flows, reduce the voltage V _OUT of the bias circuit output portion T3 to near 0 V, and sufficiently pinch off the drain current I _D of the FET M5. Therefore, even if a single power supply operation is expected in a device such as a full enhancement mode FET in which a drain-source current I _DS flows out when a gate bias is positively applied, the FET M5 is turned on / off. Since an external switch for the drain voltage V _D can be eliminated, it is possible to reduce the number of parts of the mobile phone handset set as a whole and to reduce the cost and the volume of the device.

Further, in the present embodiment, since the number of parts can be reduced, power consumption can be suppressed, and the call time and waiting time of the mobile telephone handset can be extended.

[0100] Further, in the present embodiment, sufficiently reduce the drain current of FETM5 of the bias circuit, it becomes possible to narrow a sufficient output power by the reference voltages V _1, FE by reference voltages V ₁
The lower limit value of the output power of TM5 can be lowered, and as a result, the variable range of the output power can be widened.

[0101]

As described above, according to the active bias circuit of the present invention, even if the absolute value of the reference voltage applied to generate the reference current does not reach 0V, the absolute value of the output bias voltage is increased. The value can be set to almost 0V. Further, the present invention can further widen the variable range of the RF output of the biased circuit which can be changed by changing the value of the reference voltage. Further, according to the present invention, the current flowing through the biased circuit including the enhancement type active element can be surely shut off without providing the dedicated circuit for shutting off the drain current in the biased circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an active bias circuit according to a first embodiment of the present invention, which uses a field effect transistor.

FIG. 2 is a circuit diagram showing a configuration of an active bias circuit according to a second embodiment of the present invention, which uses a field effect transistor.

FIG. 3 is a circuit diagram showing a configuration of an active bias circuit according to a third embodiment of the present invention, which uses a bipolar transistor.

FIG. 4 is a circuit diagram showing a configuration of an active bias circuit according to a fourth embodiment of the present invention, which uses a bipolar transistor.

FIG. 5 is a circuit diagram showing a configuration of an active bias circuit according to a fifth embodiment of the present invention, which uses field effect transistors.

FIG. 6 is a circuit diagram showing a configuration of a conventional active bias circuit using a field effect transistor.

[Explanation of symbols]

1, 1A, 1B, 1C, 1D Active bias circuit 2 Biased circuit 3 Switching block M1 to M8 Field effect transistors Q1, Q2, Q3, Q4 Bipolar transistor R1 Reference resistor R2 Resistor R3 for voltage drop generation Diverted resistors R4, R5 Resistors T1, T2, T3, T4 Terminal V _OUT Bias circuit output in High frequency signal input out High frequency signal output

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03F 1/00-3/72 G05F 3/26

Claims (9)

(57) [Claims] 1. A diode-connected first transistor, to which a reference current is supplied via a first resistor, a second transistor cascode-connected to the first transistor, and a control terminal of the first transistor. A third transistor having a control terminal connected thereto, through which a constant current having a current value of a predetermined ratio with respect to the reference current flows, and cascode-connected to the third transistor,
A diode-connected fourth transistor having a control terminal connected to the control terminal of the second transistor, wherein an output bias voltage is output from an output terminal formed at a connection point of the third transistor and the fourth transistor. An active transistor whose output bias voltage changes according to the value of a reference voltage applied to the first transistor and the second transistor, which are connected in cascode, while outputting
The bias circuit includes a second resistor connected between the control terminal of the first transistor and the control terminal of the third transistor, and reduces a voltage drop caused by a current flowing through the second resistor. An active bias circuit characterized in that the absolute value of the output bias voltage is reduced according to the value of the voltage drop. 2. The absolute value of the reference voltage is set to 0 from a predetermined value.
2. The active bias circuit according to claim 1, wherein, when brought close to V, the absolute value of the output bias voltage becomes 0 V before the absolute value of the reference voltage reaches 0 V. 3. The output bias voltage is designed to be applied to a control terminal of an enhancement-type voltage-driven active element, and the absolute value of the reference voltage is brought close to 0 V from a predetermined value. 3. The active bias circuit according to claim 1, wherein the output bias voltage reaches a value capable of cutting off the active element before the absolute value of the reference voltage reaches 0V. 4. A diode-connected first transistor, to which a reference current is supplied via a first resistor, a second transistor cascode-connected to the first transistor, and a control terminal of the first transistor. A third transistor having a control terminal connected thereto, through which a constant current having a current value of a predetermined ratio with respect to the reference current flows, and cascode-connected to the third transistor,
A diode-connected fourth transistor having a control terminal connected to the control terminal of the second transistor, wherein an output bias voltage is output from an output terminal formed at a connection point of the third transistor and the fourth transistor. An active transistor whose output bias voltage changes according to the value of a reference voltage applied to the first transistor and the second transistor, which are connected in cascode, while outputting
The bias circuit includes a second resistor having one terminal commonly connected to the control terminal of the second transistor and the control terminal of the fourth transistor, and a part of the current flowing through the third transistor is By dividing the voltage into the second resistor, the value of the voltage drop generated by the fourth transistor is decreased, and thus the absolute value of the output bias voltage is decreased according to the value of the voltage drop. -Bias circuit. 5. The active bias circuit according to claim 4, wherein the resistance value of the second resistor is set smaller than the resistance value of the fourth transistor. 6. The absolute value of the reference voltage is set to 0 from a predetermined value.
6. The active bias circuit according to claim 4, wherein when the voltage is brought close to V, the absolute value of the output bias voltage becomes 0 V before the absolute value of the reference voltage reaches 0 V. 7. The output bias voltage is designed to be applied to a control terminal of an enhancement-type voltage-driven active element, and the absolute value of the reference voltage is brought close to 0 V from a predetermined value. 7. The active bias circuit according to claim 4, wherein the output bias voltage reaches a value capable of cutting off the active element before the absolute value of the reference voltage reaches 0V. 8. An active bias circuit for supplying a bias voltage to a biased circuit for inputting, amplifying and outputting a high frequency signal, wherein the drain and gate are short-circuited and the drain is used as a reference power source through a reference resistor. The connected first MOS transistor and the first M transistor
A second MOS transistor having a drain connected to the source of the OS transistor and having a source grounded; a third MOS transistor having the drain connected to a bias power supply and the gate connected to the gate of the first MOS transistor; and a drain , The gate is short-circuited, the drain is connected to the source of the third MOS transistor, and the source is connected between the fourth MOS transistor having the source grounded and the gates of the second and fourth MOS transistors and the ground. Shunt resistor and the third and fourth MOS
A bias circuit output section for extracting the bias voltage from a connection point of a transistor and an input terminal for the high frequency signal are connected to the bias circuit output section, and a leakage current of the biased circuit is shunt controlled to the shunt resistor. An active bias circuit having a switching block. 9. The switching block comprises a sixth MOS transistor having a drain connected to the bias circuit output section and a source grounded, and a drain and a gate connected to the gate of the sixth MOS transistor and a source connected to the sixth MOS transistor. A grounded seventh MOS transistor, an eighth MOS transistor whose drain is connected to the gate of the sixth MOS transistor, a drain of the eighth MOS transistor and the fifth MOS transistor in the biased circuit. A first resistor connected between the drains, a second resistor connected between the source of the eighth MOS transistor and the ground, and a third resistor connected between the reference power supply and the gate of the eighth MOS transistor. 9. An active bias circuit according to claim 8 formed with a resistor. Road.