JP3339361B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device applied to a dual gate complementary insulated gate field effect transistor (CMOSFET).

[0002]

2. Description of the Related Art N-channel MOS field-effect transistors (hereinafter referred to as NMOSFET) and P-channel MOS
A CMOSFET composed of both a field-effect transistor (hereinafter, referred to as a PMOSFET) has characteristics of low power consumption and high speed, and is therefore widely used as many LSI components including memories and logics. In the CMOSFET, the gate length of each MOSFET has been miniaturized in accordance with high integration of LSI.

[0003] Conventionally, the above PMOSFET includes:
Process is simplified, because of high performance because a buried channel type or the like, the NMOSFET also N ⁺
Type gate electrodes have been used. However, since the so-called deep sub-micron generation, it is difficult to suppress the short channel effect in the buried channel type MOSFET, and therefore, it is effective to apply a surface channel type P ⁺ type to the gate electrode of the PMOSFET.

The gate electrode of an NMOSFET is set to N⁺Type and
And the gate electrode of the PMOSFET is ⁺CMO to be type
SFETs, ie different conductivity types on the same semiconductor substrate
To manufacture a CMOSFET that forms a gate electrode,
A film for forming a gate electrode, for example, N of a Poly-Si film⁺Type and
N-type impurities such as arsenic (As) and phosphorus (P)
Ion implantation, P⁺Boron (B) or Nif
Boron nitride (BF_TwoIon implantation of P-type impurities such as
In many cases, ion implantation is performed separately.
No.

Further, for example, the gate electrode, tungsten silicide (WSi _x) of silicon (Si) of polysilicon formed on the substrate 50 on (Poly-Si) film 53 formed on the upper layer as shown in FIG. 8 film Tungsten-polycide consisting of 54 (hereinafter referred to as W-polycide)
In the case of a structure, conventionally, the above ion implantation is performed by WSi
_{This is performed} after the formation of the _x film 54. In this case, NMOSFET
The WSi _x film 54 in the region 55 where the PMOSFET is formed is doped with an N-type impurity such as phosphorus at a high concentration.
Doping the example boron P-type impurity at a high concentration in the WSi _x film 54 in the region 56 to form a. Thereafter, W is formed by a high-temperature heat treatment such as annealing for activating impurities in a source region and a drain region (hereinafter, referred to as a source / drain region) (not shown) formed in the Si substrate 50.
The Si _x doped phosphorus and boron in the film 54 are diffused into the Poly-Si film 53 of the regions 55 and 56.

In FIG. 8, reference numeral 51 denotes an Si substrate 50.
A region 55 for forming an NMOSFET and a PMOSF
A field oxide film is formed so as to be separated from a region 56 where ET is to be formed.
This is a gate oxide film formed on the surface of the i-substrate 50.

[0007]

However, the following problems occur in the above-mentioned conventional technology. First,
The gate electrode by laminating a metal silicide film such as Poly-Si film and the WSi _x structure or (polycide structure), Poly-S
When a structure in which an i film and a metal film are stacked is used, the diffusion rate of N-type and P-type impurities in the metal film or the metal silicide film is much faster than in Si or silicon oxide (SiO ₂ ). (Diffusion coefficient is about 4 digits larger). for that reason,
By the high-temperature heat treatment after the ion implantation, N-type and P-type impurities cause mutual diffusion, and a phenomenon occurs that these impurities compensate each other.

[0008] For example, in the case of FIG. 8 in which the gate electrode and the W- polycide structure, WSi _x film 54 phosphorus N-type towards the Poly-Si film 53 side of the gate electrode formation portion of P-type
8 is diffused in the direction of arrow A in FIG. 8, and at the same time, P-type boron diffuses in the direction of arrow B in FIG. 8 toward the Poly-Si film 53 where the N-type gate electrode is formed. As a result, boron which has been doped in the P-type gate electrode formation portion,
The phosphorus that has been doped in the N-type gate electrode forming portion compensates each other. When this phenomenon occurs, the Fermi level in the poly-Si film 53 of the gate electrode fluctuates, or the gate electrode is depleted when a gate voltage is applied, thereby changing the threshold voltage (hereinafter referred to as Vth). As a result, the MOSFET characteristics deteriorate.

[0009] When WSi _x film 54 and is formed by a CVD (chemical vapor deposition) method using a source gas containing fluorine include fluorine in WSi _x film 54 has been formed It is. Therefore, in the W- polycide structure having such a WSi _x film 54, until the Si substrate 50 boron is doped in the Poly-Si film 53 by the enhanced diffusion due to the influence of fluorine penetrates the gate oxide film 52 There is also a problem in that the MOSFET is diffused and the MOSFET characteristics are degraded. Further phosphorus in Poly-Si film 53, an impurity such as boron, later due to a decrease in the impurity concentration in the Poly-Si film 53 due to the fact that diffuses into the WSi _x film 54 by a high-temperature heat treatment, the gate voltage The gate electrode is depleted when the voltage is applied. As a result, the device characteristics of the MOSFET are degraded.

[0010] Therefore, in order to suppress mutual diffusion of P-type impurity and the N-type impurity, it has been reported a technique for the composition of the WSi _x film with Si over the purpose of reducing the diffusion rate in the WSi _x film . This mechanism, by the composition of the WSi _x film and Si-rich, break the chain structure of W, is that eliminating the diffusion path ( "VLSI Symp.Tech.Di
g., "Dual (n ⁺ / p ⁺ ) Polycide Gate Technology usi
ng Si-Rich WSi _x to Exterminate Lateral Dopant Dif
fusion "(1994) T.Fujii, et.al., p.117"). But,
When excessively increased composition ratio of Si, it increases the resistance of the WSi _x film, which is not necessarily advisable since the delay or the like of the increase-circuit operation of the wiring resistance will be caused by.

[0011] In order to prevent the high concentration of impurities diffused into the WSi _x film, phosphorus or boron is ion-implanted into the Poly-Si film, the diffusion of these impurities in the Poly-Si film by annealing and a method of depositing a WSi _x film has been proposed thereafter on Poly-Si film. However, even by this method, if subsequent temperature of heat treatment performed is high, impurities in the Poly-Si film is WSi _x
It is very difficult to sufficiently suppress the diffusion into the film, and it is particularly difficult to suppress the gate electrode from being depleted due to a decrease in the impurity concentration in the Poly-Si film.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a first transistor provided with a first gate electrode of a first conductivity type and a second gate electrode of a second conductivity type on a substrate. And a second transistor provided with
The first gate electrode and the second gate electrode are each formed of a continuous gate electrode wiring, and the gate electrode wiring is
In a semiconductor device comprising a polysilicon film laminate and a metal film or a metal compound film formed thereon, the polysilicon film laminate is formed on a first polysilicon film and a first polysilicon film. And a second polysilicon film containing more oxygen than the oxygen content in the first polysilicon film.

Phosphorus, boron,
It is known that impurities such as arsenic have a very small diffusion coefficient in a SiO ₂ film. For example, the diffusion of the impurity in the SiO ₂ film is approximately two to three orders of magnitude smaller than the diffusion coefficient of the same impurity in Si. Therefore, at the temperature of the heat treatment performed in the manufacture of the semiconductor device, the SiO ₂ film functions as a stopper layer against diffusion of impurities.

According to the present invention, the second polysilicon film of the polysilicon film laminate of the gate electrode wiring constituting the first gate electrode and the second gate electrode is larger than the oxygen content in the first polysilicon film. The second layer is made of a film containing oxygen.
The polysilicon film is a film having properties closer to the SiO ₂ film than other films. Therefore, the first conductivity type impurity is diffused in the first polysilicon film at a high concentration to form a first gate electrode, and the second polysilicon type impurity is diffused in the first polysilicon film at a high concentration. When the second gate electrode is formed, even if the semiconductor device is subjected to a high-temperature heat treatment, diffusion of impurities in the first polysilicon film into the second polysilicon film is suppressed. For this reason, the diffusion of impurities in the first polysilicon film into the upper metal film or metal compound film is suppressed. Further, even if an impurity is present in the metal film or the metal compound film, diffusion of the impurity into the first polysilicon film is also suppressed. Therefore, interdiffusion between the first conductivity type impurity of the first transistor and the second conductivity type impurity of the second transistor is suppressed, and the first conductivity type impurity in the first polysilicon film of the gate electrode wiring is removed. Since the phenomenon of compensating with the impurities of the second conductivity type does not occur, a decrease in the impurity concentration in the first polysilicon film is also prevented.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a semiconductor device according to the present invention will be described with reference to a sectional side view of a main part shown in FIG. Here, a case will be described in which the present invention is applied to a CMOSFET and the first conductivity type in the present invention is, for example, N-type and the second conductivity type is, for example, P-type.

As shown in FIG.
Is an NMOSFET 1 having an N ⁺ type gate electrode 10.
8 and PMOSFET with P ⁺ type gate electrode 10
19 are formed on the substrate 2 made of Si. The N-type gate electrode 10 and the NMOSFET 18 serve as a first gate electrode and a first transistor in the present invention, respectively.
The SFET 19 serves as a second gate electrode and a second transistor in the present invention, respectively.

On the substrate 2, a field oxide film 3 for separating the formation region of the NMOSFET 18 and the formation region of the PMOSFET 19 is formed. The NM of the substrate 2
An NMOS channel region 4 is formed in a region where the OSFET 18 is formed.
The PMOS channel region 5 is formed in the region where the PMOSFET 19 is formed. Further, on the substrate 2, an NMOSF
An N ⁺ -type gate electrode 10 and a P ⁺ -type gate electrode 10 are formed in the formation region of the ET 18 and the formation region of the PMOSFET 19 via the gate oxide film 6, respectively.

The N ⁺ -type and P ⁺ -type gate electrodes 10 are each formed of a continuous gate electrode wiring composed of a poly-Si film laminate 9 and a metal compound film 17 formed thereon. The Poly-Si film laminate 9 includes a first Poly-Si film
It is formed by stacking a Si film 7 and a second Poly-Si film 8 containing more oxygen than the oxygen content in the first Poly-Si film 7. Also, the first Po of the N ⁺ type gate electrode 10
An N-type impurity such as arsenic is diffused at a high concentration in the ly-Si film 7, and the first Poly-Si film 7 of the P ⁺ -type gate electrode 10 is formed.
Has a high concentration of a P-type impurity such as boron.

N⁺Type, P⁺Type gate electrode 10
The first Poly-Si film 7 is a normal Poly-Si film, that is,
10 oxygen content¹⁸/ Cm^ThreeLess than Poly-Si film
The second Poly-Si film 8 has an oxygen content of, for example, 1
0¹⁸/ Cm^ThreeMore than 10 ^{twenty two}/ Cm^ThreeBelow high concentration
So-called Semi-Insulator Poly-Si containing oxygen
(SIPOS). The gate oxide film 6
A first Poly-Si film 7 is formed thereon, and
By two layers of 1 Poly-Si film 7 and 2nd Poly-Si film 8
A Poly-Si film laminate 9 is configured. Poly-
Metal compound film 17 formed on Si film stack 9
Here, here, for example, titanium silicide (TiSi_x)
A layer is formed.

Here, the reason why the oxygen content in the second Poly-Si film 8 is, for example, not less than 10 ¹⁸ / cm ^{3 and not} more than 10 ²² / cm ³ is described below as being less than 10 ¹⁸ / cm ^3. This is because the second Poly-Si film 8 may not function as a diffusion stopper layer, and if it exceeds 10 ²² / cm ³ , it may be close to an insulating film and may not be conductive.

A sidewall 13 is formed on the side surface of the N ⁺ type and P ⁺ type gate electrode 10 configured as described above. On the surface layer side of the substrate 2 on both sides of the N ⁺ -type gate electrode 10, an N-type LDD region (Light
y Doped Drain) region 11 is formed, and a P-type LDD is formed on the surface layer side of the substrate 2 on both sides of the P ⁺ -type gate electrode 10.
A region 12 is formed. Further, N
^An N-type source / drain region 14 is formed on both sides of the ⁺ -type gate electrode 10 via an N-type LDD region 11, and a P-type LDD is formed on both sides of the P ⁺ -type gate electrode 10.
A P-type source / drain region 15 is formed via region 12. Also, N-type source / drain regions 1
4, the surface portion of the P-type source / drain regions 15, similar to the top layer of each gate electrode 10, the metal compound film 17 made of TiSi _x film is formed.

Next, the CMOSFE configured as described above
2A to 2C and FIG. 3 show an example of a method of manufacturing T1.
This will be described with reference to (d) to (g). In manufacturing the CMOSFET 1, first, as shown in FIG.
LOCOS method, for example, by wet oxidation at 950 ° C.
A region for forming an NMOSFET on the substrate 2, a PMOSF
A field oxide film 3 is formed to separate a region where ET is to be formed.

Next, ion implantation for forming a P well region, ion implantation for forming a buried layer for preventing punch-through of a transistor, and ion adjustment for adjusting Vth are performed on the substrate 2 in a region where an NMOSFET is to be formed. The NMOS channel region 4 is formed by performing ion implantation or the like.
Further, ion implantation for forming an N-well region, ion implantation for forming a buried layer for preventing punch-through of a transistor, and ion implantation for adjusting Vth are performed on the substrate 2 in a region where a PMOSFET is to be formed. Are performed to form the PMOS channel region 5.

Subsequently, as shown in FIG. 2B, for example, a mixed gas of hydrogen and oxygen is used and the ambient temperature is set to 850 ° C.
The surface of the substrate 2 which is exposed by the pyrogenic oxidation under the above conditions, ie, the NMOS channel region 4
A gate oxide film 6 is formed on each surface of the PMOS channel region 5 to a thickness of, for example, about 6 nm. Thereafter, a first Poly-Si film 7 is formed on the field oxide film 3 and the gate oxide film 6 by a CVD method under reduced pressure (hereinafter, referred to as an LP-CVD method). Here, for example,
Silane (SiH ₄ ) gas is used as a source gas, and the deposition temperature is 5
The first Poly-Si film 7 is formed to a thickness of, for example, 50 nm to 200
It is formed to a thickness of about nm.

Next, as shown in FIG. 2C, a second Poly-Si film 8 is formed on the first Poly-Si film 7 by the CVD method. At this time, the thickness of the second Poly-Si film 8 is set to be equal to the thickness of the second Poly-Si film 8 at the time when a Ti film silicidation process described later is completed.
-The thickness is set so that the Si film 8 remains. Here, for example, the source gas and the flow rate are set to SiH ₄ / N ₂ O: 500 s.
ccm / 20 sccm to 30 sccm [sccm is a volume flow rate in standard condition (cm ³ / min)], C at an atmospheric pressure of about 20 Pa, and a deposition temperature of about 620 ° C.
The second Poly-Si film 8 is formed by, for example, 5 nm to 5 nm by the VD method.
It is formed to a thickness of about 0 nm. These forming conditions are merely examples, and the deposition temperature can be lowered to, for example, about 530 ° C. to increase the amount of oxygen taken in. Further, parameters of other forming conditions can be appropriately set.

Next, a lithography technique (resist coating,
By performing anisotropic etching using a resist mask (not shown) patterned by exposure, development, baking, etc., as shown in FIG.
-Si film 7 and second Poly-Si film 8 are used as gate electrode wiring patterns, that is, gate electrode 10 shown in FIG.
Process into the shape of Thereafter, the resist mask used in the anisotropic etching is removed.

Subsequently, PMO is performed by lithography technology.
Patterning of a resist mask (not shown) covering a region where the SFET is to be formed is performed. Then, the first Poly-S processed into the pattern of the resist mask and the gate electrode 10 is formed.
Using the i film 7 and the second Poly-Si film 8 as a mask,
Arsenic ions (As ⁺ ) are implanted into a region of the substrate 2 where an NMOSFET is to be formed, and an N-type LDD region 11 is formed in a region of the substrate 2 where an NMOSFET is to be formed as shown in FIG. In this ion implantation, for example, the ion energy is 20 keV and the dose is 5 × 10 ¹³ / c.
m carried out in ^two and the conditions.

After removing the resist mask, a resist mask (not shown) covering a region for forming an NMOSFET is patterned by a lithography technique.
Then, using this resist mask and the first Poly-Si film 7 and the second Poly-Si film 8 processed into the pattern of the gate electrode 10 as a mask, boron difluoride ion (BF ₂ ⁺ ) Is ion-implanted to form a P-type LDD region 12 in a region of the substrate 2 where a PMOSFET is to be formed. This ion implantation is performed, for example, at an ion energy of 20 keV and a dose of 5 × 1.
It is performed under the condition of 0 ¹³ pieces / cm ² . After that, the resist mask used in the ion implantation is removed.

Further, after an SiO ₂ film is deposited on the entire surface of the substrate 2 by LP-CVD, S
The iO ₂ film is etched back to form sidewalls 13 on the side walls of the first Poly-Si film 7 and the second Poly-Si film 8. Next, the PMOSFE is formed by the lithography technique.
A resist mask (not shown) covering a region for forming T is formed, and an NMOSFET of the substrate 2 is formed using the resist mask, the first Poly-Si film 7, the second Poly-Si film 8, and the sidewall 13 as a mask. Arsenic ions are implanted into the region to be ionized, for example, under the conditions that the ion energy is 20 keV and the dose is 3 × 10 ¹⁵ ions / cm ² .
An N-type source / drain region 14 is formed in the surface layer of the substrate 2 in the region where the NMOSFET is to be formed.

After removing the resist mask, a resist mask (not shown) is formed by lithography to cover the region for forming the NMOSFET, and the resist mask, the first Poly-Si film 7 and the second Poly-Si film 8, Using the side wall 13 as a mask, the P
Boron difluoride ions, for example, with an ion energy of 30 keV and a dose of 3
Ion implantation is performed under the condition of × 10 ¹⁵ / cm ² . Thus, a P-type source / drain region 15 is formed in the surface layer portion of the substrate 2 in the region where the PMOSFET is to be formed. Next, the resist mask is removed. At the time of ion implantation for forming the source / drain regions 14 and 15, arsenic and boron are simultaneously introduced into the first Poly-Si film 7.

Subsequently, for example, rapid thermal annealing at about 1000 ° C. for about 10 seconds (rapid thermal annealing) is performed.
The impurities and the like that have been ion-implanted earlier are activated by aling (RTA). As a result, the first Poly-Si film 7 in the region where the NMOSFET is formed is N ⁺ type, PMOSFE
The first Poly-Si film 7 in the region where T is formed becomes P ⁺ type, and a so-called dual gate is formed.

Thereafter, titanium (T) is formed on the entire surface of the substrate 2 as shown in FIG.
i) Deposit the film 16 to a thickness of, for example, about 30 nm. Subsequently, for example, the Ti film 16 and the surface layer portions of the source / drain regions 14 and 15 are caused to undergo a silicidation reaction by RTA at 650 ° C. for 30 seconds.
Region forming a T, a first 2Poly-Si film 8 and the Ti film 16 regions of the respective forming the PMOSFET by silicidation reaction to form titanium silicide (TiSi _x) layer.

Then, sulfuric acid (H_TwoSO_Four) And peroxide
Hydrogen (H_TwoO_TwoField oxide film by mixed chemicals)
3 and the unreacted Ti film 16 on the side wall 13
After removal, for example, at 800 ° C. for 30 seconds,
Knead to make TiSi _xFIG. 3 shows the phase transition of the membrane.
As shown in (g), the source / drain regions 14 and 15
Low resistance metal compound on the surface layer and on the second Poly-Si film 8
A film 17 is formed. As a result, N⁺
Type poly-Si film stack 9 and metal compound film layer 17
N⁺With MOSFET type gate electrode 10
8 is formed and P⁺Poly-Si film stack
9 composed of a metal compound film 9 and a metal compound film 17⁺Type gate electrode 1
A PMOSFET 19 with 0 is obtained.

Thereafter, although not shown, an interlayer insulating film is formed on the entire surface of the substrate 2 by, for example, a CVD method, and a gate and a wiring are formed on the interlayer insulating film using a wiring material such as aluminum (Al).
Wiring such as source / drain is formed. By the above steps, the NMOSFET having the N ⁺ type gate electrode 10
18 and a PMOSFE having a P ⁺ type gate electrode 10
The CMOSFET 1 of the first embodiment having T19 is completed.

In the above-mentioned CMOSFET 1, the first Poly-
A second Poly-Si film 8 is formed on the Si film 7 by SIPOS. As described above, since SIPOS is a poly-Si layer containing oxygen at a high concentration, it is known that SIPOS works as a stopper layer against diffusion of impurities.
It has properties close to O ₂ film. Therefore, the second Poly-Si
The film 8 functions as a diffusion stopper layer for preventing impurities doped in the first Poly-Si film 7 from diffusing into the metal compound film 17 during a high-temperature heat treatment performed when manufacturing the CMOSFET 1. .

For this reason, the CMOSF according to the first embodiment
According to ET1, high-temperature heat treatment performed after the formation of the metal compound film 17, for example, high-temperature CVD for forming an interlayer insulating film,
During the high temperature heat treatment such as oxidation and annealing, the first Po
The diffusion of arsenic, which is an N-type impurity, and boron, which is a P-type impurity, doped in the ly-Si film 7 into the second Poly-Si film 8 can be suppressed. Further, diffusion of these impurities into the metal compound film 17 can be suppressed. The second Poly-Si film 8 is made of SiH
Since it is formed by the LP-CVD method using ₄ and N ₂ O as a source gas, it is always formed stably in a state containing oxygen at a high concentration. Therefore, the interdiffusion of the N-type and P-type impurities in the metal compound film 17 is suppressed, so that a change in the Fermi level of the gate electrode 10 and a change in Vth due to the interdiffusion can be prevented.

Further, the diffusion of impurities in the first Poly-Si film 7 into the metal compound film 17 can be suppressed.
A decrease in the impurity concentration in the Poly-Si film 7 can be prevented, and the depletion of the gate electrode 10 due to this can be prevented. Further, the first Poly-Si film 7 on the gate oxide film 6
Is formed of a normal Poly-Si film having an oxygen concentration of less than 10 ¹⁸ / cm ^2, so that depletion of the gate electrode 10 can be suppressed by increasing the carrier concentration in the first Poly-Si film 7. Therefore, it is possible to realize the CMOSFET 1 in which a decrease in the MOSFET characteristics due to the fluctuation of Vth and the depletion of the gate electrode 10 is suppressed.

In the method of manufacturing the CMOSFET 1 according to the first embodiment, the first Poly-Si
Although the film 7 was formed (see FIG. 2B), the first Poly-Si
It is also possible to form an amorphous Si (a-Si) film instead of the film 7. In this case, the a-Si film is crystallized by the subsequent heat treatment, so that the first Poly-Si film 7 is formed on the gate oxide film 6. Although the metal compound film of the present invention to form a TiSi _x film, other metal compounds, tungsten silicide (WSi _x) layer, a cobalt silicide (CoS
i _x) film, a nickel silicide (NiSi _x) refractory metal silicide film or a titanium oxynitride, such as films (TiON)
A film, a titanium nitride (TiN) film, or the like may be formed, and the metal compound may be replaced with a metal film such as a titanium (Ti) film, a tungsten (W) film, or titanium tungsten (TiW).

Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to a sectional side view of a main part shown in FIG. In the drawings, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. CMO of this embodiment
The SFET 20 differs from the first embodiment in that the gate electrode 23 has a W-polycide structure.

That is, the NMOSFET 18 on the substrate 2
The N ⁺ -type gate electrode 23 and the P ⁺ -type gate electrode 23 provided in the formation region of the PMOSFET 19 and the formation region of the PMOSFET 19, respectively, are the same as those of the first embodiment.
An offset oxide film 22 made of a SiO ₂ film is formed on a W-polycide layer made up of a WSi _x metal compound film 21 formed on this and an upper layer thereof. Sidewalls 13 are formed on the side walls of the gate electrode 23 made of a W-polycide layer with such an offset oxide film 22. N-type source / drain regions 14
And the surface layers of the P-type source / drain regions 15 are not silicided.

In manufacturing the above-described CMOSFET 20, first, steps similar to those of the method of manufacturing the CMOSFET 1 according to the first embodiment are performed until the gate oxide film 6 is formed (see FIGS. 2A and 2B). Next, as shown in FIG. 5A, the field oxide film 3 is formed by the LP-CVD method.
A first Poly-Si film 7 is formed on the gate oxide film 6. Here, for example, SiH ₄ gas is used as a source gas,
L under conditions where the deposition temperature was set to about 580 ° C. to 620 ° C.
The first Poly-Si film 7 is, for example, 50
It is formed to a thickness of about nm to 150 nm.

Next, the PMOS is formed by lithography technology.
A resist mask (not shown) covering a region for forming an FET
By using the obtained resist mask, phosphorus is ion-implanted only in a region where an NMOSFET is to be formed to form an N ⁺ gate region 24. This ion implantation is performed, for example, under the condition that the dose is set to 3 × 10 ¹⁵ / cm ² . After removing the resist mask, a resist mask (not shown) for covering the region where the NMOSFET is to be formed is patterned by lithography technique, and boron is ion-implanted only into the region where the PMOSFET is to be formed using this resist mask. ^{+ A} gate region 25 is formed. This ion implantation is performed, for example, at a dose of 3 × 10
It is performed under the condition of ¹⁵ pieces / cm ² . After that, the resist mask used in the ion implantation is removed.

Subsequently, for example, in a nitrogen (N ₂ ) atmosphere,
Perform annealing 00 ° C. for about 10 minutes, phosphorus in the N ⁺ gate regions 24 formed in the previous ion implantation, the boron in the P ⁺ gate regions 25 of the N ⁺ gate region 24, P ⁺ gate region 25 first 1Poly- It is diffused into the Si film 7. This annealing can be performed by RTA. Then C
The second Poly-Si film is formed on the first Poly-Si film 7 by the VD method.
A film 8 is formed. Here, for example, the source gas and the flow rate are set to SiH ₄ / N ₂ O: 500 sccm / 20 sccm.
The second poly is formed by the CVD method under the conditions of about 30 sccm, an atmospheric pressure of about 20 Pa, and a deposition temperature of about 620 ° C.
-Forming the Si film 8 to a thickness of, for example, about 5 nm to 50 nm; These forming conditions are merely examples, and the parameters of the deposition temperature and other forming conditions can be appropriately changed as described above.

Next, as shown in FIG. 5A, the second Poly-
A metal compound film 21 is deposited on the Si film 8. Here, for example, a tungsten hexafluoride (WF ₆₎ gas and dichlorosilane (SiCl ₂ H ₂₎ gas as a raw material gas, and by an LP-CVD method of deposition temperature and 580 ° C. the conditions, metal made of WSi _x A compound film 21 is deposited to a thickness of about 100 nm. Furthermore, for example, SiH
₄ gas and O ₂ gas as source gases, and the deposition temperature is 4
By a CVD method at 20 ° C., an offset oxide film 22 is deposited to a thickness of 150 nm. Thus, a W-polycide layer with an offset oxide film 22 composed of the first Poly-Si film 7, the second Poly-Si film 8, and the metal compound film 21 is formed.

Next, anisotropic etching is performed using the resist patterned by the lithography technique as a mask, and as shown in FIG.
The W-polycide layer with the gate electrode 23 (FIG. 5D)
Reference pattern). In the anisotropic etching, for example, a fluorocarbon gas is used as an etching gas for the offset oxide film 22, and a Cl ₂ gas and an O ₂ gas are used as an etching gas for the W-polycide layer. Do. Thereby, the NMOSFET on the substrate 2
Is formed in the region where the first Poly-Si film 7 is N ⁺ type, and the gate electrode 23 where the first Poly-Si film 7 is P ⁺ type is formed in the region where the PMOSFET is formed. Thus, a so-called dual gate is formed. After that, the used resist mask is removed.

Next, arsenic ions are implanted into a region of the substrate 2 where an NMOSFET is to be formed, and N-type LDD regions 11 are formed on both sides of the gate electrode 23 of the substrate 2 in that region as shown in FIG. I do. In addition, the P
Boron difluoride ions are implanted into a region where a MOSFET is to be formed, and the gate electrode 2 of the substrate 2 in that region is implanted.
(3) P-type LDD regions 12 are formed at both sides. LDD
The regions 11 and 12 are formed under the same conditions as in the first embodiment, for example. Further, a SiO ₂ film is deposited on the entire surface of the substrate 2 to a thickness of about 150 nm by LP-CVD, and then the SiO ₂ film is etched back by anisotropic etching to form a sidewall 13 on the side wall of the gate electrode 23.

Next, arsenic ions, for example, ion energy of 20 are applied to the region of the substrate 2 where the NMOSFET is to be formed.
Ion implantation is performed under the conditions of keV and a dose of 3 × 10 ¹⁵ / cm ² , and an N-type source / drain region 14 is formed in the substrate 2 in that region. The PMOSFET on the substrate 2
Is formed, for example, with boron difluoride ions at an ion energy of 20 keV and a dose of 3 × 10 ¹⁵ ions /
Ion implantation is performed under the condition of cm ² , and a P-type source / drain region 15 is formed in the substrate 2 in that region. Then, for example, the impurities doped in the source / drain regions 14 and 15 are activated by RTA at 1000 ° C. for 10 seconds.

Thereafter, although not shown, an interlayer insulating film is formed on the entire surface of the substrate 2 by, for example, a CVD method, and wiring such as a gate and a source / drain is formed on the interlayer insulating film using a wiring material such as Al. Through the above steps, the NMOSFET18 having an N ⁺ -type gate electrode 23, CMOSFET20 of the second embodiment and a PMOSFET23 having a P ⁺ -type gate electrode 23 is completed.

CMOSFET 2 manufactured as described above
In the case of No. 0, as in the first embodiment, the metal compound layer 21 is formed on the Poly-Si film laminate 9 including the second Poly-Si film 8 serving as the impurity diffusion stopper layer. For this reason, the metal compound film 2
At the time of high-temperature heat treatment performed after the formation of 1, for example, high-temperature CVD for forming an interlayer insulating film, or high-temperature heat treatment such as oxidation and annealing, arsenic and boron in the first Poly-Si film 7 are transferred to the second Poly-Si film 8. Diffusion can be suppressed, and further diffusion to the metal compound film 21 can be suppressed. Further, since the first Poly-Si film 7 on the gate oxide film 6 is made of a normal Poly-Si film having an oxygen concentration of 10 ¹⁸ / cm ² , the gate by increasing the carrier concentration in the first Poly-Si film 7 is increased. Depletion of the electrode 23 can be suppressed.

Therefore, the same effect as that of the first embodiment, that is, fluctuation of Vth and depletion of the gate electrode 23 due to mutual diffusion of impurities can be prevented, and the effect of realizing the CMOSFET 20 in which the deterioration of the MOSFET characteristics is suppressed can be realized. can get. The metal compounds of the formed WSi _x film 21
Even if fluorine is contained, the second Poly-Si film 8
This suppresses the diffusion of fluorine into the first Poly-Si film 7, so that the boron in the first Poly-Si film 7 is not affected by the fluorine in the metal compound film 21. Therefore, the accelerated diffusion of boron due to the influence of fluorine can be prevented, and the phenomenon that boron penetrates through gate oxide film 6 and diffuses to substrate 2 can also be prevented. Therefore, the MOSFET caused by boron penetrating through the gate oxide film 6
It is possible to obtain the CMOSFET 20 in which the fluctuation of the characteristics is prevented.

The CMOSFET 20 of the second embodiment
In the manufacturing method of the first embodiment, the first poly-
Although the Si film 7 was formed (see FIG. 5A), the first Poly-
It is also possible to form an a-Si film instead of the Si film 7. Also, WSix _{x is} used as the metal compound film in the present invention.
Although the film is formed, another refractory metal silicide film or the like may be used, or the metal compound may be replaced with a metal film.

In the dual gate process, the poly-Si film of the gate electrode has a two-layer structure and the upper poly-Si film is formed.
A structure in which the Si film is made of poly-Si having a large crystal grain size,
Chemical oxide between ly-Si film
A method of interposing a layer has been proposed by the present inventors (H8-162961). It is disclosed that the chemical oxide layer increases the grain size of the upper Poly-Si layer and also serves as a stopper layer for impurity diffusion. Therefore, next, a CM in which this chemical oxide layer portion is constituted by the second Poly-Si film of the present invention is used.
An OSFET will be described as a third embodiment of a semiconductor device according to the present invention with reference to a sectional side view of a main part shown in FIG. In the drawings, the same components as those of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 6, in the MOSFET 30, a region where the NMOSFET 18 is formed on the substrate 2,
N provided in the formation region of the PMOSFET 19
^The configuration is the same as that of the second embodiment except for the ⁺ type gate electrode 32 and the P ⁺ type gate electrode 32. That is, N ⁺
Type gate electrode 32 and P ⁺ type gate electrode 32
Consisting -Si film stack 31 and the WSi _x formed in the upper metal compound film 21. W- on the polycide layer is constituted is further offset oxide film 22 is formed.

In the Poly-Si film laminate 31, a first Poly-Si film 7 is formed on a gate oxide film 6, and a second Poly-Si film 7
A poly-Si film 8 is stacked, and the first Poly-Si film 7 is further stacked on the second Poly-Si film 8 to form a three-layer stack. First and bottom poly-Si films 7
Is Poly-S having a normal oxygen content as in the first embodiment.
The second Poly-Si film 8 is made of, for example, SIPOS containing oxygen more than the oxygen content of the first Poly-Si film 7 as in the first embodiment.

The second Poly-Si film 8 is formed of the second Poly-S
When the uppermost first Poly-Si film 7 is formed on the i-film 8 by lamination, the film thickness is such that the uppermost first Poly-Si film 7 does not inherit the crystallinity of the lowermost first Poly-Si film 7. The first poly-Si film 7 as the lowermost layer is formed to have a thickness that suppresses diffusion of impurities doped into the first poly-Si film 7. Here, the thickness is, for example, about 2 nm to 20 nm. Further, the uppermost first Poly-Si film 7 has a crystal grain size larger than that of the lowermost first Poly-Si film 7,
For example, it is formed of a film having a large particle size of about 20 nm to 1 μm.

The CMOSFE according to the third embodiment
At T30, the first Poly-Si film 7 and the second Poly-Si
-Si film 8, the sidewalls 13 on the side wall of the 1poly-Si film 7, WSi _x of the metal compound film 21 made of W- polycide layer and a gate electrode 32 consisting of the upper layer of the offset oxide film 22 is formed.

In manufacturing the above-described CMOSFET 30, first, the same steps as those in the method of manufacturing the CMOSFET 1 according to the first embodiment are performed until the formation of the gate oxide film 6 (see FIGS. 2A and 2B). Next, as shown in FIG. 7A, the field oxide film 3 is formed by the LP-CVD method.
A first Poly-Si film 7 is formed on the gate oxide film 6. Here, for example, SiH ₄ gas is used as a source gas,
L under conditions where the deposition temperature was set to about 580 ° C. to 620 ° C.
The first Poly-Si film 7 is, for example, 50
It is formed to a thickness of about 100 nm to 100 nm.

Next, the first Poly-Si is formed by the CVD method.
A second Poly-Si film 8 is formed on the film 7. Here, for example, the source gas and the flow rate are set to SiH ₄ / N ₂ O: 500 s.
ccm / 20sccm-30sccm, ambient pressure is 2
CV under conditions of about 0 Pa and a deposition temperature of about 620 ° C.
The second Poly-Si film 8 is formed to a thickness of, for example, 2 nm to 20
It is formed to a thickness of about nm. These forming conditions are merely examples, and the parameters of the deposition temperature and other forming conditions can be appropriately changed as described above. Then, the second Poly
A-Si film on the Si film 8 is, for example, 50 nm to 100 n
The thickness is about m. The a-Si film is formed by, for example, using SiH ₄ gas as a source gas and setting the deposition temperature to 530 ° C.
It is performed by the LP-CVD method under the condition of about 580 ° C.

Next, the PMOS is formed by lithography technology.
A resist mask (not shown) covering a region for forming an FET
By using the obtained resist mask, phosphorus is ion-implanted only in a region where an NMOSFET is to be formed to form an N ⁺ gate region 24. This ion implantation is performed, for example, under the condition that the dose is set to 3 × 10 ¹⁵ / cm ² . After removing the resist mask, a resist mask (not shown) for covering the region where the NMOSFET is to be formed is patterned by lithography technique, and boron is ion-implanted only into the region where the PMOSFET is to be formed using this resist mask. ^{+ A} gate region 25 is formed. This ion implantation is performed, for example, at a dose of 3 × 10
It is performed under the condition of ¹⁵ pieces / cm ² . After that, the resist mask used in the ion implantation is removed.

Subsequently, the a-Si film is solid-phase-grown and crystallized by performing low-temperature long-time annealing at about 650 ° C. for about 10 hours in an N ₂ atmosphere, for example.
The ly-Si film 7 is formed. The a-Si film is the second Poly-Si
Since the first Poly-Si film 7 formed by crystallization of the a-Si film is formed on the film 8, the crystal grain size of the first Poly-Si film 7 is the lowermost first Po-Si film previously formed by the LP-CVD method.
The grain size is larger than the crystal grain size of the ly-Si film 7 and the number of crystal grain boundaries is small. Next, for example, annealing is performed at about 800 ° C. for about 10 minutes, and the phosphorus in the N ⁺ gate region 24 and the boron in the P ⁺ gate region 25 formed by the previous ion implantation are replaced with the first Poly-Si in the respective regions 24 and 25. Diffusion into the film 7. This annealing can be performed by RTA.

Next, as shown in FIG. 7A, a metal compound film 21 is deposited on the uppermost first poly-Si film 7 to a thickness of about 100 nm. Further, an offset oxide film 22 is deposited on this upper layer to a thickness of about 150 nm. The formation of the metal compound film 21 and the offset oxide film 22 is performed, for example, in the second
This is performed under the conditions described in the embodiment. As a result, the first Poly
A W-polycide layer with an offset oxide film 22 composed of a -Si film 7, a second Poly-Si film 8, a first Poly-Si film 7, a metal compound film 21, and an offset oxide film 22 is formed.

Next, anisotropic etching is performed using the resist patterned by the lithography technique as a mask, and as shown in FIG.
Is formed in the pattern of the gate electrode 32. In the anisotropic etching, for example, a fluorocarbon gas is used as an etching gas for the offset oxide film 22, and a C-type gas is used for the W-polycide layer.
The etching is performed using l ₂ gas and O ₂ gas as an etching gas.
Thus, the gate electrode 32 in which the first Poly-Si film 7 is of the N ⁺ type is formed in the region of the substrate 2 where the NMOSFET is to be formed, and the first Poly-S region of the region where the PMOSFET is to be formed.
A so-called dual gate is formed by forming a gate electrode 32 in which the i film 7 is a P ⁺ type. After that, the used resist mask is removed.

Next, arsenic ions are ion-implanted into a region of the substrate 2 where an NMOSFET is to be formed, and N-type LDD regions 11 are formed on both sides of the gate electrode 32 of the substrate 2 in that region as shown in FIG. I do. In addition, the P
Boron difluoride ions are implanted into a region where a MOSFET is to be formed, and a gate electrode 3 of the substrate 2 in that region is implanted.
2. P-type LDD regions 12 are formed on both sides. LDD
The regions 11 and 12 are formed under the same conditions as in the first embodiment, for example. Further, an SiO ₂ film is deposited on the entire surface of the substrate 2 to a thickness of about 150 nm by the LP-CVD method, and then the SiO ₂ film is etched back by anisotropic etching to form a sidewall 13 on the side wall of the gate electrode 32.

Then, arsenic ions, for example, ion energy of 20 are applied to the region of the substrate 2 where the NMOSFET is to be formed.
Ion implantation is performed under the conditions of keV and a dose of 3 × 10 ¹⁵ / cm ² , and an N-type source / drain region 14 is formed in the substrate 2 in that region. The PMOSFET on the substrate 2
Is formed, for example, with boron difluoride ions at an ion energy of 20 keV and a dose of 3 × 10 ¹⁵ ions /
Ion implantation is performed under the condition of cm ² , and a P-type source / drain region 15 is formed in the substrate 2 in that region. And
For example, the impurities doped in the source / drain regions 14 and 15 are activated by RTA at 1000 ° C. for 10 seconds.

Thereafter, although not shown, an interlayer insulating film is formed on the entire surface of the substrate 2 by, for example, a CVD method, and wiring such as a gate and source / drain is formed on the interlayer insulating film using a wiring material such as Al. Through the above steps, the NMOSFET18 having a gate electrode 32 of the N ⁺ type, CMOSFETs 30 of the third embodiment and a PMOSFET19 having a gate electrode 32 of the P ⁺ -type is completed.

CMOSFET 3 manufactured as described above
0, as in the first embodiment, the Poly-Si laminate 31
Since the second Poly-Si film 8 serving as the impurity diffusion stopper layer is formed on the lowermost first Poly-Si film 7,
In the high temperature heat treatment performed after the formation of the metal compound film 21 in the manufacture of the CMOSFET 30, the lowermost first Poly-S
Arsenic and boron in the i film 7 can be suppressed from diffusing into the first Poly-Si film 7 as the uppermost layer and further into the metal compound film 21. Further, since the uppermost first Poly-Si film 7 is formed of a Poly-Si film having a large grain size and a small number of crystal boundaries,
This layer itself also serves as a diffusion stopper layer for impurities, and can prevent arsenic and boron in the uppermost first Poly-Si film 7 from diffusing into the upper metal compound film 21.

Further, even _if the WSix metal compound film 21 contains fluorine, the fluorine in the metal compound film 21 is reduced by the first Poly-Si film 7 and the second Poly-Si film 8 as the uppermost layer. Diffusion into the Si film 7 can be suppressed. Also, the first Po on the gate oxide film 6
The ly-Si film 7 has a normal oxygen concentration of less than 10 ¹⁸ / cm ²
Since the gate electrode 32 is made of the Poly-Si film, the depletion of the gate electrode 32 can be suppressed by increasing the carrier concentration in the first Poly-Si film 7.

Therefore, similarly to the second embodiment, it is possible to prevent Vth fluctuation and depletion of the gate electrode 32 due to the interdiffusion of impurities, and to prevent boron in the first Poly-Si film 7 from forming in the metal compound film 21. Can prevent the penetration of boron from the gate oxide film 6 due to the accelerated diffusion due to the influence of fluorine, so that the CMOSFET 30 having excellent MOSFET characteristics can be realized. Furthermore, the Poly-Si film laminate 31
In this case, since the uppermost first poly-Si film 7 has a large crystal grain size, the heat resistance (Thermal Budget) of the gate electrode 32 can be improved.

The CMOSFET 30 of the third embodiment
So although a metal compound film of the present invention to form a WSi _x film may be other refractory metal silicide film or the like, also can be replaced with the metal compound to the metal film as a matter of course. In the first and second embodiments, a poly-Si film laminate having a two-layer structure has been described. In the third embodiment, a poly-Si film laminate having a three-layer structure has been described. It is needless to say that the laminate may be composed of four or more layers. Further, in the first, second and third embodiments, the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type may be P-type and the second conductivity type may be N-type. .

The numerical conditions of each process in the manufacturing method described in the first to third embodiments are examples. Therefore, the conditions are not limited to the above-described conditions as long as the optimal conditions for achieving each processing are selected.

[0071]

As described above, according to the semiconductor device of the present invention, the polysilicon film laminate of the first gate electrode and the second gate electrode includes the first polysilicon film and the second polysilicon film formed on the first polysilicon film. And a polysilicon film,
Since the second polysilicon film contains oxygen at a high concentration, when the semiconductor device is further subjected to a high-temperature heat treatment,
The polysilicon film becomes a stopper layer for impurity diffusion,
It is possible to prevent impurities of the first conductivity type and the second conductivity type in the first polysilicon film from diffusing into the upper metal film or metal compound film. Therefore, it is possible to suppress mutual diffusion of impurities of different conductivity types generated in the metal film or the metal compound film and to maintain the first gate electrode and the second gate electrode maintaining the impurity concentration in the polysilicon film at a high concentration. V can be obtained, and V
A semiconductor device having excellent device characteristics in which fluctuation of th and depletion of the gate electrode are suppressed can be manufactured.

[0072]

[Brief description of the drawings]

FIG. 1 is a sectional side view of a main part showing a first embodiment of a semiconductor device according to the present invention.

FIGS. 2A to 2C are cross-sectional views (part 1) of an essential part for explaining an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps;

FIGS. 3D to 3G are cross-sectional views (part 2) of an essential part for explaining an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps;

FIG. 4 is a side sectional view showing a main part of a second embodiment of the semiconductor device according to the present invention;

FIGS. 5A to 5C are main-portion side cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment in the order of steps;

FIG. 6 is a side sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention.

FIGS. 7A to 7C are side sectional views of a main part for explaining an example of a method for manufacturing a semiconductor device according to a third embodiment in the order of steps;

FIG. 8 is a diagram for explaining a problem of the present invention.

[Explanation of symbols]

1,20,30 ... CMOSFET, 2 ... substrate, 7 ... first
Poly-Si film, 8 ... second Poly-Si film, 9, 31 ... Poly
-Si film laminated body, 10, 23, 32 ... gate electrode, 1
7, 21: metal compound film, 18: NMOSFET, 19
... PMOSFET

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-38103 (JP, A) JP-A-9-69521 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 29/78 H01L 21/336 H01L 21/28 H01L 29/49

Claims (3)

(57) [Claims] A first transistor including a first gate electrode of a first conductivity type and a second transistor including a second gate electrode of a second conductivity type are formed on a substrate. A first gate electrode and a second gate electrode are formed by a continuous gate electrode wiring, and the gate electrode wiring is formed on the substrate by a polysilicon film laminate and a metal film or a metal compound formed thereon. In the semiconductor device comprising a film, the polysilicon film laminate may be formed on a lowermost first polysilicon film and on the lowermost first polysilicon film.
The oxygen content in the lowermost first polysilicon film.
A second polysilicon film containing much more oxygen, and a second polysilicon film formed on the second polysilicon film;
2Lower oxygen content than polysilicon film
Larger than the crystal grain size of the lowermost first polysilicon film
An uppermost first polysilicon film having a crystal grain size.
Wherein a configured Te. 2. The method according to claim 1, wherein the second polysilicon film is formed by a chemical vapor deposition method performed under reduced pressure using a source gas containing silane gas and dinitrogen monoxide gas. Item 2. The semiconductor device according to item 1. 3. The semiconductor device according to claim 1, wherein the oxygen content in said second polysilicon film is not less than 10 ¹⁸ / cm ^{3 and not} more than 10 ²² / cm ³ .