JP3338355B2 - Semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The technical field to which the present invention pertains is:
The present invention relates to a semiconductor circuit which has a high operation speed, is multifunctional, and has a large degree of freedom in design.

[0002]

2. Description of the Related Art As an example of the prior art close to the present invention, there is known a logic gate of a system in which two negative differential resistance elements are connected in series and a potential at the connection point is taken out as an output (KJ. et a1. Ext, Abs, “1994 Solid State D
evices and Materia1s, "Yokohama, 1994, p979). FIG. 12 is a circuit diagram of the above-mentioned prior art.
, 1 is a first negative differential resistance element, 2 is a second negative differential resistance element, and 3 is a first field effect transistor. The two negative differential resistance elements are, for example, resonance tunnel diodes.

The current-voltage characteristics of one negative differential resistance element are as shown in FIG. When two negative differential resistance elements are connected in series, the stable point of the system is the power supply voltage Vbi
It changes as shown in FIG. 14 according to as. In FIG. 14, D ₁ indicates a current-voltage characteristic curve of the first negative differential resistance element 1, and D ₂ indicates a current-voltage characteristic curve of the second negative differential resistance element 2. First, as shown in FIG. 14A, when Vbias is smaller than twice the peak voltage Vp, the point A (voltage V _A )
Is a stable point, and the output voltage is Vbias / 2. Vbias
The Increase, exceeds 2Vp as shown in FIG. 14 (b), a stable point of the system becomes two points B and C, and the output voltage is V _B or V _C according to the stable point. Here, which of the stable points B and C is settled depends on the difference between the peak currents of the two negative differential resistance elements. For example, the larger the negative peak current differential resistance element 1 on the driver side, the state of the system point B, and the output voltage becomes V _B. On the other hand, when the peak current of the negative differential resistance element 2 on the load side is large, V _C
Is output.

[0004] In order to form a logic circuit using these elements, the following two elements are required. The first element modulates the peak current according to the input voltage, thereby making the magnitude relationship between the peak current values of the first negative differential resistance element 1 and the second negative differential resistance element 2 variable. It is. One method for this is to connect the field effect transistor 3 in parallel with the negative differential resistance element. At this time, as shown in FIG. 15, the current flowing through this composite element is the sum of the two. This means that the peak current has been effectively modulated. Specifically, when the circuit is designed, the area of the bi-differential differential resistance element is determined. The input voltage is set to “Hi” so that the sum of the peak currents is smaller than the peak current of the negative differential resistance element 2 on the load side.
gh ”, the sum of the current of the field effect transistor 3 and the peak current of the negative differential resistance element 1 is equal to the negative differential resistance element 2
Must be designed to be larger than the peak current. The second factor is to use a drive voltage that periodically changes above and below 2Vp as Vbias. This acts as a clock, switching occurs when the voltage rises, allowing the operation to hold the output while the voltage is above 2Vp.

[0005]

In order to drive such a conventional logic gate, a logic gate drive circuit capable of supplying a current of about the peak current of the negative differential resistance element is required. . In order to realize a logic gate driving circuit having a high current driving capability, for example, it is conceivable to use a field-effect transistor having a wide gate width. However, a signal for operating the driving circuit is actually Since the driving force generated in the chip is small, it is very difficult to operate the driving circuit composed of a field-effect transistor having a wide gate width at high speed by directly using the driving force. Therefore, a drive circuit is obtained by preparing a plurality of amplifier circuits and gradually increasing the gate width.

As a result, although the prior art is characterized in that a high-speed and low-power consumption circuit can be designed with a simple circuit configuration, it is necessary to prepare a large-scale drive circuit. In addition, power consumption will increase. In addition, if the driving circuit is reduced in size and power consumption is reduced, a transistor having a narrow gate width drives a transistor having a wide gate width, so that high-speed operation cannot be realized. Therefore, high speed
Techniques for driving the negative differential resistance element circuit with a small circuit configuration without compromising the characteristics of the negative differential resistance element circuit, such as low power consumption, were required. Did not.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and enables a circuit constituted by a negative differential resistance element to operate at high speed even if constituted by a transistor having a small gate width. It is an object of the present invention to provide a semiconductor circuit.

[0008]

In order to achieve the above object, the present invention is configured as described in the appended claims. That is, the invention according to claim 1 relates to a basic circuit configuration method, in which a circuit composed of two negative differential resistance elements connected in series and a first transistor for driving the circuit are connected in parallel. And connected in series with a constant current source. This configuration corresponds to, for example, the semiconductor circuit in the embodiment shown in FIG. 1. For example, the first potential is grounded, and the second potential is V
ss.

The invention described in claim 2 is the first invention.
Wherein an element capable of peak current modulation is used as at least one of the first negative differential resistance element and the second negative differential resistance element, and a peak current modulation terminal of the element is used as a data input terminal; Is a clock input terminal to form a logic circuit. This configuration corresponds to, for example, the logic circuit in the embodiment shown in FIG. 4 or FIG. 6, and FIG. 4 is a circuit in which the first negative differential resistance element is an element capable of peak current modulation. A circuit that outputs in synchronization with the clock signal is obtained. FIG. 6 shows a circuit in which the second negative differential resistance element is an element capable of peak current modulation, and a circuit that outputs an inverted data input signal (a signal obtained by inverting the data input signal) in synchronization with a clock signal. Is obtained. In addition,
In FIGS. 4 and 6, as a device capable of peak current modulation, a device in which a field effect transistor is connected in parallel to both ends of a negative differential resistance device is used, but such a function is formed as one device. A thing may be used.

According to a third aspect of the present invention, the first negative differential resistance element is an element capable of peak current modulation.
And a second circuit using the second negative differential resistance element as an element capable of modulating peak current to form a 1/2 static frequency divider. This configuration corresponds to, for example, the logic circuit in the embodiment shown in FIG.

[0011] The invention described in claim 4 is the same as the claim 3.
And an OR circuit (OR circuit or NOR circuit) is added to the invention described in (1) to constitute a 1/2 static frequency divider that outputs a signal having a duty ratio of 50%. This configuration corresponds to, for example, the logic circuit in the embodiment shown in FIG.

The invention described in claim 5 is the first invention.
1 shows a specific example of the configuration of FIG. The above configuration is described, for example, in the embodiment shown in FIG.

[0013] The invention according to claim 6 is the invention according to claim 2.
5 shows a specific example of claim 5, wherein the element capable of peak current modulation connects the source and the drain of the field effect transistor to both ends of the negative differential resistance element, and uses the gate as a terminal for peak current modulation. Or an emitter and a collector of a bipolar transistor are respectively connected to both ends of a negative differential resistance element, and a base is used as a peak current modulation terminal. The above configuration is described in the embodiments shown in FIGS. 4, 6, 8, and 10, for example.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention basically has a configuration in which a field effect transistor is connected in parallel to two series-connected negative differential resistance element circuits, and a constant current source and these are connected in parallel. This is a circuit that enables high-speed driving of two serially connected negative differential resistance element circuits with a field-effect transistor having a small gate width.

(First Embodiment) A circuit for outputting an input signal as a signal having a larger driving capability An embodiment of the present invention in which an input signal is output as a signal having a larger driving capability will be described. I do. FIG. 1 illustrates an example of a circuit in this embodiment. The circuit shown in FIG. 1A has one signal input terminal S and one output terminal Q
And In this circuit, two negative differential resistance elements 1 and 2 are connected in series, terminals at both ends of the series circuit are respectively connected to a drain electrode and a source electrode of the field effect transistor 3, and an electric field is applied to the series circuit. Effect transistor 3
Are connected in parallel. One end of the parallel circuit (the drain electrode side of the field effect transistor 3) is grounded, and the other end of the parallel circuit (the source electrode side of the field effect transistor 3) is connected to a constant current source 5 to which the voltage Vss is applied. Connect with Then, the gate electrode of the field effect transistor 3 is connected to the signal input terminal S to input a signal, and the connection point between the two negative differential resistance elements 1 and 2 is set as the output terminal Q, and the potential is output. Circuit. Also, the negative differential resistance element 1
The emitter area of the negative differential resistance element 2 is larger than that of the negative differential resistance element 2.

As the above constant current source 5, for example, FIG.
As shown in (b), a circuit in which the voltage Vss is applied to the source electrode of the field effect transistor and the potential between the gate and source electrodes is kept constant can be used. FIG.
In (b), an example is shown in which the gate and the source are directly connected to make the potentials of both electrodes equal, but different potentials may be used as long as the potential between the gate and source electrodes is constant.

The negative differential resistance elements 1 and 2 include:
Resonant tunnel diodes and Esaki diodes can be used. Further, a bipolar transistor can be used instead of the field effect transistor 3. In this case, the emitter electrode of the bipolar transistor may be connected instead of the source electrode of the field effect transistor, the collector electrode may be connected instead of the drain electrode, and the base electrode may be connected instead of the gate electrode.

In the circuit of FIG. 1, if the voltage Vin applied to the signal input terminal S is "High", the potential Vout at the output terminal Q is always "High", and while Vin is "Low", the potential Vout is Vout. "Low" is always obtained.

Next, a specific output determination process will be described. The current flowing between the drain and source of the field effect transistor 3 is Id, and the current supplied from the constant current source 5 is Id.
s, the current flowing in the series circuit 6 when the voltage Vr is applied to the series circuit 6 in which the negative differential resistance element 1 and the negative differential resistance element 2 are connected in series is Ir, and the negative differential resistance element 1 is
If the peak current density is Ip and the peak voltage is Vp, the operating conditions of the present embodiment are as follows: (1) The constant current source 5 has Is ≧ Ip
And (2) the gate-source potential of the field effect transistor 3 when Id = Is is 2 Vp or less. It is.

The source potential Vs of the field-effect transistor 3 according to the present embodiment is determined so as to satisfy Id = Is-Ir and Vs = 0-Vr. If Ir = 0, Id = Is
Since Is is a constant current, Vs is Vin−V
The difference of s is kept constant, and changes in accordance with Vin so as to satisfy Id = Is. However, actually, Vr = ┃
Since 0−Vs┃> 0, Ir> 0, and Ir depends on Vs, Vin−Vs is not constant and I−Vs is not constant.
Vs will be determined so as to satisfy d = Is-Ir.

For example, if “High” (〜0 potential) is applied as Vin, even if Ir = 0, the operating condition (2)
Therefore, Vr = {0−Vs} ≧ 2Vp is assured, so that the series circuit 6 is in a monostable state (the characteristic shown in FIG. 2 (a)) according to the prior art. Actually, Vr = ┃
Since 0−Vs┃> 0, that is, Ir> 0, Id = Is−Ir
Since <Is, the value of Vin−Vs becomes smaller as compared to the case where Ir = 0, and Vs shifts to the 0 potential side. At this time, since Vr <2Vp, the output "High" is obtained because the series circuit 6 is in a monostable state.

When Vin decreases, Vs also changes to a low potential (= Vr increases). At the same time, Ir decreases.
Increase (see FIG. 2A), and Id (= Is-I
To reduce r), the value of Vin-Vs decreases. And V
When r = {0−Vs} = 2Vp, that is, Ir = Ip
Then, the value of Vin−Vs becomes a minimum, and almost no current flows through the field effect transistor 3 and becomes Id〜0. When Vin further decreases, whether the series circuit 6 remains in the monostable state or transits to the bistable state (the characteristic shown in FIG. 2B) becomes a problem in the operation of the circuit. Even if it is in the state, since Ir <Ip, the current I
d will flow. For that purpose, Vin−Vs keeps a value equal to or more than the threshold value of the field effect transistor 3, and therefore, as Vin decreases, Vs decreases.
Since Vr = {0−Vs}> 2Vp, the series circuit 6 transitions to the bistable state. The operation of the series circuit 6 at the time of the monostable / bistable transition is the same as that of the prior art. As described above, since the emitter areas of the negative differential resistance element 1 and the negative differential resistance element 2 are set to be larger in the negative differential resistance element 2, Vr = {0−Vs}> 2Vp. Where the output changes. That is, Vout also decreases as Vin decreases, and when Vin is "Low", the output also becomes "Low".

Specifically, the transconductance is 75
HEMT (High level) with a threshold of about -0.2 V
When a high electron mobility field effect transistor) and a negative differential resistance element with Ip = about 6 mA are used, the circuit operates at high speed with a HEMT having a gate width of about 30 μm, as shown in FIG. An output corresponding to an appropriate input signal is obtained.

Since the driving capability of the series circuit 6 composed of two negative differential resistance elements is high, the input section of the next stage has a gate width wider than that of the field-effect transistor used in the present embodiment. Even if one is used, the circuit of the present invention can operate at high speed without attenuating the amplitude. Therefore, the circuit of this embodiment can be used as a driver circuit or an amplifier circuit.

(Second Embodiment) A circuit for outputting a data input signal in synchronization with a clock signal An embodiment of the present invention in which a data input signal is output in synchronization with a clock will be described. FIG. 4 illustrates an example of a circuit in this embodiment. The circuit shown in FIG. 4 has the same configuration as the circuit described in the first embodiment, and further has a second field-effect transistor 4 connected in parallel with the negative differential resistance element 1, and a gate thereof. The peak current modulation of the negative differential resistance element 1 is enabled by applying a voltage to the electrode. In this embodiment, a configuration in which a negative differential resistance element and a field-effect transistor are connected in parallel is used as an element capable of peak current modulation, but such a function is used as one element. The formed one may be used. The signal input method is such that the gate electrode of the field effect transistor 4 is connected to the data signal input terminal D, and the gate electrode of the field effect transistor 3 is connected to the clock signal input terminal CK.

In the circuit shown in FIG.
The behavior of the source potential Vs of the field-effect transistor 3 with respect to the voltage Vck applied to K is the same as in the first embodiment. Since the output is determined by the same principle as in the prior art, if the data signal applied to the data signal input terminal D when Vck changes from “High” to “Low”, the output is “High”. The output becomes "Low" if the data signal is "Low". While Vck is "Low", the output does not change even if the data signal changes. That is, as shown in the timing diagram of FIG. 5, a circuit that outputs the data input signal in synchronization with the clock signal is obtained.

In this embodiment, as in the first embodiment, the driving capability of the series circuit composed of two negative differential resistance elements is high. Even if a transistor having a gate width wider than the gate width of the field-effect transistor to be used is used, high-speed operation without amplitude attenuation can be performed.

(Third Embodiment) A circuit for outputting an inversion of a data input signal in synchronization with a clock signal A case where an inversion of a data input signal (a signal obtained by inverting a data input signal) is output in synchronization with a clock An embodiment of the present invention will be described. FIG. 6 illustrates an example of a circuit in this embodiment. The circuit shown in FIG. 6 is different from the first embodiment in that the area of the negative differential resistance element 1 is larger than that of the negative differential resistance element 1 with respect to the size of the emitter areas of the negative differential resistance element 1 and the negative differential resistance element 2. It is getting bigger. Further, by connecting a second field-effect transistor 4 in parallel with the negative differential resistance element 2 and applying a voltage to its gate electrode,
The peak current modulation of the negative differential resistance element 2 is enabled. The signal input method is a field effect transistor 4
Is connected to the data signal input terminal D, and the gate electrode of the field effect transistor 3 is connected to the clock signal input terminal CK.

In the circuit shown in FIG.
The behavior of the source potential Vs of the field-effect transistor 3 with respect to the voltage Vck applied to K is the same as in the first embodiment. Since the output is determined by the same principle as in the prior art, if the data signal applied to the data signal input terminal D when Vck changes from “High” to “Low”, the output is “High”. When the data signal is "Low", the output becomes "High". While Vck is "Low", the output does not change even if the data signal changes. That is, as shown in the timing diagram of FIG. 7, a circuit that outputs the inversion of the data input signal in synchronization with the clock signal is obtained.

In this embodiment, as in the case of the first embodiment, the circuit composed of two negative differential resistance elements has a high driving capability, and is used in this embodiment as an input circuit of the next stage. Even if a field effect transistor having a gate width wider than that of the field effect transistor is used, high-speed operation without amplitude attenuation can be performed.

(Fourth Embodiment) When a 1/2 Static Frequency Divider is Constructed by Combining the Circuits of the Present Invention A 1/2 static frequency divider for outputting a signal having a frequency 1/2 of the frequency of the input clock signal. An embodiment of the present invention in the case of configuring a frequency divider will be described. FIG. 8 illustrates an example of a circuit in this embodiment. The circuit shown in FIG. 8 uses the data input terminal and the output terminal of the circuit 7 (the circuit that outputs the data input signal in synchronization with the clock signal) shown in FIG. This circuit is connected to the output terminal and the data input terminal of a circuit that outputs a signal inversion in synchronization with a clock signal), and one of the circuits 7 and 8 is used as the entire output terminal Q. The clock signal CLK is input to the clock input terminal of the circuit 7, and the inverted clock signal CLK
(A signal obtained by inverting the clock signal).

In the circuit shown in FIG. 8, if X is "Low" or "High" and the output of circuit 7 (that is, the input of circuit 8) is X, when CLK becomes "Low",
The output of the circuit 8 (that is, the input of the circuit 7) is X. Next, when CLK becomes “Low”, the output of the circuit 7 (that is, the input of the circuit 8) becomes X. Thus, the input to the circuit 8 is inverted in one cycle of the clock. Therefore, the input of the circuit 8 returns to the original state in two cycles of the clock. That is, if the output terminal Q is provided at the connection point between the circuit 7 and the circuit 8, it can be seen that the circuit shown in FIG. 8 operates as a 1/2 frequency divider as shown in the timing diagram of FIG. In the output waveform shown in FIG. 9, the duty ratio (the interval between “High” and “Low” in one cycle) is not 50%.
No problem arises for some applications.

(Fifth Embodiment) Duty Ratio 50%
Of a 1/2 static frequency divider for obtaining an output of FIG. 1 shows an example of a circuit for obtaining an output with a duty ratio of 50%.
0 is shown. The basic configuration of the circuit is the same as that shown in FIG. 8, but outputs are taken from both output terminals of the circuits 7 and 8 and input to the OR circuit 9 to obtain an output Q from the OR circuit 9. The point is the difference.

The basic operation principle is the same as that of the circuit shown in FIG. Assuming that signals input from the circuits 7 and 8 to the OR circuit 9 are Q1 and Q2, respectively, as shown in the timing diagram of FIG. 11, the circuit shown in FIG.
It operates as a frequency divider, and it can be seen that the duty ratio of the output Q is 50%. It is apparent that the same effect can be obtained by using a NOR circuit instead of the OR circuit 9.

[0035]

As described above, the present invention provides a circuit for driving two serially connected negative differential resistance element circuits.
A constant current source is connected in series to the negative differential resistance element circuit, a driving transistor is connected in parallel, and a driving signal is input to a gate electrode (or a base electrode) of the negative differential resistance element circuit. In other words, a circuit that obtains an output by driving a negative differential resistance element circuit with a transistor having a small gate width can be easily realized with a small-scale circuit without deteriorating the advantages of the conventional technology. In addition, the effect of realizing low power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and is a circuit diagram for outputting an input signal as a signal having a larger driving capability.

FIG. 2 is a load curve diagram when a voltage Vr applied to a series circuit 6 of two negative differential resistance elements changes in the circuit of FIG.

FIG. 3 is an input / output waveform diagram of the circuit in FIG.

FIG. 4 is a diagram showing a second embodiment of the present invention, and is a circuit diagram for outputting a data input signal in synchronization with a clock.

FIG. 5 is a timing diagram for the circuit of FIG. 4;

FIG. 6 is a diagram showing a third embodiment of the present invention, and is a circuit diagram for outputting an inverted data input signal in synchronization with a clock.

FIG. 7 is a timing diagram of the circuit of FIG. 6;

FIG. 8 is a diagram showing a fourth embodiment of the present invention, and is a circuit diagram of a 1/2 static frequency divider formed by combining the circuits of the present invention.

FIG. 9 is a timing diagram of the circuit of FIG. 8;

FIG. 10 is a diagram showing a fifth embodiment of the present invention;
FIG. 4 is a circuit diagram of a 1/2 static frequency divider having a duty ratio of 50%.

FIG. 11 is a timing diagram of the circuit of FIG. 10;

FIG. 12 is a circuit diagram of an example of the related art.

FIG. 13 is a current-voltage characteristic diagram of a negative differential resistance element.

FIG. 14 is an operation characteristic diagram showing a stable point of a system in which two negative differential resistance elements are connected in series.

FIG. 15 is a current-voltage characteristic diagram of a composite element including a negative differential resistance element and a field-effect transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st negative differential resistance element 2 ... 2nd negative differential resistance element 3 ... 1st field-effect transistor 4 ... 2nd field-effect transistor 5 ... Constant current source 6 ... 2 negative differentials Series circuit of resistive elements 7 Circuit for outputting data input signal in synchronization with clock 8 Circuit for outputting inverted data input signal in synchronization with clock 9 OR circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 19/00

Claims (6)

(57) [Claims] A first transistor connected to both ends of a series circuit including a first negative differential resistance element and a second negative differential resistance element; A connection point between the differential resistance element and one power supply terminal of the first transistor is connected to a first potential, and a connection between the second negative differential resistance element and the other power supply terminal of the first transistor is provided. A point is connected to a second potential via a constant current source, a control terminal of the first transistor is used as a signal input terminal, and the first negative differential resistance element and the second negative differential resistance element are connected to each other. Semiconductor circuit with connection points as signal output terminals. 2. The semiconductor circuit according to claim 1, wherein an element capable of peak current modulation is used as at least one of said first negative differential resistance element and said second negative differential resistance element. A semiconductor circuit in which a current modulation terminal is a data input terminal, and a control terminal of the first transistor is a clock input terminal. 3. A semiconductor circuit according to claim 2, wherein said first negative differential resistance element is an element capable of modulating said peak current, and said second negative differential resistance element is A second circuit, which is an element capable of modulating the peak current,
A signal output terminal of the first circuit is connected to a peak current modulation terminal of the second circuit, and a signal output terminal of the second circuit is connected to a peak current modulation terminal of the first circuit. Connecting the control terminal of the first transistor of the first circuit as a clock input terminal, the control terminal of the first transistor of the second circuit as an inverted clock input terminal, A semiconductor circuit in which the signal output terminal of the second circuit is used as the signal output terminal of the entire circuit. 4. The semiconductor circuit according to claim 2, wherein said first circuit comprises said first negative differential resistance element as said element capable of modulating said peak current, and said second negative differential resistance element comprises: A second circuit, which is an element capable of modulating the peak current,
A signal output terminal of the first circuit is connected to a peak current modulation terminal of the second circuit, and a signal output terminal of the second circuit is connected to a peak current modulation terminal of the first circuit. Connecting the control terminal of the first transistor of the first circuit as a clock input terminal, the control terminal of the first transistor of the second circuit as an inverted clock input terminal, and the signal output of the first circuit. A semiconductor circuit in which a terminal and a signal output terminal of the second circuit are input to an OR circuit, and an output of the OR circuit is an output signal of the entire circuit. 5. The negative differential resistance element is a resonant tunneling diode or an Esaki diode, the transistor is a field effect transistor or a bipolar transistor, and the two power supply terminals are a source and a drain or an emitter and a collector. The control terminal is a gate or a base, the constant current source is connected to keep a constant potential between the gate and the source of the field effect transistor, and the drain is connected to the second negative differential resistance element and the second negative differential resistance element. 2. The semiconductor device according to claim 1, wherein the transistor is connected to a connection point of the first transistor with a power supply terminal, and a source is connected to the second potential. 3. 6. An element capable of modulating peak current, wherein a source and a drain of a field effect transistor are respectively connected to both ends of a negative differential resistance element, and a gate is a terminal for peak current modulation, or a negative differential resistance element is provided. An emitter and a collector of a bipolar transistor are connected to both ends of the element, respectively, and a base is used as a terminal for peak current modulation. The negative differential resistance element is a resonance tunnel diode or an Esaki diode. The semiconductor device according to claim 2.