JP3349948B2 - Analog / digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter for converting an input analog signal into a digital signal and supplying the digital signal to a digital processing unit for performing predetermined digital processing. The present invention can be applied to a receiver that performs demodulation and decoding processing.

[0002]

2. Description of the Related Art For example, in a communication system for transmitting data as a digital signal, a transmitting side performs processing such as encoding and modulation on the data as a digital signal, and then converts the data into an analog signal. Send. On the other hand, on the receiving side, after converting a received signal, which is an analog signal, into a digital signal (A / D conversion), demodulation and decoding are performed to reproduce transmission data.

When the analog signal (level and / or dynamic range) input to the A / D converter is too small at the time of A / D conversion on the receiving side, the converted digital signal becomes quantization noise. It is buried and degrades the error rate characteristics of the reproduced data. On the other hand, when the analog signal (level and / or dynamic range) input to the A / D conversion unit is too large, the range of the A / D conversion is limited, and the converted digital signal has an upper limit or a lower limit. The sticking to the value also occurs, and the sticking causes nonlinear distortion, which degrades the error rate characteristics of the reproduced data.

Therefore, in order to prevent the deterioration of the error rate characteristics of the reproduced data, it is necessary to perform gain control so as to keep the analog signal input to the A / D converter in an appropriate level range.

Conventionally, a general gain control method is as follows. The power of the digital signal after the A / D conversion is measured, and a certain value (a reference power level; hereinafter, simply referred to as a reference level) is subtracted from the measured power,
The gain of the variable gain amplifying unit provided before the A / D converter is automatically controlled so that the subtraction result becomes 0.
This reference level is selected so that the signal-to-noise ratio (S / N ratio) of the digital signal after A / D conversion is maximized.

Also, DC (direct current) added at the time of A / D conversion
The offset also degrades the error rate characteristics of the reproduced data.

In order to compensate for the DC offset, conventionally, generally, the DC signal of the digital signal after the A / D conversion is used.
A method of measuring the offset and subtracting the measured DC offset from the digital signal after A / D conversion has been adopted.

[0008]

As described above, conventionally, a gain control method for optimizing a level range of an analog signal input to an A / D converter and a DC offset of a digital signal after conversion have been proposed. Each compensation method is independently executed as an unrelated process. For example, conventionally, the reference level in the gain control method is constant regardless of the magnitude of the DC offset.

However, in the gain control method, the digital signal used for calculating the power has a DC offset compensated, and the probability that the digital signal sticks to the upper limit or the lower limit depends on the magnitude of the DC offset. And the two methods are not completely unrelated. In the related art, since the gain control method and the DC offset compensation method are independently executed as irrelevant processing, the degree of preventing the deterioration of the error rate characteristic of the reproduced data is always high even if both methods are applied. It was not something.

FIG. 2 is an explanatory diagram showing that the gain control method for optimizing the level range of an analog signal and the DC offset compensation method are interrelated. As described above, the probability that the digital signal sticks to the upper limit or the lower limit also depends on the magnitude of the DC offset. Therefore, the optimum reference level in the gain control method also depends on the magnitude of the DC offset. I do. FIG. 2 shows the relationship between the S / N ratio (SNR) of the digital signal after A / D conversion and the reference level (Refer Level) when the digital signal after A / D conversion is 5 bits, using a plurality of DC offsets. (0, 1, 2, 3, 4 and 5).

For example, when the DC offset is 0,
If the reference level is 28, the maximum S / N ratio is obtained,
It can be seen from FIG. 2 that this value 28 is the optimal reference level. For example, when the DC offset is 5,
If the reference level is 17, the maximum S / N ratio can be obtained,
It can be seen from FIG. 2 that this value 17 is the optimal reference level. That is, it can be seen that the optimum reference level is different for each DC offset.

For this reason, DC mixed at the time of A / D conversion
An analog / digital converter that can control the level of an analog signal to be used for A / D conversion in consideration of an offset is desired.

[0013]

In order to solve such a problem, a first analog / digital conversion device of the present invention comprises:
(1) variable gain means for amplifying an input analog signal with a gain specified by a gain control signal; (2) A / D conversion means for converting an analog signal amplified by the variable gain means into a digital signal; ) DC offset compensating means for measuring and removing a DC offset in the digital signal from the A / D converting means, (4) power measuring means for measuring the power of the digital signal from the A / D converting means, (5) gain control means for forming the gain control signal such that the power measured by the power measurement means maintains the reference level; and (6) the reference level based on the DC offset measured by the DC offset compensation means. And reference level control means for controlling

According to a second aspect of the present invention, there is provided an analog / digital conversion apparatus for converting each of M (M is an integer of 2 or more) input analog signals into a digital signal and outputting the digital signal. m is an m-th variable gain means for amplifying the input analog signal of 1 to M) with a gain indicated by the common gain control signal; and (2) converting the analog signal amplified by the m-th variable gain means into a digital signal. M-th
(3) an m-th DC offset compensator for measuring and removing a DC offset in a digital signal from the m-th A / D converter; and (4) the m-th A / D converter. M-th power measuring means for measuring the power of the digital signal from the D converting means; and (5) first to M-th power measuring means.
Gain control means for forming the common gain control signal such that the sum of the powers measured by the power measurement means maintains the reference level and applying the common gain control signal to the first to M-th variable gain means;
To a reference level control means for controlling the reference level based on the DC offset measured by the M-th DC offset compensation means.

Further, a third aspect of the present invention is an analog / digital converter for converting each of M (M is an integer of 2 or more) input analog signals into a digital signal and outputting the digital signal. m is an m-th variable gain means for amplifying the input analog signal of 1 to M) with a gain indicated by the m-th gain control signal; and (2) a digital signal obtained by amplifying the analog signal amplified by the m-th variable gain means. (3) m-th DC offset compensating means for measuring and removing a DC offset in a digital signal from the m-th A / D converting means; M-th power measuring means for measuring the power of the digital signal from the m-th A / D conversion means, and (5) the m-th power measuring means for maintaining the reference level of the power measured by the m-th power measuring means. Gain system And gain control means of the m giving to form a signal to the variable gain means of the m, (6) DC of the first m
M-th reference level control means for controlling a reference level given to the m-th gain control means based on the DC offset measured by the offset compensation means; and (7) DC output from the m-th DC offset compensation means. M-th gain correction means for correcting the gain of the digital signal from which the offset has been removed in accordance with a change in the reference level output from the m-th reference level control means to obtain an m-th output digital signal; And (8) the first to Mth gain correction means performs gain correction processing so that the total gain of the output digital signal with respect to the input analog signal is the same in all systems.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First Embodiment Hereinafter, a first embodiment of an analog / digital converter according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of the analog / digital converter according to the first embodiment.

In FIG. 1, an analog / digital converter according to a first embodiment includes an input terminal 1, a variable gain amplifier 2, an A / D converter 3, subtractors 4 and 9, output terminals 5, D
C offset measurement unit 6, filters 7 and 11, power measurement unit 8, reference level control unit 10, and D / A conversion unit 1
2 is comprised.

The variable gain amplifying unit 2 amplifies the analog signal input from the input terminal 1 with a gain indicated by the gain control signal output from the D / A converter 12 and outputs the amplified signal to the A / D converter 3. Is what you do.

The A / D converter 3 converts an input signal, which is an analog signal, into a digital signal and outputs the digital signal to the subtractor 4. For example, if the analog input signal is a digital modulation signal having a basically constant amplitude, such as a PSK modulation signal or an FSK modulation signal, the analog input signal is converted into a 5-bit digital signal.

The subtractor 4 subtracts a DC offset value (correction value of the DC offset) given from a filter 7 described later from the digital output signal from the A / D converter 3 and outputs the signal after the subtraction. These are output to the DC offset measurement unit 6, the power measurement unit 8, and the output terminal 5.

The DC offset measuring section 6 measures the DC offset mixed at the time of A / D conversion by the A / D conversion section 3. As long as the DC offset measuring section 6 can digitally detect the level of the DC component (DC offset) of the input signal, any existing internal configuration may be applied. Note that the input signal to the analog / digital conversion device is a PSK modulation signal or FSK modulation signal.
In the case of a modulated signal such as an SK modulated signal or an FM signal, the DC component of the signal is 0, so that the DC offset measuring unit 6 can easily measure the DC offset.

The filter 7 smoothes the DC offset output from the DC offset measuring section 6 to form a correction value of the DC offset, and supplies the corrected value to the subtracting section 4 as a subtraction input. Is to give. The filter 7 also defines a response time constant of a processing loop including the subtraction unit 4, the DC offset measurement unit 6, and the filter 7.

The reference level control unit 10 receives the input DC
The optimum reference level according to the offset correction value is output to the subtraction unit 9 as a subtracted input.

The power measuring section 8 measures the power of the output signal from the subtracting section 4 and outputs it to the subtracting section 9 as a subtraction input. For example, the sum of the squares of the sampling values in a predetermined period, the square root thereof, the sum of the absolute values of the sampling values, and the like are measured as the power.

The subtraction unit 9 subtracts the signal power measured by the power measurement unit 8 from the reference level output from the reference level control unit 10 and gives the signal power to the filter 11.

The filter 11 smoothes the output signal from the subtractor 9 and outputs the smoothed signal to the D / A converter 12.
The filter 11 includes a variable gain amplifier 2, an A / D converter 3, a subtractor 4, a power measuring unit 8, a subtractor 9, and a filter 1.
1 and a response time constant of a processing loop including the D / A converter 12.

The D / A converter 12 converts an input signal, which is a digital signal, into an analog signal and supplies the analog signal to the variable gain amplifier 2 as a gain control signal.

Next, the overall operation of the analog / digital converter of the first embodiment will be described.

In FIG. 1, an analog signal input from an input terminal 1 is amplified by a variable gain amplifier 2 and input to an A / D converter 3, where it is converted into a digital signal. A subtraction unit 4 subtracts the DC offset correction value from the converted digital signal, and performs DC offset compensation.

The digital output signal from the subtraction unit 4 is supplied to a processing circuit (not shown) at the next stage via an output terminal 5, where a predetermined process (for example, demodulation or decoding of a digital modulation signal) is performed. Is done.

The digital output signal from the subtraction unit 4 is also supplied to a DC offset measurement unit 6, where the DC offset generated by the A / D conversion is measured, and the measured DC offset is measured. The DC offset is smoothed by the filter 7 and given as a DC offset value to the subtraction unit 4 as a subtraction input. That is, the subtraction unit 4, the DC offset measurement unit 6, and the filter 7
The DC offset component in the digital signal after A / D conversion is removed by the processing of the processing loop.

The output signal of the filter 7 (correction value of the DC offset) is also supplied to the reference level control unit 10, whereby the reference level control unit 10 outputs the optimum reference level corresponding to the correction value of the DC offset. Is supplied to the subtraction unit 9 as a subtracted input.

The digital output signal from the subtraction unit 4 that has been subjected to the DC offset compensation is also supplied to a power measurement unit 8, the signal power of which is measured by the power measurement unit 8, and supplied to a subtraction unit 9 as a subtraction input. Can be As a result, a difference signal of the measured power level from the reference level is output from the subtraction unit 9, the difference signal is smoothed by the filter 11, and then converted to an analog signal by the D / A conversion unit 12. It is provided to the variable gain amplifier 2 as a gain control signal.

That is, the variable gain amplifying unit 2, the A / D converting unit 3, the subtracting unit 4, the power measuring unit 8, the subtracting unit 9, the filter 1
By the processing of the processing loop consisting of 1 and the D / A converter 12, the difference between the reference level output from the reference level controller 10 at that time and the measured power of the digital signal after conversion becomes zero. , The gain of the variable gain amplifier 2 is controlled. As a result, it is possible to prevent the analog input signal to the A / D converter 3 from being excessively small or excessively large. In addition, the reference level serving as a reference for such an operation is optimal according to the DC offset.

Next, the internal configuration and operation of the reference level control unit 10 will be described in detail. As described above, the optimum reference level depends on the magnitude of the DC offset. Also,
As described above, the reference level control unit 10 forms an optimum reference level according to the magnitude of the DC offset, and outputs the optimum reference level to the subtraction unit 9.

For example, when there is a relationship as shown in FIG. 3 between the magnitude of the DC offset and the optimum reference level, the reference level control unit 10 stores the optimum reference level as shown in FIG. It can be composed of a ROM.
In this case, if the value of the DC offset in FIG. 3 is used as an address for specifying the storage area of the ROM, and the output signal from the filter 8 is used as the address input of the ROM, the optimum reference level corresponding to the magnitude of the DC offset is subtracted. It can be supplied to the unit 9. As described above, FIG. 3 can be considered to represent the detailed configuration of the reference level control unit 10, and can also be considered to represent an example of the relationship between the DC offset value and the optimal reference level. .

As described above, according to the first embodiment,
Since the reference level for defining the target power of the digital signal can be adjusted to an optimum level in accordance with the magnitude of the measured DC offset, the level of the analog input signal to the A / D converter can be optimized. A / D-converted digital signal can be output with high accuracy.

As a result, the accuracy of the processing circuit for processing the digital signal from the analog / digital converter can be improved. For example, if digital demodulation processing or decoding processing is performed on a digital signal, the error rate characteristics of the reproduced data can be improved as compared with the related art.

(B) Second Embodiment Next, a second embodiment of the analog / digital converter according to the present invention will be described in detail with reference to the drawings.

The analog-to-digital converter of the second embodiment also has the overall configuration shown in FIG. 1 according to the first embodiment.
The detailed configuration of the reference level control unit 10 is different from that of the first embodiment. Therefore, hereinafter, a detailed configuration and operation of the reference level control unit 10 will be described.

FIG. 4 is a block diagram showing a detailed configuration of the reference level control unit 10 according to the second embodiment.

In FIG. 4, the reference level control unit 10 of the second embodiment includes an input terminal 21, a constant storage unit (linear coefficient storage unit) 22, a constant storage unit (constant term storage unit) 23, a multiplication unit 24, It comprises an adder 25 and an output terminal 26, and is a linear operation unit. The input terminal 21 is
The output terminal 26 is connected to the output terminal of the filter 7 (see FIG. 1), and the output terminal 26 is connected to the subtracted input terminal of the subtraction unit 9 (see FIG. 1).

In FIG. 4, the DC offset (correction value) from the filter 7 input through the input terminal 21 includes a constant (linear coefficient) stored in the constant storage unit 22 in the multiplication unit 24. A constant (constant term) stored in the constant storage unit 23 is added to the multiplied and obtained multiplication output in the addition unit 25, and the obtained addition output is output to the subtraction unit 9 (FIG. 1) is given as the subtracted input (optimal reference level).

The reference level control unit 1 of the second embodiment
0 is a configuration when there is a linear relationship (linear function) between the magnitude of the DC offset and the optimal reference level. The relationship between the magnitude of the DC offset and the optimum reference level shown in FIG. 3 described above corresponds to this case. That is, if the optimum reference level is set to R and the magnitude of the DC offset is set to D, the relationship between the magnitude of the DC offset and the optimum reference level shown in FIG. 3 can be expressed by the following equation (1). it can.

R = a · D + b = −2 · D + 28 (1) Therefore, in this example, “−2” is stored in the constant storage unit (linear coefficient storage unit) 22 and the constant storage unit (constant term storage) Part) 2
If “28” is stored in 3, the optimum reference level R according to the magnitude D of the DC offset can be obtained and output.

Although FIG. 4 shows the case where the constant storage unit 22 and the multiplication unit 24 perform the operation of a · D in the equation (1), this component can multiply a constant value. If so, another configuration may be used. For example, if the linear coefficient a is a power of 2, the multiplication component may be formed by a shifter. Further, the adding unit 25 may perform subtraction.

As apparent from FIG. 2, the relationship between the magnitude of the DC offset and the optimum reference level can be approximated by a linear function (linear relationship) in practice. The detailed configuration of the reference level control unit 10 can be adopted. In addition, approximation may be made by a quadratic function. In this case, a plurality of arithmetic elements and constant storage units may be arranged in accordance with the approximation.

According to the second embodiment, the reference level defining the target power of the digital signal is obtained by measuring the measured D level.
The level of the analog input signal to the A / D conversion unit can be optimized because it can be adjusted to an optimum value according to the magnitude of the C offset, and the device outputs the A / D converted digital signal with high accuracy. be able to.

According to the second embodiment, the circuit scale of the reference level control unit 10 can be reduced. It is considered that the analog / digital converter is likely to be mounted together with other circuits on one chip. However, when a ROM is formed on a chip, the circuit scale of that portion generally increases, Pressure on the occupied area of the element. In the case of the second embodiment, since no ROM is applied, it is considered that such an inconvenience can be avoided.

(C) Third Embodiment Next, a third embodiment of the analog / digital converter according to the present invention will be described in detail with reference to the drawings.

The analog / digital converter of the third embodiment converts two related analog input signals into digital signals. For example, in digital modulation schemes such as the PSK modulation scheme and the FSK modulation scheme, when downconverting to an intermediate frequency band (IF band) or a baseband frequency band on the receiver side, signals of the in-phase component and the quadrature component are usually converted. Often, these in-phase and quadrature-component signals are separately A / D converted and demodulated, and the analog / digital converter of the third embodiment can be applied to such digital signal receivers. Things.

FIG. 5 is a block diagram showing the overall configuration of the analog / digital conversion apparatus according to the third embodiment. The same parts as those in FIG. The corresponding reference numerals are attached.

In FIG. 5, the analog-to-digital converter according to the third embodiment has an input terminal 1I, a configuration relating to a first system (here, a processing system for in-phase components).
A variable gain amplifier 2I, an A / D converter 3I, a subtractor 4I,
Output terminal 5I, DC offset measuring unit 6I, filter 7
And an input terminal 1Q, a variable gain amplifier 2Q, an A / D converter 3Q, a subtractor, as a configuration related to a second system (here, a quadrature component processing system). 4Q, output terminal 5Q, DC offset measuring unit 6Q,
A filter 7Q and a power measuring unit 8Q are provided.
As a configuration common to these systems, a subtraction unit 9, a reference level control unit 10, a filter 11, and a D / A conversion unit 12 are provided.

The input terminal 1 which is a component specific to each system
I, variable gain amplifier 2I, A / D converter 3I, subtractor 4
I, output terminal 5I, DC offset measurement unit 6I, filter 7I, power measurement unit 8I, input terminal 1Q, variable gain amplification unit 2Q, A / D conversion unit 3Q, subtraction unit 4Q, output terminal 5
The functions of the Q, DC offset measuring unit 6Q, filter 7Q, and power measuring unit 8Q are the same as those of the corresponding elements of the first embodiment, and thus description thereof will be omitted.

On the other hand, the functions of the subtraction unit 9, reference level control unit 10, filter 11, and D / A conversion unit 12, which are common to both systems, are basically the same as those of the corresponding elements of the first embodiment. However, when viewed in detail, it is slightly different.

The reference level control unit 10 of the third embodiment is provided with DC offset correction values from the filters 7I and 7Q of both systems, and the reference level control unit 10 corrects the DC offset correction values of these two systems. And a reference level is provided to the subtractor 9 as an input to be subtracted.

The subtraction unit 9 of the third embodiment subtracts the measured powers output from the two power measuring units 8I and 8Q from the reference level from the reference level control unit 10, respectively. To give.

The filter 11 smoothes the output signal from the subtraction unit 9 and supplies the output signal to the D / A conversion unit 12.

The D / A converter 12 according to the third embodiment converts the output signal (digital signal) from the subtractor 9 into an analog signal, and applies gain to the two variable gain amplifiers 2I and 2Q. This is given as a control signal.

Next, the overall operation of the analog / digital converter of the third embodiment will be described.

In FIG. 5, an analog signal related to the in-phase component input from the input terminal 1I is supplied to a variable gain amplifier 2I.
And is input to the A / D conversion unit 3I, where it is converted into a digital signal. A subtraction unit 4I subtracts the DC offset correction value from the converted digital signal, and performs DC offset compensation for the first system.

The digital output signal from the subtractor 4I is
The signal is supplied to a processing circuit (not shown) at the next stage via the output terminal 5I, and is subjected to predetermined processing (for example, demodulation and decoding of a digital modulation signal).

The digital output signal from the subtraction unit 4I is also supplied to a DC offset measurement unit 6I.
In the C offset measuring unit 6I, the A / D of the first system
The DC offset generated by the conversion is measured, and the measured DC offset is smoothed by the filter 7I and is provided as a DC offset value to the subtraction unit 4I as a subtraction input. That is, the DC offset component in the digital signal after the A / D conversion for the first system is removed by the processing of the processing loop including the subtraction unit 4I, the DC offset measurement unit 6I, and the filter 7I.

On the other hand, the analog signal relating to the quadrature component input from the input terminal 1Q is amplified by the variable gain amplifier 2Q, input to the A / D converter 3Q, and converted into a digital signal. The subtraction unit 4Q subtracts the DC offset correction value from the converted digital signal, and performs DC offset compensation for the second system.

The digital output signal from the subtractor 4Q is
The signal is supplied to the next processing circuit (not shown) via the output terminal 5Q, and is subjected to predetermined processing (for example, demodulation and decoding of a digital modulation signal).

The digital output signal from the subtraction section 4Q is also supplied to a DC offset measurement section 6Q.
In the C offset measuring unit 6Q, the A / D of the second system
The DC offset generated by the conversion is measured, and the measured DC offset is smoothed by the filter 7Q, and given as a DC offset value to the subtraction unit 4Q as a subtraction input. That is, the DC offset component of the digital signal after the A / D conversion for the second system is removed by the processing of the processing loop including the subtraction unit 4Q, the DC offset measurement unit 6Q, and the filter 7Q.

The output signal (correction value of the DC offset) of the filter 7I is also supplied to the reference level control unit 10. The output signal (correction value of the DC offset) of the filter 7Q is also supplied to the reference level control unit 10. Thus, the reference level control unit 10 supplies the subtraction unit 9 with the optimum reference level corresponding to the two DC offset correction values as a subtracted input.

The digital output signal from the subtraction unit 4I that has been subjected to the DC offset compensation for the first system is
The signal power is also supplied to the power measuring unit 8I, the signal power is measured by the power measuring unit 8I, and the signal power is supplied to the subtracting unit 9 as a subtraction input. Similarly, the digital output signal from the subtraction unit 4Q, for which the DC offset has been compensated for the second system, is also supplied to the power measurement unit 8Q, and the power measurement unit 8Q
And the signal power is measured and supplied to the subtraction unit 9 as a subtraction input.

As a result, the subtraction unit 9 outputs a difference signal obtained by subtracting the sum of the two measured power levels from the reference level, and after the difference signal is smoothed by the filter 11, the D / A conversion is performed. The signal is converted into an analog signal by the unit 12 and supplied to the variable gain amplifying units 2I and 2Q as a gain control signal.

That is, the processing of the processing loop composed of the variable gain amplifying section 2I, the A / D converting section 3I, the subtracting section 4I, the power measuring section 8I, the subtracting section 9, the filter 11 and the D / A converting section 12, Amplifying unit 2Q, A / D converting unit 3Q, subtracting unit 4Q, power measuring unit 8Q, subtracting unit 9, filter 11 and D
The difference between the reference level output from the reference level control unit 10 at that time and the sum of the measured powers of the two types of digital signals after conversion is reduced to 0 by the processing of the processing loop including the / A conversion unit 12. So that the variable gain amplifiers 2I and 2I
The gain of Q is controlled. As a result, it is possible to prevent the analog input signals to the A / D converters 3I and 3Q from being excessively small or excessively large. In addition, the reference level serving as a reference for such an operation is optimal according to the DC offset.

Next, the internal configuration and operation of the reference level control unit 10 according to the third embodiment will be described in detail. As described above, the optimum reference level depends on the magnitude of the DC offset. In this case, both two types of DC offset are considered. Further, as described above, the reference level control unit 10 forms an optimum reference level according to the magnitudes of the two types of DC offsets and outputs the optimum reference level to the subtraction unit 9.

For example, two types of DC offset magnitudes (DC offset correction values) and an optimal reference level are:
When there is a relationship as shown in FIG. 6, the reference level control unit 10 can be constituted by a ROM storing the optimum reference level as shown in FIG. As shown in FIG. 6, the DC offset correction value of the in-phase component and the DC offset correction value of the quadrature component
Since the offset correction values are independent of each other, all combinations of the DC offset correction values of the in-phase component and the quadrature component must be considered.

In the case of a ROM, if the address for specifying the storage area of the ROM is a combination such that the DC offset correction value of the in-phase component is on the upper side and the DC offset correction value of the quadrature component is on the lower side, 2 Kinds of DC
An optimum reference level according to the offset correction value can be supplied to the subtraction unit 9.

As described above, according to the third embodiment,
For example, two signals such as in-phase and quadrature components are A / D
In performing the conversion, the reference level that defines the target power of the digital signal can be adjusted to an optimum level according to the magnitude of the measured DC offset, so that the level of the analog input signal to the A / D converter is optimized. It is possible to output two digital signals that have been A / D converted with high precision from the device. As a result, the accuracy of the processing circuit that processes the digital signal from the analog / digital converter can be improved. For example, if digital demodulation processing and decoding processing are performed on two systems of digital signals, the error rate characteristics of the reproduced data can be improved as compared with the related art.

According to the third embodiment, D /
The output signal of the A converter 12 is divided into two variable gain amplifiers 2
Since the variable gain amplifiers 2I and 2Q amplify with the same gain as a common gain control signal for I and 2Q, the apparatus outputs two systems of digital signals with balanced levels. be able to. As a result, also in this aspect, it is possible to improve the accuracy of the processing circuit that processes the two digital signals from the analog / digital converter. For example, 2
If digital demodulation processing and decoding processing are performed on digital signals of the system (in-phase component and quadrature component),
It is preferable that the composite point of the two digital signals is located on the circumference on the IQ plane, and this can be satisfied if the levels of the two digital signals are balanced.

(D) Fourth Embodiment Next, a fourth embodiment of the analog / digital converter according to the present invention will be described in detail with reference to the drawings.

The analog-to-digital converter of the fourth embodiment also has the overall configuration shown in FIG. 5 according to the third embodiment.
The detailed configuration of the reference level control unit 10 is different from that of the third embodiment. Therefore, hereinafter, a detailed configuration and operation of the reference level control unit 10 will be described.

FIG. 7 is a block diagram showing a detailed configuration of the reference level control unit 10 according to the fourth embodiment.

In FIG. 7, the reference level controller 10 of the fourth embodiment has two input terminals 31I and 31Q,
Adders 32 and 36, a constant storage (linear coefficient storage) 33, a constant storage (constant term storage) 34, and a multiplier 3
5 and an output terminal 37. The input terminal 31I is connected to the output terminal of the filter 7I (see FIG. 5), and the input terminal 31Q is connected to the filter 7I.
The output terminal 37 is connected to the output terminal of Q (see FIG. 5), and the output terminal 37 is connected to the subtracted input terminal of the subtraction unit 9 (see FIG. 5).

In FIG. 7, the DC offset (correction value) from the filter 7I inputted through the input terminal 31I and the filter 7 inputted through the input terminal 31Q are used.
The DC offset from Q (correction value of the DC offset)
The obtained addition value is multiplied by a constant (linear coefficient) stored in a constant storage unit 33 in a multiplication unit 35, and the obtained multiplication output is added to a constant storage in an addition unit 36. The constants (constant terms) stored in the unit 34 are added, and the obtained addition output is given as an input to be subtracted (optimal reference level) of the subtraction unit 9 (see FIG. 5) via the output terminal 37.

The reference level control section 1 of the fourth embodiment
0 is a configuration in which it can be approximated that there is a linear relationship (linear function) between the sum of the two types of DC offset correction values and the optimum reference level.

The relationship between the magnitudes of the two types of DC offset and the optimum reference level shown in FIG. 6 corresponds to the case where this approximation holds. That is, if the optimal reference level is R, the DC offset correction value of the in-phase component is Di, and the DC offset correction value of the quadrature component is Dq, the magnitude of the two types of DC offset shown in FIG. In the relation, the approximate expression shown in Expression (2) is established.

Rc · (Di + Dq) + d = −2 · (Di + Dq) +56 (2) Therefore, in this example, “−2” is stored in the constant storage unit (linear coefficient storage unit) 33, and the constant storage unit (Constant term storage unit) 3
If “56” is stored in 4, the optimum reference level R corresponding to the two types of DC offset magnitudes Di and Dq can be obtained and output.

Although FIG. 7 shows the case where the constant storage unit 33 and the multiplication unit 35 perform the operation of c · (Di + Dq) in the equation (2), this component can multiply a constant value. Other configurations may be used. For example, if the linear coefficient a is a power of 2, the multiplication component may be formed by a shifter. Further, the adding unit 36 may perform a subtraction.

The approximation function may be approximated by a quadratic function or a linear function using the magnitudes of the DC offsets Di and Dq as variables. In this case, a plurality of arithmetic elements and constant storage corresponding to the functions may be used. Parts may be arranged.

According to the fourth embodiment, the same effect as that of the third embodiment can be obtained.

According to the fourth embodiment, the circuit scale of the reference level control unit 10 can be reduced. It is considered that the analog / digital converter is likely to be mounted together with other circuits on one chip. However, when a ROM is formed on a chip, the circuit scale of that portion generally increases, Pressure on the occupied area of the element. In the case of the fourth embodiment, since no ROM is applied, it is considered that such an inconvenience can be avoided.

(E) Fifth Embodiment Next, a fifth embodiment of the analog / digital converter according to the present invention will be described in detail with reference to the drawings.

The analog / digital converter according to the fifth embodiment converts the related two analog input signals into digital signals, similarly to the third and fourth embodiments.

FIG. 8 is a block diagram showing the overall configuration of an analog / digital conversion apparatus according to the fifth embodiment. Parts corresponding to those in FIG. 1 according to the first embodiment are denoted by corresponding reference numerals. Is shown.

The above-described third and fourth analog-to-digital converters for converting two related analog input signals into digital signals, respectively.
In the embodiment, the subtraction unit 9, the reference level control unit 10, the filter 11, and the D / A conversion unit 12 which are common to the two systems are provided.

However, in the case of the fifth embodiment,
These components are also provided for each system. That is, the first system includes the subtraction unit 9I and the reference level control unit 1
0I, a filter 11I, and a D / A conversion unit 12I. The second system includes a subtraction unit 9Q, a reference level control unit 10Q, a filter 11Q, and a D / A conversion unit 1
2Q is provided.

Therefore, in the case of the fifth embodiment, the first
A / D conversion configuration of the system (processing system for in-phase components)
Is independent of the A / D conversion configuration of the system (processing system of the in-phase component), and is not configured to transmit and receive signals. The configuration of each system is the configuration of the first embodiment. It is almost the same.

The configuration of each system is different from that of the first embodiment in that the subtractors 4I and 4Q output the output terminals 5I and 5Q.
In that the gain correction units 13I and 13Q are provided on the path to. The other components are the same as those of the first embodiment, and the description of the functions will be omitted.

Each of the gain correction units 13I and 13Q is provided with a correction value of the DC offset output from the corresponding filter 7I or 7Q. Each of the gain correction units 13I and 13Q multiplies the corresponding digital signal output from the subtraction unit 4I or 4Q by a gain correction value determined by the correction value of the DC offset output from the corresponding filter 7I or 7Q. Output terminals 5I and 5Q.

The gain correction units 13I and 13Q are provided with the output digital signal of the first system (in-phase component) and the second system.
This is provided to make the weights of the output digital signals (of the orthogonal components) of the two systems equal, in other words, to improve the level balance of the digital signals of both the systems.

In the case of the third and fourth embodiments described above,
Since the gains of the two systems of variable gain amplifiers 2I and 2Q are controlled by the same gain control signal, it can be expected that the level balance of the digital signals of both systems is improved. However, since the DC offset correction value used to form the signal is formed by two independent loops, the accuracy of the gain control signal itself may be poor. That is, when the correspondence between two corresponding components is high such that the two components are formed on the same semiconductor chip, the third and fourth embodiments are very useful. In the case where the compensation of the DC offset compensation system of two systems is poor, the accuracy of the common gain control signal may be low.

In such a case, it is preferable not to provide a common configuration in the two-system configuration as in the fifth embodiment. However, in this case, the level balance between the two digital signals from the analog / digital converter may not be good. Therefore, gain correction units 13I and 13Q are provided in each system to improve the level balance of the digital signals of the two systems.

Here, the gain correction units 13I, 13
Since Q does not transmit or receive a signal between the two systems, it is corrected so that a digital signal having a reference gain is output.

As described above, each gain correction unit 13I, 1
3Q multiplies a correction gain that makes the weights of the in-phase component and the quadrature component the same. For example, if the reference level of the in-phase component is Ri, the reference level of the quadrature component is Rq, the correction gain of the in-phase component is Gi, and the correction gain of the quadrature component is Gq,
The gain is corrected by obtaining a correction gain that satisfies the relationship of equation (3). Expression (3) is based on the reference levels Ri and Rq.
However, as described in the first embodiment, in general, the reference levels Ri and Rq and D
Since there is a linear relationship with the C offset (correction value thereof), D
The correction gains Gi and Gq can be easily determined from the C offset.

Ri × Gi ² = Rq × Gq ² (3) Equation (3) has the following qualitative meaning. The gain of the digital output signal from the analog / digital conversion device, as viewed from the analog input signal to the device, is obtained by multiplying the gain of the variable gain amplification units 2I and 2Q by the gain of the gain correction units 13I and 13Q. Conceivable. The indirectly determining the gain in the variable gain amplifying sections 2I and 2Q includes a reference level from the reference level control sections 10I and 10Q. Since this is the target value of the measured power, the order is , The square of the signal gain.
In order to make the weights of the in-phase component and the quadrature component in the digital output signal from the device the same, the gain parameters of the variable gain amplifying units 2I and 2Q and the gain correction unit 1
It suffices if the product of the gain parameter at 3I and 13Q (the order of both parameters must be the same) is the same. That is, if equation (3) can be satisfied,
The weights of the in-phase component and the quadrature component in the digital output signal from the device can be made the same.

FIG. 9 shows a case where the DC offset (correction value thereof) and the reference level have the relationship shown in FIG. 3 described above and the correction gain determination equation is equation (3).
9 shows a relationship between (correction value of) DC offset and correction gain. Note that sqrt (X) in FIG.
Represents the square root of. For example, the relationship shown in FIG.
Each gain correction unit 13I, 13
When a DC offset (correction value) is given to each of the Qs, a correction gain is extracted from a table, and the correction gain is multiplied by the output signals (digital signals) from the subtractors 4I and 4Q to correct the gain. .

According to the fifth embodiment, the same effects as those of the third and fourth embodiments can be obtained.

Furthermore, according to the fifth embodiment, the provision of the gain correction section enables the independent setting of the optimum reference level for the in-phase component and the quadrature component, and the gain control in the analog stage. It is possible to improve the accuracy of the device.

(F) Sixth Embodiment Next, a sixth embodiment of the analog / digital converter according to the present invention will be briefly described.

FIG. 10 is a block diagram showing the overall configuration of an analog / digital conversion apparatus according to the sixth embodiment. The same parts as those in FIG. , Corresponding symbols are attached.

The analog / digital converter of the sixth embodiment is based on the same technical concept as the fifth embodiment, and the difference is apparent from the comparison between FIG. 10 and FIG. As described above, the signals input to the gain correction units 13I and 13Q to determine the correction gain are not the DC offsets (correction values thereof) but the reference levels output from the corresponding reference level control units 10I and 10Q. It is a point.

Therefore, in the case of the sixth embodiment, the correction gain can be determined from the relationship itself of the above equation (3).

FIG. 11 shows a detailed configuration example of the gain correction unit 13 (13I or 13Q; hereinafter, the configuration of FIG. 11 will be described as 13I) in the sixth embodiment. This corresponds to the case where the specific value (constant) of the right side and the left side in Expression 3) is “1”.

In FIG. 11, the gain corrector 13 includes two input terminals 41 and 42, a square root calculator 43, a reciprocal calculator 44, a multiplier 45, and an output terminal 46. First
Is connected to the output terminal of the reference level controller 10I, and the second input terminal 42 is connected to the subtractor 4I.
The output terminal 46 is connected to the output terminal 5I of the entire analog / digital converter.

The square root of the reference level input from the input terminal 41 is obtained in the square root calculator 43, and the reciprocal thereof is obtained in the reciprocal calculator 44, and is input to the multiplier 45 as a correction gain. The output signal from the subtraction unit 4I is also input to the multiplication unit 45 via the second input terminal 42. The multiplication unit 45 multiplies this output signal by a correction gain and changes the gain to another system. Is corrected so that the level and the balance can be obtained, and output from the output terminal 46.

Also in the sixth embodiment, the basic technical concept is the same as that of the fifth embodiment, so that the same effects as those of the fifth embodiment can be obtained.

In addition to this, according to the sixth embodiment,
The gain correction units 13I and 13Q can be configured without using a ROM table, and as a result, a reduction in the size of the device can be expected.

(G) Seventh Embodiment Next, a seventh embodiment of the analog / digital converter according to the present invention will be briefly described.

FIG. 12 is a block diagram showing the overall configuration of the analog / digital converter of the seventh embodiment. The same components as those in FIG. , Corresponding symbols are attached.

The analog / digital converter of the seventh embodiment is based on the same technical concept as that of the sixth embodiment, and the difference is apparent from a comparison between FIGS. 12 and 10. As described above, the signals input to the gain correction units 13I and 13Q for determining the correction gain are not the reference levels output from the reference level control units 10I and 10Q of the own system, but the reference level control units 10Q and 10Q of the other system. 1
The point is that the reference level is output from 0I.

By transforming the above equation (3), the following equation (4) is obtained. If the values on the right and left sides in the equation (4) are set to a constant A (the weights of both systems are the same, they may be treated as constants), and further, the equation (5) is obtained. As is apparent from the equation (5), it is understood that the correction gain is determined from the reference level output from the reference level control unit 10 of another system.

Gi ² / Rq = Gq ² / Ri (4) Gi ² = A · Rq Gq ² = A · Ri (5) FIG. 13 shows the gain correction unit 13 (1) in the seventh embodiment.
3I or 13Q; hereinafter, the configuration of FIG. 13 will be described as 13I), which corresponds to the case where the constant A in the above-described equation (5) is “1”. .

In FIG. 13, the gain corrector 13 has two input terminals 51 and 52, a square root calculator 53, a multiplier 5
4 and an output terminal 55. First input terminal 51
Is connected to the output terminal of the reference level control unit 10Q of another system, the second input terminal 52 is connected to the output terminal of the subtraction unit 4I, and the output terminal 55 is connected to the analog / digital converter. It is connected to the entire output terminal 5I.

The square root of the reference level of the other system input from the first input terminal 51 is obtained in the square root calculator 52 and is input to the multiplier 54 as a correction gain. The multiplication unit 54 is connected to the subtraction unit 4 via the second input terminal 52.
The output signal from I is also input, and the multiplication section 54 multiplies the output signal by a correction gain, corrects the gain so as to be balanced with the level of another system, and outputs the output signal from the output terminal 55.

Also in the seventh embodiment, the basic technical concept is the same as that of the sixth embodiment, so that the same effects as those of the sixth embodiment can be obtained. In addition, according to the seventh embodiment, the gain correction units 13I and 13Q can be simplified because the reciprocal operation unit is not required.

(H) Other Embodiments The analog / digital converter of the present invention is intended to be mounted on a digital signal receiver. Of course, the invention may be applied.

In the third to sixth embodiments, 2
Although the case where A / D conversion is performed on system signals has been described, the present invention can also be applied to a device that performs A / D conversion on three or more types of signals. Note that the technical concept of providing the gain correction unit is also applicable to a device that performs A / D conversion of one type of signal.

Further, in the above description, the device configuration has been described as being realized by a hardware configuration.
A part may be realized by a software configuration using a DSP or a CPU.

[0126]

As described above, according to the present invention, the reference level as the target power for varying the gain of the analog signal before conversion is varied in accordance with the DC offset. Thus, a digital signal that has been A / D converted with high accuracy can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a first embodiment.

FIG. 2 is a characteristic curve diagram for explaining a conventional problem.

FIG. 3 is an explanatory diagram of a configuration of a reference level control unit according to the first embodiment.

FIG. 4 is a block diagram illustrating a detailed configuration of a reference level control unit according to a second embodiment.

FIG. 5 is a block diagram illustrating an overall configuration of a third embodiment.

FIG. 6 is an explanatory diagram illustrating a configuration of a reference level control unit according to a third embodiment.

FIG. 7 is a block diagram illustrating a detailed configuration of a reference level control unit according to a fourth embodiment.

FIG. 8 is a block diagram showing an overall configuration of a fifth embodiment.

FIG. 9 is an explanatory diagram illustrating a relationship between a DC offset and a correction gain according to the fifth embodiment.

FIG. 10 is a block diagram showing an overall configuration of a sixth embodiment.

FIG. 11 is a block diagram illustrating a detailed configuration example of a gain correction unit according to a sixth embodiment.

FIG. 12 is a block diagram illustrating an overall configuration of a seventh embodiment.

FIG. 13 is a block diagram illustrating a detailed configuration example of a gain correction unit according to a seventh embodiment.

[Explanation of symbols]

 2, 2I, 2Q: Variable gain amplifier, 3, 3I, 3Q: A / D converter, 4, 4I, 4Q, 9: Subtractor, 6, 6I, 6Q: DC offset measuring unit, 7, 7I, 7Q , 11: filter, 8, 8I, 8Q: power measurement section, 10, 10I, 10Q: reference level control section, 12, 12I, 12Q: D / A conversion section, 13I, 13Q: gain correction section, 22, 23, 33, 34 ... constant storage unit, 24, 35, 45, 54 ... multiplication unit, 25, 32, 36 ... addition unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/18 H04L 27 / 22,27 / 14

Claims (10)

(57) [Claims] A variable gain means for amplifying an input analog signal with a gain designated by a gain control signal; A / D conversion means for converting an analog signal amplified by the variable gain means into a digital signal; DC offset compensating means for measuring and removing a DC offset in the digital signal from the D converting means, power measuring means for measuring the power of the digital signal from the A / D converting means, and measuring by the power measuring means. Gain control means for forming the gain control signal so that power maintains a reference level; and reference level control means for controlling the reference level based on the DC offset measured by the DC offset compensation means. Analog / digital converter. 2. The analog / digital converter according to claim 1, wherein said reference level control means is a memory table for outputting a reference level stored in a memory area having an input DC offset as an address. Digital conversion device. 3. The reference level control means according to claim 2, further comprising: a multiplying unit for multiplying the input DC offset by a predetermined constant; and an adding unit for adding a predetermined constant to the multiplied output. 2. The analog / digital conversion device according to 1. 4. An analog / digital converter for converting each of M (M is an integer of 2 or more) input analog signals into a digital signal and outputting the digital signal, wherein an m-th (m is 1 to M) input analog signal Variable gain means for amplifying the analog signal amplified by the common gain control signal, m-th A / D conversion means for converting an analog signal amplified by the m-th variable gain means into a digital signal, An m-th DC offset compensator for measuring and removing a DC offset in a digital signal from the A / D converter, and an m-th DC offset compensator for measuring power of the digital signal from the m-th A / D converter. Power measuring means, and forming the common gain control signal such that the sum of the powers measured by the first to Mth power measuring means maintains a reference level, and forming the common gain control signal in the first to Mth variable gain means. And gain control means for obtaining, based on the first to DC offset DC offset compensation means of the M was measured, the analog / digital conversion device characterized by comprising a reference level control means for controlling the reference level. 5. The reference level control means is a memory table for outputting a reference level stored in a memory area whose address is data in which input M DC offsets are arranged at predetermined positions. The analog / digital converter according to claim 4, wherein 6. The reference level control means includes: a sum calculation unit for calculating a sum of the input M DC offsets; a multiplication unit for multiplying the sum by a predetermined constant; and a predetermined constant for the multiplied output. The analog-to-digital converter according to claim 4, further comprising an adder that performs addition. 7. An analog / digital converter for converting each of M (M is an integer of 2 or more) input analog signals into a digital signal and outputting the digital signal, wherein an m-th (m is 1 to M) input analog signal M-th variable gain means for amplifying the analog signal amplified by the m-th gain control signal, and m-th A / D conversion means for converting an analog signal amplified by the m-th variable gain means into a digital signal; An m-th DC offset compensator for measuring and removing a DC offset in the digital signal from the m-th A / D converter, and a second DC-offset compensator for measuring the power of the digital signal from the m-th A / D converter. m power measuring means, and the m-th gain control signal, which forms the m-th gain control signal so that the power measured by the m-th power measuring means keeps the reference level, and supplies the m-th gain control signal to the m-th variable gain means. Control means; m-th reference level control means for controlling a reference level given to the m-th gain control means based on the DC offset measured by the m-th DC offset compensation means; The gain of the digital signal from which the DC offset has been removed is corrected in accordance with the change in the reference level output from the m-th reference level control means, and the corrected digital signal is output as the m-th system output digital signal. m gain correction means, wherein the first to M-th gain correction means perform gain correction processing so that the total gain of the output digital signal with respect to the input analog signal is the same in all systems. Analog / digital converter. 8. The apparatus according to claim 7, wherein said m-th gain correction means performs a gain correction process according to a change in a reference level based on the DC offset measured by said m-th DC offset compensation means. 2. The analog / digital converter according to claim 1. 9. The apparatus according to claim 7, wherein the m-th gain correction means performs a gain correction process according to a change in the reference level based on the reference level obtained by the m-th reference level control means. 2. The analog / digital converter according to claim 1. 10. The analog-to-digital converter according to claim 7, wherein M is 2. The first gain correction means is configured to determine a reference level based on a reference level obtained by the second reference level control means. The second gain correction means performs gain correction processing according to a change in the reference level based on the reference level obtained by the first reference level control means. An analog / digital conversion device characterized by the above-mentioned.