JP3228171B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a mask ROM capable of increasing a storage capacity.

[0002]

Conventional mask ROM (read only memory) is a whether a drain current at a given gate voltage (Vg ₀₎ exceeds a predetermined value (Id _0), the data "1" and "0" However, only one piece of information can be stored in one memory cell.
The manufacturing method is determined by whether or not ions are implanted below the gate electrode.

FIG. 3 shows gate voltage-drain current characteristics (hereinafter, referred to as Vg-Ig characteristics) in a conventional mask ROM. The Vg-Ig characteristics of FIG. 3 (a), Vg ₀
At this time, since the drain current Id exceeds Id ₀ , the data becomes “0”, and according to the Vg-Ig characteristic of FIG.
Since the drain current Id does not exceed Id ₀ at the time of g _0, the data becomes “1”.

[0004]

However, in the conventional method for manufacturing a semiconductor memory device as described above, only one information can be stored in one memory cell, and the transistor has the Vg-Ig characteristic. Since only two different types can be formed, it is difficult to increase the storage capacity, and when the storage capacity is increased, there is a problem of an increase in the chip size due to an increase in the number of transistors.

The present invention solves such a conventional problem, and a method of manufacturing a semiconductor memory device having a gate voltage-drain current characteristic having a plurality of leakage currents and an on-current for a predetermined gate voltage. The purpose is to provide.

[0006]

Means for Solving the Problems] In the manufacturing method of the semiconductor memory device of the present invention in order to achieve this object, semiconductors
Forming an isolation oxide film on a body substrate , and forming a first, second, third, and fourth MOS transistors in which a gate electrode is formed on a gate insulating film and source / drain regions are formed. Forming each of the isolation oxide films separately ; performing a first ion implantation into a channel region below a gate electrode of the second and fourth MOS transistors and the isolation oxide film; And the fourth M
The channel region under the gate electrode of the OS type transistor and
And ion implantation from the first ion implantation into the isolation oxide film.
Performing a second ion implantation with a small amount of ion implantation.

In addition, the first ion implantation allows a MOS to be formed.
The leakage current of the Vg-Ig characteristic of the MOS transistor is increased, and the on-current of the Vg-Ig characteristic of the MOS transistor is increased by the second ion implantation.

Further, the impurity concentrations of the channel regions of the first to fourth MOS transistors are different from each other, and the output data is changed to the first by the two different gate voltages.
(0,0), the second MOS transistor
It is characterized in that (1, 0) for the type MOS transistor, (0, 1) for the third MOS type transistor, and (1, 1) for the fourth MOS type transistor.

According to the manufacturing method of the present invention, four kinds of Vg-
A MOS transistor having Ig characteristics can be formed. By changing the gate voltage of the MOS type transistor, each MOS type transistor becomes a multi-valued memory which can read binary data, and the storage capacity can be increased.

[0010]

Embodiments of the present invention will be described below in detail with reference to FIG.

FIGS. 1A to 1C are process sectional views of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.

First, after an isolation oxide film 2 is formed on a semiconductor substrate 1, first to fourth MOS transistors (hereinafter Tr1 to Tr4) having a gate insulating film 3, a gate electrode 4, and a source / drain region 5 are provided. (A).

Next, a resist pattern 6 is formed using a mask having the first ROM data. Then, T
Using the resist pattern 6 formed on the regions r1 and Tr3 as an ion implantation mask, a first ion implantation 7 for increasing leakage current is performed on channel regions of the Tr2 and Tr4 where the resist pattern 6 is not formed. (B). For example, boron as an impurity is 10 ¹⁴ / cm
Implant ³ ions.

Next, a resist pattern 8 is formed using a mask having the second ROM data. Then, T
Using the resist pattern 8 formed on the regions r1 and Tr2 as an ion implantation mask, a second ion implantation 9 for increasing the on-current is performed in the channel regions of the Tr3 and Tr4 where the resist pattern 8 is not formed. (C). For example, 10 ¹³ boron / cm 3 as an impurity
Implant ³ ions.

Thus, Tr1 which is not subjected to the first and second ion implantations, Tr2 which is subjected to only the first ion implantation, Tr3 which is subjected to only the second ion implantation, and first and second ion implantations are formed in the channel region. Tr also used as ion implantation
4, four types of MOS transistors are formed.

FIG. 2 shows an MO formed by the manufacturing method of FIG.
5 shows Vg-Ig characteristics of an S-type transistor. In the figure, when the gate voltage is Vg ₁ , Id is Id ₁
If it is less than or equal to “0”, it will be “1” if more than Id ₁ , and at the gate voltage Vg ₂ , it will be “0” if Id is more than Id ₂ and “1” if Id is less than Id _2. Become. Therefore, by changing the gate voltages (Vg ₁ , Vg ₂ ),
Output data is (0,0) for Tr1, and (1,0) for Tr2.
0), (0, 1) for Tr3 and (1, 1) for Tr4, so that binary data can be obtained from one MOS transistor.

In the above-described embodiment, the first ion implantation for increasing the leakage current and the second ion implantation for increasing the on-current are performed. The same effect can be obtained even if the second ion implantation is performed first.

In the above embodiment, the first and second
At the time of the ion implantation, the ions are implanted into the source / drain regions, but there is no problem if the ions are implanted only into the channel region below the gate electrode.

[0019]

As described above, according to the present invention, four kinds of Vg-
A MOS transistor having Ig characteristics can be formed. By changing the gate voltage of the MOS type transistor, each MOS type transistor becomes a multi-valued memory in which binary data can be read separately, and the storage capacity can be increased without increasing the area of the semiconductor device. .

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 shows V of the semiconductor memory device in the embodiment of FIG. 1;
g-Ig characteristic diagram

FIG. 3 is a Vg-Ig characteristic diagram of a conventional semiconductor memory device;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Separation oxide film 3 Gate insulating film 4 Gate electrode 5 Source / drain region 6, 8 Resist pattern 7 First ion implantation 9 Second ion implantation

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/8246 H01L 27/112

Claims (1)

(57) [Claims] 1. A process for forming an isolation oxide film on a semiconductor substrate.
A gate electrode is formed on the gate insulating film, and
First, second, third, and third where source / drain regions are formed
Fourth MOS transistors are respectively connected to the isolation oxide film.
Forming the second and fourth MOs separately.
Channel region and under the gate electrode of the S-type transistor
There rows first ion implantation into the isolation oxide film, MOS type bets
A step of increasing a leakage current of a Vg-Ig characteristic of the transistor, and a step of increasing a channel region under a gate electrode of the third and fourth MOS transistors and the isolation oxide film.
First had second row ion implantation ion implantation amount is less than the ion implantation, Vg-Ig characteristics of the MOS transistor
Increasing the on-state current of the semiconductor memory device.