JP3203845B2 - Method of forming gate electrode - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate electrode formed on a semiconductor substrate and a method for forming the same.

[0002]

2. Description of the Related Art In various semiconductor devices, a plurality of semiconductor elements having a gate electrode are formed on the same semiconductor substrate. The gate electrode is usually formed by a photolithography technique. As the integration of a semiconductor device progresses, the size of a gate electrode also decreases as the size of each semiconductor element decreases. At present, the 0.35 μm rule is being applied as a design rule. Therefore, it is necessary to make the pattern resolution in the photolithography technique for forming a fine gate electrode correspond to such miniaturization of a semiconductor element. Therefore, in photolithography technology, a light source having a wavelength shorter than the minimum dimension of a pattern to be formed on a semiconductor substrate or a semiconductor element is used.

Generally, in photolithography, a pattern is formed using a photomask. However, as the size of a pattern to be formed on a semiconductor substrate or a semiconductor element becomes smaller, the wave nature of light becomes more conspicuous as the wavelength of a light source used becomes shorter.
Therefore, there arises a problem that a pattern of a mask pattern formed on a photomask is not formed on a semiconductor substrate or a semiconductor element due to light interference called light diffraction or standing wave effect.

One means for solving this problem is a phase shift method. In a photomask used in this phase shift method, a pattern called a phase shifter for changing the phase of transmitted light is formed near the mask pattern.
Then, the light transmitted through the mask pattern and the light transmitted through the phase shifter are shifted in phase by, for example, 180 degrees.
A phase shifter is configured. By interfering light transmitted through the mask pattern and light transmitted through the phase shifter, a fine pattern having a shape similar to the shape of the mask pattern can be formed on a semiconductor substrate or a semiconductor element.

[0005]

However, the target mask pattern and the phase shifter cannot be formed unless a sufficient computer simulation is carried out during the production of the photomask, and the production cost of the photomask is high and the production time is high. Has the problem of being long. Further, since a phase shifter must be formed in addition to the mask pattern, the manufacturing process of the photomask is complicated.

Further, depending on the shape of a pattern to be formed on a semiconductor substrate or a semiconductor element, a phase shifter cannot be formed in some cases, and further, the size of the phase shifter for a mask pattern cannot be optimized.

On the other hand, there is an X-ray lithography technique as another means for forming a fine pattern, but a lens material and a photosensitive material for converging X-rays have not been developed. Also,
There is a problem that the cost is too high because a large-scale X-ray generator is required.

As another technique for forming a fine pattern, there is an electron beam lithography technique based on electron beam lithography. However, on a photosensitive material formed on a semiconductor substrate or a semiconductor element, more than a few million fine patterns are formed. Has to be drawn directly, which requires a long time for drawing, and has a problem of low throughput.

As described above, the current fine pattern forming technology has various problems, and a method for forming a fine gate electrode by the current photolithography technology is desired.

Accordingly, an object of the present invention is to provide a method of forming a fine gate electrode using a general photolithography technique, which is suitable for mass production without largely changing a conventional semiconductor device manufacturing apparatus, and a fine gate. It is to provide an electrode.

[0011]

According to the present invention, there is provided a method for forming a gate electrode, comprising the steps of: (a) forming an opening forming layer on a semiconductor substrate and then forming a gate electrode on the semiconductor substrate; Forming an opening in the opening forming layer located above the region, and (b) forming a side spacer on the side wall of the opening and covering a portion of the semiconductor substrate located at the bottom of the opening with the side spacer. And (c)
The method comprises the steps of: burying a gate electrode material in an opening to form a gate electrode portion; and (d) removing an opening forming layer.

In the method of forming a gate electrode according to the present invention, the opening forming layer and the side spacer are formed by, for example, LP-
SiO ₂ , PSG, BSG, BPSG by CVD method,
It can be made of various insulating materials such as Si ₃ N ₄ .
The gate electrode material is preferably made of a silicon-based material. Further, the formation of the opening in the opening forming layer in the step (a) may be performed, for example, by forming a resist layer on the opening forming layer, and then forming a resist layer patterned by photolithography using a photomask. The opening is then formed by etching the opening forming layer using the resist layer as a mask. The removal of the opening forming layer in the step (d) is performed, for example, after forming the resist layer,
Forming a resist layer patterned by photolithography using a photomask having a pattern opposite to that of the photomask used in the step (a), and then etching the opening forming layer using the resist layer as a mask; Can be performed. Further, between the steps (b) and (c), a gate oxide film may be formed on the semiconductor substrate exposed at the bottom of the opening.

It is desirable to remove the opening forming layer by anisotropic etching.

According to another aspect of the present invention, there is provided a gate electrode including a gate electrode portion made of a gate electrode material and side spacers formed on side walls of the gate electrode portion. The size of the horizontal section is larger than the size of the horizontal section below the gate electrode portion.

In the gate electrode of the present invention, the gate electrode material is preferably made of a silicon-based material. The side spacer is made of, for example, S-LP by the LP-CVD method.
It can be made of various insulating materials such as iO ₂ , PSG, BSG, BPSG, and Si ₃ N ₄ .

[0016]

According to the method of forming a gate electrode of the present invention, an opening is formed by a conventional photolithography technique. Then, since the side spacer is formed on the side wall of the opening, the size of the gate electrode portion formed by embedding the gate electrode material and substantially functioning as the gate electrode can be made smaller than the size of the opening. it can. That is, by the conventional photolithography technology,
A fine gate electrode can be formed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

First, after forming the opening forming layer 14 on the silicon semiconductor substrate 10, the opening 18 is formed in the opening forming layer 14 located above the gate electrode forming region of the semiconductor substrate.
To form

For this purpose, after an element isolation region 12 is formed in a silicon semiconductor substrate 10 by a conventional method, the device isolation region 12 is made of SiO ₂ by, for example, LP-CVD, and is formed to a thickness of 200 nm.
An opening forming layer 14 having a thickness of about the same thickness is deposited on the entire surface (see FIG. 1A).

Next, after a resist layer is applied to the entire surface, a patterned resist layer 16 is formed by photolithography using a first photomask (see FIG. 1B). In this embodiment, a positive resist material is used, and a mask pattern is formed on the first photomask so that light is applied to the resist layer located above the region where the gate electrode is to be formed. I have.
When a negative resist material is used, a mask pattern is formed on the first photomask so that light is applied to a resist layer located above a region other than a region where a gate electrode is to be formed. The pattern interval width L of the resist layer 16 corresponding to the length of the gate electrode to be formed is 0.5
〜0.35 μm.

Next, the opening 18 is formed by etching the opening forming layer 14 using the resist layer 16 as a mask by using a conventional vapor phase etching technique.
6 is removed (see FIG. 1C).

Next, a side spacer 22 is formed on the side wall of the opening 18, and a part of the semiconductor substrate located at the bottom of the opening 18 is covered with the side spacer 22.

That is, first, for example, LP-CVD
A side spacer forming layer 20 made of SiO ₂ and having a thickness of about 200 nm is deposited by a method (see FIG. 1D). Thereafter, the side spacer forming layer 20 is etched by a normal vapor phase anisotropic etching technique, and the side spacer 22 is formed from the side spacer forming layer (FIG. 2).
(A)). The thickness of the side spacer 22 at the bottom of the opening 18 was 0.1 μm. When the side spacer 22 is formed by etching the side spacer forming layer 20 by the vapor phase anisotropic etching technique, the thickness of the side spacer 22 near the edge 18 </ b> A of the opening 18 is lower than the bottom of the opening 18. Is thinner than the thickness of the side spacer 22 in FIG. The side spacer 22
The desired thickness can be controlled by adjusting the etching time. Here, 1.1 times the time of the time required to etch the side spacer layer up to the surface of the semiconductor substrate 10, side spacer type
The formed layer 20 was etched. Thus, a portion of the semiconductor substrate located at the bottom of the opening 18 is
Covered by

Next, the semiconductor substrate exposed at the bottom of the opening 18 is made of SiO ₂ by thermal oxidation to a thickness of 8 to 8 mm.
A 10 nm gate oxide film 24 is formed.

Thereafter, a gate electrode material is buried in the opening 18 to form a gate electrode portion 26. Specifically, a phosphorus-doped amorphous silicon layer 28 having a thickness of about 100 nm is deposited on the entire surface by a conventional LP-CVD method, and then a tungsten silicide layer 30 having a thickness of about 100 nm is deposited on the entire surface ( FIG. 2 (B)
reference). In this embodiment, the gate electrode material is made of a silicon-based material such as phosphorus-doped amorphous silicon and tungsten silicide. In addition, phosphorus doped
The amorphous silicon contains 1 to 2% by weight of phosphorus. Instead of phosphorus-doped amorphous silicon, phosphorus-doped polysilicon or amorphous silicon or polysilicon doped with boron or arsenic can be used.

Next, the opening forming layer 14 is removed. That is, after a resist layer is applied on the entire surface, a patterned resist layer 32 is formed by a photolithography technique using a second photomask (see FIG. 2C). In the present embodiment, a positive resist material is used, and the second photomask is provided with a mask pattern that irradiates light to a resist layer located above a region other than a region where a gate electrode is to be formed. Is formed. When a negative resist material is used, a mask pattern is formed on the second photomask so that the resist layer located above the region where the gate electrode is to be formed is irradiated with light.

Next, the tungsten silicide layer 30, the phosphorus-doped amorphous silicon layer 2 and the
8 and the opening forming layer 14, the resist layer 32 is removed.
(See FIG. 2D). That is, the entire surface is selectively etched to the opening forming layer 14 by anisotropic etching. Thus, a gate electrode including the gate electrode portion 26 made of the gate electrode material and the side spacer 22 formed on the side wall of the gate electrode portion is formed. In the gate electrode, as a result of being affected by the vertical cross-sectional shape of the side spacer 22, the size of the horizontal cross section of the upper portion of the gate electrode portion is larger than the size of the horizontal cross section of the lower portion of the gate electrode portion.

The pattern interval width L of the resist layer 16 corresponding to the length of the gate electrode to be formed is, for example, 0.5 μm or 0.35 μm, and the thickness of the side spacer 22 at the bottom of the opening 18 is, for example, 0.1 μm. When it is 1 μm, the gate length of the gate electrode is 0.3 μm or 0.15 μm.
m.

Although the present invention has been described based on the preferred embodiment, the present invention is not limited to this embodiment. SiO ₂ is formed on a semiconductor substrate on which an element isolation region is formed.
After the formation of the gate oxide film made of SiO ₂ , the gate electrode can be formed based on the above embodiment using the opening forming layer and the side spacer forming layer made of an insulating material different from SiO ₂ . However, in this case, the step of forming the gate oxide film described in the embodiment is unnecessary.

The numerical values, the method of forming the opening forming layer and the side spacer forming layer, the type of the gate electrode material and the embedding method described in the embodiment are merely examples, and can be changed as appropriate. As an example, an opening forming layer and a side spacer forming layer made of SiO ₂ can be formed using a TEOS-based gas.

In the embodiment, the silicon semiconductor substrate 1
Although the method of forming a gate electrode on the surface of the substrate 0 has been described as an example, the method of forming a gate electrode and the gate electrode of the present invention can be applied to another semiconductor substrate, for example, a GaAs substrate. For example, when manufacturing a top gate thin film transistor, a gate electrode may be formed on a polysilicon layer in some cases. Therefore, such a polysilicon layer is also included in the semiconductor substrate of the present invention.

[0032]

According to the present invention, a fine gate electrode can be formed by using a normal photolithography technique. The dimensions of the mask pattern of the photomask can be larger than the dimensions required for the gate electrode,
There is no increase in the production cost and production time of the photomask. Moreover, the present invention is suitable for mass production without largely changing the conventional semiconductor device manufacturing apparatus, and does not cause an increase in semiconductor device manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view illustrating a method for forming a gate electrode according to the present invention.

FIG. 2 is a schematic partial cross-sectional view following FIG. 1 for explaining a method of forming a gate electrode of the present invention.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 12 element isolation region 14 opening forming layer 16 resist layer 18 opening 20 side spacer forming layer 22 side spacer 24 gate oxide film 26 gate electrode portion 28, 30 layer of gate electrode material 32 resist layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57) [Claims] (A) forming an opening in the opening forming layer located above the region where the gate electrode is to be formed on the semiconductor substrate after forming the opening forming layer on the semiconductor substrate; Forming a side spacer on the side wall of the opening and covering a portion of the semiconductor substrate located at the bottom of the opening with the side spacer; (c) embedding a gate electrode material in the opening and forming the gate electrode portion forming, (d) removing said opening forming layer, Ri consists, formation of the openings of the opening-forming layer in the step (a)
After forming a resist layer on the opening forming layer,
Using a photolithography technique with a mask,
Forming a coated resist layer, and then forming the resist layer
Is used to etch the opening forming layer.
The removal of the opening forming layer in the step (d) is performed by a resist
After the formation of the photomask, the photomask used in the step (a) is used.
Using a photomask having a pattern opposite to that of the
Resist patterned by photolithography
Layer, and then opening using the resist layer as a mask.
A method for forming a gate electrode, which is performed by etching a portion forming layer . 2. A method of forming a gate electrode according to claim 1 gate electrode material, characterized in that it consists of silicon material.