JP3290703B2 - Manufacturing method of semiconductor energy detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a back-illuminated charge-transfer type semiconductor energy detector which is effective for irradiating an energy ray having a very large absorption coefficient, such as ultraviolet rays, radiation, and particle beams. It is.

[0002]

2. Description of the Related Art A charge transfer device (CCD) sequentially transmits an analog charge group in one direction at a speed synchronized with a clock pulse from the outside. It is a very clever functional device that can be converted to a series signal. However, in order to extract two-dimensional image information as a time-series signal, a device needs to be devised due to the configuration of the device. If the charge is transferred while the above-described device is irradiated with light, the photo-excited charge and the transferred charge are mixed at each location, and the video signal is degraded. In order to avoid this, a so-called time-sharing operation that temporally divides a light irradiation period (charge accumulation period) and a charge transfer time (charge transfer period) can be considered. Therefore, the time during which the video signal is output is limited to the transfer time, and is an intermittent signal.

[0005] Generally, three methods of a frame transfer (FT), a full frame transfer (FFT), and an interline transfer (IT) configuration are typical as practical imaging devices. Of these, the full frame transfer method is mainly used for measurement.

Hereinafter, a full frame transfer system will be described. 8 and 9 show the configuration of an imaging device using the full frame transfer method. FIG. 8 is a top view of the imaging device, and FIG. 9 is a cross-sectional view of a main part thereof. In this method, as shown in FIG. 8, the channel for charge transfer is divided in the vertical direction by the channel stop diffusion layer 1 formed on the substrate to form a pixel column corresponding to the number of horizontal pixels. On the other hand, a transfer electrode group 2 is arranged orthogonal to the channel stop diffusion layer 1. In the above-described frame transfer method, the electrode group 2 is grouped into two upper and lower parts,
The upper half is used as a CCD for receiving light and the lower half is used as a CCD for temporarily storing signal charges. However, the full frame transfer type CCD shown in FIG. 8 has no storage unit. Therefore, during the charge transfer time, that is, during the read time, the shutter must be closed to prevent light from entering the CCD. Note that three overflow drains 5 are formed between the four pixel columns in the vertical direction.

When light enters the light receiving region, as shown in FIG. 9, the excited signal charges exist under one transfer electrode (storage electrode), that is, under the polysilicon electrode 20 to which the rising clock pulse φ ₁ is applied. Collected in the potential well 3. One pixel has an area surrounded by the number of electrodes 20 and the channel stop diffusion layer 1 corresponding to the number of phases (4) of the clock pulses (φ _{1 to} φ ₄ ) constituting one stage of the CCD. The vertical transfer clock pulse electrode group 2 supplies clock pulses φ _{1 to} φ ₄ to the silicon electrode 20. As shown in FIG. 9, an interlayer insulating film 19 made of PSG (phosphorus glass) is deposited on the upper surface of the polysilicon electrode 20, and a gate oxide film 21 is interposed between the electrode 20 and the silicon substrate 22.

When the charge storage time for converting the optical signal into signal charge ends, the clock voltages φ _{1 to} φ ₄ applied to the vertical transfer electrode group 2 on the light receiving region sequentially rise to start reading the signal charge. . However, in the full frame transfer CCD, as described above, the frame transfer CC is used.
There is no so-called storage section different from the light receiving section such as D. Therefore, if the input of the optical signal is not interrupted by closing the shutter or the like before starting the signal reading, the optical signal is newly mixed into the signal being transferred, and the signal purity is reduced. descend. However, when capturing a one-shot phenomenon, it is considered that there is no new light input during the transfer of the signal charge, so that a shutter or the like is not required.

Here, a signal reading operation will be described with reference to FIG. The signal charges are sent downward one row at a time by the pulses φ ₁ to φ ₄ applied to the clock pulse electrode group 2 for vertical transfer, and are transferred to the output terminal through the horizontal read register 6. That is, in FIG. 8, first, the signal charges in the lowermost row are simultaneously sent to the horizontal readout register 6, and the clocks φ ₅ , φ ₆
And read from the output terminal as a time series signal. The horizontal transfer clocks φ ₅ and φ ₆ are applied from the horizontal transfer clock pulse electrode group 7. At this time, since the next signal charge has already moved down by one stage, it enters the horizontal read register 6 at the next vertical transfer clock pulse,
Read to the output end. When all the signal charges for one screen are read out through the horizontal readout register 6, the shutter is opened and a new signal accumulation operation is started. As described above, since the horizontal read register 6 operates at a higher speed than the vertical register, high-speed transfer is enabled by using two-phase clock pulses φ ₅ and φ ₆ .

FIG. 10A shows an example of a readout circuit on-chip in a CCD, and FIG. 10B shows an example showing a relationship between an applied clock pulse and an output waveform. The reference point of the pulse is 0V with an amplitude of + 12V. Areas 17 and 18 below the electrodes to which the clocks φ ₅ and φ ₆ are applied represent the final part of the horizontal register 6. The substrate 22 has + 12V _DC , and the output gate (OG) 13 has + 12V _DC .
7V _DC , + 12V _{DC for} reset drain (RD) 16
Has been added. The drain 8 of the amplifying MOSFET has a voltage of 15 V _DC , and the source 9 is grounded via a load resistor. Therefore, this MOSFET operates as a source follower circuit. Hereinafter, the operation will be described with reference to FIG.

It is assumed that signal charges are successively transferred to the readout circuit by the horizontal register 6. At time t
_{In 1} , the clock pulse φ ₅ is at the high level, so that a potential well is formed in the region 17 below the electrode 7 to which the clock φ ₅ has been applied, and the signal charge has been transferred to the region 17. Next, at time t ₂ clock φ
_{Since 5} is at a low level and φ ₆ is at a high level, the potential well in the region 17 under the electrode 7 to which the clock φ ₅ is applied disappears, and the potential well in the region 18 under the electrode 7 to which the clock φ ₆ is applied. It is formed. Therefore, the aforementioned signal charges are transferred to the region 18. Time t ₃
In the above, since a pulse is applied to the reset gate (RG) 15, the floating diffusion (FD)
The potential of 14 is reset to 12 V which is the potential of RD16. At time t ₄ , since the signal charge has not been transferred to the FD 14 yet, the potential maintains the reset value. At the time t ₅ , the clock φ ₆ becomes low level, so that the signal charge existing in the region 18 at the last part of the horizontal register 6 gets over the low potential barrier formed by the low DC bias applied to the OG 13,
FD14 is reached, and its potential is changed. FIG. 10 (b)
As can be seen in the example of the output voltage of the electron come flows, the output clock phi ₆ is at a low level extends downward. The FD 14 is connected to the gate of a source follower circuit (MOSFET) by wiring, and an output of the same magnitude as that input to the gate can be obtained from the source with low impedance.

As described above, the feature of the full frame transfer system is that the light receiving portion has a large area without the accumulation portion, so that the light utilization rate is high, and therefore, the full frame transfer method is widely used for faint light use such as measurement. On the other hand, since incident light is absorbed by the transfer electrode, the sensitivity to input having a large absorption coefficient, for example, blue light having a short wavelength is significantly reduced. As mentioned earlier, FIG.
Shows a typical light receiving portion, but a polysilicon electrode 20 covers the surface without any gap, and a PSG film 19 having a thickness of several microns is further laminated to separate the electrodes. In particular, the polysilicon is 400 nm
Since it absorbs light of the following wavelengths and low energy electron beams, it cannot contribute to photoelectric conversion.

With respect to such a photodetector, the substrate 22
Is thinned from about 15 μm to about 20 μm, and light is emitted from the back as shown in FIG. The surface of the substrate 22 is covered without gaps by the polysilicon electrode 20 with the gate oxide film 21 interposed therebetween, and absorbs short-wavelength light. However, on the back surface of the substrate 22, there is no obstacle other than the thin oxide film 23. High sensitivity can be expected for short wavelength light. This back-illuminated CCD has sensitivity to light having a short wavelength of about 200 nm, and is further applied to an electron impact CCD imaging device. This device can be used as a high-sensitivity imaging device because it can use the multiplication effect of signal charges generated by electron impact.

Here, a typical example of a manufacturing process of the above-mentioned back-illuminated CCD will be described. First, as a wafer, P
A P / P ⁺ -type epitaxial wafer in which a P layer and a P ⁺ layer doped with a type impurity are stacked is used. The specific resistance and thickness of this epi layer are 30Ω-cm and 30 μm, respectively.
The specific resistance and thickness of the sub-epi layer are 0.01Ω respectively.
−cm, 500 μm. For this epi wafer,
All the CCD manufacturing processes including the aluminum (Al) wiring process are completed in advance. Although it is naturally conceivable to apply Al wiring after thinning the light-receiving portion silicon in a later step, it is difficult to use a photo-etching method for the thinned film portion. The thinned part may be broken. For this reason, it is necessary to complete as many processes as possible before thinning so as not to lower the yield.

Next, the silicon nitride film and the silicon oxide film on the back surface of the wafer are removed.

Thereafter, a chrome / gold layer formed by laminating chrome and gold is deposited on the entire back surface. This functions as an etching mask in a later step. Then, only the portion corresponding to the light receiving surface, that is, only the region corresponding to the rear incident surface
The chrome / gold layer is removed.

After dividing the above-mentioned epi wafer into chips, the wafer is attached to a holder with wax. Then, HF: HN
The silicon substrate is etched from the back surface using an etchant having a ratio of O ₃ : CH ₃ COOH = 1: 3: 8 while leaving the peripheral portion of the chip thick. Since this etching solution is rich in nitric acid, the etching proceeds with the rate of dissolution control by hydrofluoric acid. If the solution is sufficiently agitated to control the dissolution and a new etchant is not always applied to the etched surface, the film thickness becomes extremely uneven.

Here, the reason why the dissolution-controlled etchant is widely used will be described. If it is rich in hydrofluoric acid,
Etching proceeds at the rate of oxidation control. Here, since the wafer to be used is a P / P ⁺ type, if only the P ⁺ layer is selectively etched, a wafer excellent in absolute value of film thickness and in-plane uniformity can be manufactured, and short wavelength sensitivity can be improved. It is very easy to control reproducibility and uniformity. In this respect, since the oxidation rate of the P ⁺ layer is high in the case of an oxidation-controlled etching solution, there is a possibility that a film having excellent film thickness uniformity and reproducibility can be produced.

However, in reality, since there are many crystal defects in the P ⁺ layer, the oxidation rate is further increased, so that the etching is performed quickly. Defects cause the thickness of the etched surface to be non-uniform, resulting in fogging of the light receiving surface. Therefore, an oxidation-controlled etchant cannot be used, and it is difficult to control the film thickness. However, a solution-controlled etchant must be used. When an alkaline etchant is used, the film thickness is excellent in uniformity and controllability.
In an OS device, a gate oxide film is contaminated with an alkali metal contained in an etchant, and a threshold voltage or the like is different from a design value, thereby causing an operation failure. Therefore, conventionally, an alkaline etchant has not been used in the process.

After the etching is completed by the above method, the film thickness is measured. As a result, if the film thickness is insufficient as a desired value, etching is performed again.

Thereafter, the above-mentioned wafer is oxidized on the back surface in steam at 120 ° C. for 48 hours. At this stage, Al
Since the wiring is completed, it is impossible to oxidize by applying a high temperature. Therefore, oxidation is performed at a low temperature of 120 ° C. for a long time.

Next, the back oxide film is irradiated with negative ions.
A so-called backside accumulation is performed. This is because, in order to increase the sensitivity to short wavelengths, it is necessary to make the backside silicon into an accumulation state so that photoelectrons can efficiently reach the potential well of the CCD. In a back-illuminated CCD, the back surface of the CCD is a light incident surface. Usually, the thickness of the silicon wafer forming the CCD is several hundred microns. In addition, from 200 nm to 300 nm
This light has a very large absorption coefficient, and most of it is absorbed when it enters a little from the surface. Therefore, even if a CCD having a thickness of several hundred microns is used as it is as a backside illumination type, photoelectrons generated on the backside cannot diffuse into the potential well of the CCD on the front side, and most of them recombine. Lost. Also, even if some of them can reach the potential well, the signals are mixed while spreading along a long way, so that the so-called resolution is remarkably reduced. Therefore, in the back-illuminated CCD, the back surface, which is the light receiving surface, must be thinned by etching and polishing so that the generated electrons can reach the surface potential well in the shortest distance. As shown in FIG. 11, a typical detection element using silicon has a thickness of 15 to 20 μm. Here, oxide film 23 has a thickness of several tens to several hundreds of angstroms.

FIG. 12 shows a potential profile of a cross section from the light receiving surface to the CCD on the surface of the silicon detecting element thinned in FIG. Referring to the drawing, the left side represents the back surface of the substrate, and the right side represents the front surface of the substrate. Note that the substrate 22 is a P-type. On the back surface of the substrate 22, a silicon oxide film 23 as a protective film is grown.

However, oxide film charges and interface states always exist in the silicon oxide film 23, and all of them work to deplete the surface of the P-type silicon substrate 22. That is, from the viewpoint of the potential profile, as shown by the solid line in FIG. 12, the potential for electrons decreases as approaching the silicon oxide film 23 on the back surface. On the contrary, it is pushed to the interface between the backside silicon oxide film 23 and the silicon substrate 22 and is destined to wait for reconnection. Therefore, the silicon oxide film 23 is charged by irradiating negatively charged ions after thinning the light receiving portion and oxidizing the back surface, thereby the silicon substrate 2
The surface of No. 2 is in an accumulation state. Thus, a potential profile as shown by a dotted line in FIG. 12 can be obtained. For this reason, photoelectrons generated at a shallow position on the back surface can efficiently reach the potential well of the CCD.

In general, when performing accumulation, boron ions may be implanted into a P-type silicon substrate. However, the ion implanted layer becomes amorphous, and recrystallization and ion implantation are performed by a subsequent heat treatment. The activated boron atoms must be activated. Usually, this heat treatment (annealing) requires so-called two-step annealing in which heat treatments at around 600 ° C. and around 1000 ° C. are continuously performed. If annealing is insufficient, the life of minority carriers is shortened, and short-wavelength sensitivity cannot be increased. Therefore, accumulation of the backside silicon by ion implantation can be achieved, and in reality, only passive accumulation such as irradiation with negative ions is employed.

Finally, the wafer having undergone the above operation is mounted in a package. Cooling a CCD to reduce leakage current and rms noise is an important technique for measuring weak light. Therefore, in this step, the surface of the thinned silicon substrate, that is, the surface on which the CCD is formed, is bonded to the package via a non-conductive resin having a low thermal resistance.

[0025]

However, the above-mentioned manufacturing method has problems in the following points. For example, since a solution-controlled etchant is used for etching the substrate, the thickness of the film becomes extremely non-uniform unless the etchant is sufficiently stirred and a new etchant is constantly supplied to the etching surface. However, no matter how much agitation is performed, a step is formed at the boundary between the etched portion and the portion not to be etched due to the wraparound of the etchant or the like, and the film thickness tends to be non-uniform. Further, when measuring the film thickness, the CCD chip must be once removed from the holder. However, since the film thickness of the region corresponding to the light receiving portion of the CCD chip has already become considerably thin, there is a possibility that the thin film portion may be damaged while being taken from or attached to the substrate.

Further, as described above, in the negative accumulation of irradiating the oxide film with negative ions, there is a problem in the persistence of the effect, and in order to improve the sensitivity to short wavelength light, such an operation is required. Despite this, the negative ions attached to the back surface oxide film are easily removed or easily neutralized by irradiation with short wavelength light. That is, the accumulated state becomes depleted again,
The sensitivity to short wavelength light is lost.

Therefore, consider a case where accumulation is performed by ion implantation ignoring the yield. In order to perform ideal annealing, it is necessary to reduce the thickness of the Al wiring before Al wiring, implant ions of boron atoms into the light receiving surface, and perform annealing.

Annealing is performed by continuously performing heat treatment at around 600 ° C. and around 1000 ° C. as described above.
Step annealing is desirable. However, unless an oxide film is formed at the earliest possible stage during the heat treatment and the outdiffusion of ion-implanted boron atoms is avoided, the boron concentration on the surface becomes low and the intended potential profile cannot be formed. However, even if an oxide film is formed, boron atoms are very easily incorporated into the oxide film, and a so-called redistribution phenomenon of impurity atoms occurs. The boron concentration becomes lower than the deep boron concentration, and the intended potential profile cannot be formed.

As described above, when a P-type wafer is used, even if boron is ion-implanted and annealed to the light-receiving surface to create an accumulation state, the surface has a potential profile opposite to the ideal. For electrons that are signal charges, the surface is more stable than the inside, and the signal charges generated at a shallow position are collected on the surface and recombined at the interface between the silicon and the oxide film. Therefore, the improvement of the short wavelength sensitivity naturally becomes a lower value than expected.

As described above, the problems with the conventional manufacturing method can be summarized as follows.
When wiring is performed, the degree of freedom of the heat treatment for accumulation on the back surface is increased, and two-step annealing can be performed after ion implantation of boron atoms. But,
When annealing is performed without an oxide film, the surface concentration decreases due to boron atom outdiffusion, and when annealing is performed with an oxide film, a large amount of boron atoms are incorporated into the oxide film. Can not be in the state of the operation. Furthermore, it is difficult to perform photolithography at the time of Al wiring, and the thin film may be damaged when the die bond is cured.

On the other hand, when the thinning is performed after the aluminum wiring, only the assembling is performed after the thinning, so that the probability of damaging the thin film portion is reduced. However, backside accumulation is difficult, and the thin film portion may be damaged when the die bond is cured.

In both cases, since the CCD portion is not protected, it is not possible to use an alkali-based etchant excellent in uniformity and controllability of the film thickness.

As described above, the conventional backside illumination type CC
The D manufacturing process is problematic and very difficult to commercialize.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor energy detector which has solved the above-mentioned problems.

[0035]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor energy detector in which an energy ray is incident from the back surface of a semiconductor thin plate, comprising: a first silicon wafer having a low impurity concentration; A first step of bonding and integrating a second silicon wafer having the same conductivity type and a high impurity concentration by heat treatment via a silicon oxide film, and a step opposite to a bonding surface of the first silicon wafer, A second step of forming a charge readout portion by arranging a plurality of charge transfer elements, and starting etching from a surface opposite to a bonding surface of the second silicon wafer to expose a silicon oxide film on the bonding surface. And a third step of forming a semiconductor energy detecting element.

Here, between the second step and the third step, the first and second silicon wafers on which the charge readout portions are integrally formed are provided with metal bumps on a preformed auxiliary substrate. It is sufficiently possible to further include a step of filling the resin between the first and second silicon wafers and the auxiliary substrate and curing the resin between the first and second silicon wafers and the auxiliary substrate.

It is preferable that the first silicon wafer is formed by epitaxial growth, and it is preferable to use an alkaline etchant when etching the second silicon wafer. Furthermore, the second silicon wafer may have a high impurity concentration at least on the bonding surface side.

[0038]

According to the present invention, a low-impurity-concentration silicon wafer is bonded to a high-impurity-concentration silicon wafer by heat treatment to be integrated, so that the high-impurity-concentration silicon wafer becomes a diffusion source of the impurity and becomes low-impurity. The impurity is diffused into the silicon wafer having a low concentration, and a high-concentration impurity region is newly formed in the silicon wafer having a low impurity concentration. Thus, the accumulation state can be maintained.

On the other hand, the formed semiconductor energy detecting element and the auxiliary substrate are connected, and the space between them is filled with resin before etching is performed. Therefore, the oxide film in the detecting element functions as an etching stopper, and the etching is performed during etching. To C
The CD section does not come into contact with the etchant, so that contamination of the CCD section can be prevented. Furthermore, by assembling the semiconductor energy detecting element and the auxiliary substrate while connected, the thinned detecting element can be prevented from being damaged.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor energy detector according to the present invention will be described below with reference to the drawings.

FIG. 1A shows an epitaxial growth layer (hereinafter referred to as an epi layer) 24 of the same conductivity type as the substrate 25 on an N-type or P-type substrate 25.
Shows the state where it has grown. Here, the epi layer 24 is
For example, the specific resistance is 10 Ω-cm and the thickness is 15 μm.
00 μm. The thickness of the epi layer 24 needs to be the same as the thickness of the light-receiving portion after thinning, or about 15 μm to 20 μm, which is slightly thicker. Hereinafter, the epi layer 24 is referred to as a first wafer 24.

Next, an oxide film is formed. FIG. 1 (b)
FIG. 3A shows a state in which a silicon oxide film 26 is formed on the surfaces of the first wafer 24 and the substrate 25 in FIG. This silicon oxide film 26 has a thickness of several hundred angstroms.

FIG. 4C shows a separately prepared bulk wafer having a high impurity concentration or a wafer having a high concentration impurity layer formed only on its surface, and has the same conductivity type as the first wafer 24 described above. is there. Here, 1 × for N-type
An impurity concentration of about 10 ¹⁹ cm ⁻³ or about 5 × 10 ¹⁸ cm ^{−3 for} a P-type is appropriate. Hereinafter, this bulk wafer is referred to as a second wafer 27.

Next, the first and second wafers are bonded together. FIG. 4D shows the first wafer 24 provided with the silicon oxide film 26 shown in FIG.
FIG. 11 is a view showing a state where the semiconductor device is turned upside down in the figure and the epi-layer side and the second wafer 27 having a high impurity concentration shown in FIG. The silicon oxide film 26 is a bonding surface. Here, a silicon oxide film is provided on one side of the bonding surface, but may be provided on both sides. These direct bonding techniques for silicon wafers use two methods without using an adhesive.
This is a technology that integrates two wafers. It is very firmly adhered only by heat treatment while applying hydrophilicity or applying voltage to the surface. This technique is described in detail in the following document “Applied Physics Vol. 60, No. 8, (1991) Direct Bonding Technique for Si Wafer”.

What is clear here is that the heat treatment at the time of bonding the silicon wafers causes impurities from the second wafer 27 having a high impurity concentration to the first wafer 24 having a low impurity concentration via the silicon oxide film 26. Diffusion is what happens.

Here, as an example, the first wafer 24
A thermal oxide film of 50 angstroms is formed, and as an example of a heat treatment for bonding and forming a CCD, 9 ° C. at 1100 ° C.
A specific example of what impurity profile is caused in the first wafer 24 when performed for 0 minutes will be described.

FIG. 2 shows that a 250 Å thermal oxide film is grown on a first silicon wafer having a boron concentration of 2 × 10 ¹⁵ cm ^{-3, and} a second wafer having a boron concentration of 5 × 10 ¹⁷ cm ^-3 and silicon are formed. Bonded through an oxide film, 110
FIG. 9 shows an impurity profile after heat treatment at 0 ° C. for 90 minutes. The diffusion of boron atoms from the second wafer having a high impurity concentration to the first wafer having a low impurity concentration occurs. The boron concentration at the bonding surface of the first wafer is 1.12 × 10 ¹⁸ cm ^-3 and the depth is 1. Is about 1 μm. As shown by the broken line in the figure, when annealing is performed after boron ions are implanted, boron is absorbed into the silicon oxide film, and the boron concentration near the silicon oxide film interface of the first wafer decreases. According to the present embodiment, there is no such concern.

FIG. 3 shows that a 250 Å thermal oxide film is grown on a first silicon wafer having a phosphorus concentration of 2 × 10 ¹⁵ cm ^{-3, and} a second wafer having a phosphorus concentration of 1 × 10 ¹⁹ cm ^-3 and silicon are formed. Bonded via oxide film 9 at 1100 ° C
7 shows an impurity profile after heat treatment for 0 minutes. Phosphorus atoms diffuse from the second wafer having a high impurity concentration to the first wafer having a low impurity concentration. The phosphorus concentration at the bonding surface of the first wafer is 3 × 10 ¹⁶ cm ^-3 and the depth is about It can be seen that it was 1 μm. Note that there is no decrease in the phosphorus concentration near the interface of the first wafer with the silicon oxide film.

FIG. 4 shows an antimony concentration of 2 × 10 ¹⁵ cm ^-3.
A 250 Å thermal oxide film is grown on the first silicon wafer having an antimony concentration of 1 × 10 ¹⁹ cm ^−3.
7 shows an impurity profile after bonding the second wafer through a silicon oxide film through a heat treatment at 1100 ° C. for 90 minutes. Antimony atoms diffuse from the high impurity concentration second wafer to the low impurity concentration first wafer, and the antimony concentration at the bonding surface of the first wafer is 1.3 × 10 ¹⁷ cm ⁻³ and the depth is Is about 0.5 μm
You can see that it became. It should be noted that there is no decrease in the antimony concentration near the silicon oxide film interface of the first wafer.

As described above, the low impurity concentration first
On the bonding surface side of the wafer 24, an impurity region 28 having a high concentration toward the surface was formed.

Next, etching is performed. FIG. 1 (e)
This shows a state where the substrate 25 has been removed by polishing or etching. Further, a part of the first wafer 24 may be slightly removed. However, it should be noted here that the silicon oxide film 2 that is left unetched, that is, from the surface of the first wafer 24 to the bonding surface.
The thickness up to 6 finally becomes the thickness of the light receiving surface. Therefore, this thickness must be accurately controlled to 15 microns or the like.

Here, an explanation has been given using an epitaxially grown wafer as the first wafer 24 serving as a portion for forming a CCD. The feature of epitaxial growth wafer is that there is no swirl as seen in bulk wafer,
Further, since the oxygen concentration is low, the crystallinity is excellent. Accordingly, although a bulk wafer can be applied, a higher yield can be expected by using an epitaxial growth wafer. At this stage, the surface damage layer generated at the time of polishing or etching must be completely removed.

Next, the surface side of the first wafer 24 shown in FIG. FIG. 5 (a) shows the first
2 shows a state in which the CCD 30 is formed on the surface of the wafer 24 and the metal wiring 29 is further provided.

Next, as shown in FIG. 5B, a silicon nitride film 31 is deposited on the entire upper and lower surfaces of the wafer after the steps up to FIG. Thereafter, the silicon nitride film 31 in the area where the metal bumps 32 are to be grown on the surface on which the CCD 30 is formed is removed. On the surface opposite to the surface on which the CCD 30 is formed, the silicon nitride film 31 in the region to be thinned is removed.

Here, as an example of a method of forming the bump 32, an example in which a solder bump is formed by an ultrasonic method will be described.

FIG. 6 is a schematic diagram of an ultrasonic soldering apparatus. The solder 43 filling the solder bath 45 is jetted by a stirrer 44 installed inside the solder bath 45. On the upper part of the solder tank 45,
The CCD wafer 41 is vertically arranged in the
The ultrasonic transducer 42 is placed so as to face the vertical surface of the CCD wafer 41 from the outside of the device 5. In this apparatus, a CCD wafer 41 facing an ultrasonic transducer 42 is used.
, Fresh solder is always sent to the surface, and the oxidation of the solder is prevented by flowing N ₂ into the solder bath 45.

Next, the mechanism of ultrasonic soldering using the above-described apparatus will be described. First, the solder 4
When a cavity is formed in the surface of the CCD wafer 41 and a pressure loss occurs on the surface of the CCD wafer 41, a natural oxide film on the Al electrode formed on the wafer 41 is destroyed. When the natural oxide film is removed, a eutectic reaction occurs with the formed Al electrode, and a bump is formed. Since no eutectic reaction occurs in a non-metal portion such as a passivation film, there is no adhesion of solder. Therefore, the silicon nitride film 31
There is no solder growth in the area where
On the surface opposite to the side on which D30 is formed, there is no silicon nitride, but there is also silicon growth with a thin natural oxide film, so that no solder grows. The metal bump 32 of FIG. 5B is formed by the above-described method. In the ultrasonic method, a bump having a height of several tens of microns is formed for an Al pattern having a square of 100 microns. However, as the thickness of the underlying Al increases, the height of the formed bump can be increased. It is possible. In addition, as a method for forming a bump, there are other methods such as a vapor deposition method and a plating method, and the height of the formed bump can be changed accordingly.

Since all the processes up to this point are performed in the form of a wafer, there is not much labor required for these operations. Finally, the wafer is divided into individual chips by dicing or the like. FIG. 5B shows the state.

FIG. 5C shows a substrate (auxiliary substrate) for supporting the CCD chip. As the substrate 35, a silicon wafer or glass having the same thermal expansion coefficient as that of a CCD chip is preferable. In this embodiment, a silicon wafer is used. First, a silicon wafer 35 is oxidized to form a silicon oxide film 33 of an appropriate thickness on both upper and lower surfaces, and a wiring 3 of Al or the like is formed on the upper surface.
4 is provided. The wiring 34 indirectly connects the metal bump 32 formed on the CCD chip to an electrode of a package to be mounted later. Thereafter, in order to guard a portion that comes into contact with the silicon etchant, a silicon nitride film 36 is deposited on both upper and lower surfaces, and the silicon nitride film 36 on the upper surface is removed except for the peripheral portion. Thereafter, those shown in FIGS. 5B and 5C are integrated. FIG. 5 (d) shows the CCD chip and the metal wiring 3 via the metal bump 32 formed by the above-described method.
4 shows a state where the silicon wafer 35 subjected to No. 4 is bump-bonded. The side on which the CCD 30 is formed is the abutting surface.

Next, the resin 50 is filled. FIG. 7 (a)
Shows a state in which the resin 50 is filled so that a silicon etchant to be used later does not enter the surface where the CCD chip and the silicon wafer 35 abut. The resin 50 is, for example, Kayatron M manufactured by Nippon Kayaku Co., Ltd.
L-230P. The curing of the resin 50 is performed by heat treatment. As described above, most resins generate compressive stress during curing. However, in this embodiment, since the CCD light receiving portion is not yet thinned, the compressive stress is decomposed to the entire CCD chip, and is applied to the light receiving surface after the thinning. It does not crack or crack. The characteristics required of the resin are that it is non-conductive, withstands the etchant used in the subsequent process, does not contain an alkali metal, etc. Maintaining good contact and enduring heat of about 150 ° C. during die bonding and wire bonding.

Next, the second wafer 27 is etched. FIG. 7B shows a state in which the structure formed in FIG. 7A is immersed in an etchant, and a portion of silicon corresponding to the light receiving surface is etched and thinned. At this time,
The region where the silicon nitride film 31 is formed is not etched because the silicon nitride film 31 functions as a mask.
The composition of the etchant used here is, for example, HF: HN
It is an acid-based etchant such as O ₃ : CH ₃ COOH = 1: 3: 8 or an alkali-based etchant of 8N KOH: H ₂ O: isopropyl alcohol = 950 ml: 1150 ml: 700 ml. In this embodiment, the case where an alkaline etchant is used will be described. The etchant must be heated to 78 ° C., and the CCD 30 bump-bonded to the substrate 35 must be rotated so as to revolve around itself to remove bubbles generated on the etched surface. If the bubbles are not sufficiently removed, there is a possibility that the etched surface becomes rough and the film thickness becomes uneven. The etch rate is
Approximately 0.6 μm / min is obtained. The film thickness of the alkaline etchant is relatively uniform due to anisotropic etching. However, in the case of a back-side illuminated CCD, there is a possibility that the reproducibility of a slight film thickness between chips may be poor, or variation within a chip may occur. Here is a solution to this problem.

The selectivity of the silicon oxide film to silicon with respect to the alkaline etchant is about 1/200. As described above, the oxide film 26 is a bonding surface. Therefore, even if the etching is advanced with an alkaline etchant and the film thickness becomes somewhat non-uniform on the way, the etching automatically stops when the oxide film 26 is reached. 1
If the thickness of the wafer 24 is controlled tightly, the thickness of the light-receiving surface after the etching becomes very uniform between and within the chips. That is, the silicon oxide film 26 on the bonding surface can be used as an etching stopper.

FIG. 7B shows a state in which the etching has been completed. Here, it is not recommended to remove the entire silicon oxide film 26 except for special uses.

When the etching is completed, the silicon nitride film 36 deposited on the surface of the substrate 35 is removed, and the metal wiring 34 is exposed on the surface.

The importance of the accumulation of the light receiving surface on the back surface has been described above. In the stage of FIG.
Impurities are diffused into the first wafer 24 via 6 to form the high-concentration impurity regions 28, which helps to bring the light receiving surface into an accumulation state. That is, this structure does not require a process for creating a new accumulation state.

The potential profile with respect to the photocharge is formed so as to gradually decrease from the light-receiving surface toward the CCD according to the impurity profile shown in FIG.
D potential well can be reached. That is, the sensitivity to short-wavelength light can be increased and stabilized.

Next, the above elements are mounted. FIG. 7 (c)
A package 38 such as a ceramic
And a state where the substrate 35 and the package 38 are connected by bonding 39.

Previously, an example was shown in which an etchant containing an alkali metal such as KOH was used to etch the silicon on the back surface of the CCD. Normally, MOS devices such as CCDs require very high oxide film cleanliness.
Extremely dislikes alkaline ions such as a ⁺ and K ⁺ . However, in the example shown here, when starting the etching, the CCD is already protected by the resin 50 and does not touch the etchant. After that, the tree 50 and the substrate 35 are not separated from the CCD 30.
The surface on which 30 is formed never touches the outside again. In this process, even if an alkali-based etchant is used, the CCD 30 is kept clean and operates reliably.

[0069]

As described above in detail, according to the present invention, a high concentration impurity region is formed on the surface on which the energy beam is incident, so that it is not necessary to perform a new backside accumulation step, and it is possible to manufacture the device. The yield can be increased. Moreover, since the oxide film formed on the surface on which the energy rays are incident is used as an etching stopper, the thickness of the incident surface can be made uniform.

Therefore, the variation in sensitivity to energy rays between chips and within a chip can be reduced, and the absolute value and uniformity of the thickness of the wafer in the energy ray incident area can be easily determined without contaminating the CCD section. Can be controlled.

As described above, a highly reliable method of manufacturing a semiconductor energy detector can be obtained.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a semiconductor energy detector according to the present invention.

FIG. 2 is a graph showing an impurity profile when boron is used.

FIG. 3 is a graph showing an impurity profile when phosphorus is used.

FIG. 4 is a graph showing an impurity profile when arsenic is used.

FIG. 5 is a process chart showing a method for manufacturing a semiconductor energy detector according to the present invention.

FIG. 6 is a schematic sectional view of an ultrasonic soldering apparatus.

FIG. 7 is a process chart showing a method for manufacturing a semiconductor energy detector according to the present invention.

FIG. 8 is a top view showing a configuration of a full frame transfer system.

FIG. 9 is a sectional view showing a main part of the full frame transfer method.

FIG. 10 is a diagram showing a readout circuit diagram and a clock pulse output waveform.

FIG. 11 is a view showing a conventional backside illumination type detector.

FIG. 12 is a diagram showing a potential profile of a conventional backside illumination type detector.

[Explanation of symbols]

24 ... first wafer, 25 ... substrate, 26 ...
Silicon oxide film, 27 second wafer, 28 high concentration impurity region, 29 metal wiring, 30 CCD, 31 silicon nitride film, 32 metal bump, 33 silicon oxide film, 34 metal wiring, 35 … Silicon wafer, 36…
Silicon nitride film, 38 package, 39 bonding, 41 CCD wafer, 42 ultrasonic transducer, 43
... solder, 44 stirrer, 45 solder bath, 50 resin.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/14 G01J 1/02 H01L 27/12 H01L 31/09

Claims (5)

(57) [Claims] 1. A method of manufacturing a semiconductor energy detector in which an energy ray is incident from the back surface of a semiconductor thin plate, comprising: a first silicon wafer having a low impurity concentration; and a high impurity concentration having the same conductivity type as the first silicon wafer. A first step of bonding and integrating the second silicon wafer by heat treatment via a silicon oxide film; and arranging a plurality of charge transfer elements on a surface opposite to a bonding surface of the first silicon wafer. A second step of forming a charge readout portion, and etching is started from a surface opposite to the bonding surface of the second silicon wafer to expose a silicon oxide film on the bonding surface, thereby detecting semiconductor energy. And a third step of forming an element. 2. The method according to claim 1, wherein the first and second silicon wafers, on which the charge readout portions are integrally formed, are provided on an auxiliary substrate formed in advance between the second and third steps. The method for manufacturing a semiconductor energy detector according to claim 1, further comprising a step of connecting via a metal bump, filling a resin between the first and second silicon wafers and the auxiliary substrate and curing the resin. 3. The method of manufacturing a semiconductor energy detector according to claim 1, wherein the second silicon wafer has a high impurity concentration at least on the bonding surface side. 4. The method according to claim 1, wherein an alkaline etchant is used when etching the second silicon wafer. 5. The method for manufacturing a semiconductor energy detector according to claim 1, wherein said first silicon wafer is formed by epitaxial growth.