JP3265181B2 - Clock distribution circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock distribution circuit for distributing an input clock signal to each constituent circuit in an integrated circuit chip.

[0002]

2. Description of the Related Art As described above, in order to distribute an input clock signal to each constituent circuit in an integrated circuit chip, a typical prior art employs, for example, "Introduction to LSI Design" (Sasaki,
As shown in Morino and Suzuki, Corona Co., pp. 154 to 155), a method of supplying inverters arranged in a tree is used. FIG. 6 is a block diagram showing an electrical configuration of the clock distribution circuit 1 disclosed in Japanese Patent Application Laid-Open No. 5-159080, which is such a typical prior art.

The clock signal CK input to the input terminal 2
Are connected via a CMOS (complementary metal oxide semiconductor) inverter B1 to a plurality of inverters B21, B in the next stage.
22, B23 (when collectively referred to as B below). Each inverter B21, B22, B2
3 have the same characteristics, and the wiring length from the inverter B1 to each of the inverters B21, B22, B23 is also equal to each other.

In this way, inverters B1 and B
21 is output clock signal C which is inverted and output by
In the path of K1, the gate delay time of the inverters B1 and B21, the gate delay time of the inverters B1 and B22 in the path of the output clock signal CK2, and the gate delay time of the inverters B1 and B23 in the path of the output clock signal CK3 are: They are configured to be equal to each other.

Accordingly, each of the inverters B21, B2
2 and B23 output clock signals CK1, CK2 and CK3 output to output terminals P1, P2 and P3 respectively.
The timing difference called clock skew is suppressed, and the phases match each other. Each of the output clock signals CK1, CK2, CK3 is connected to output terminals P1, P
2 and P3, respectively.

On the other hand, one inverter B21, B22,
There is a limit to the load capacity that can be driven by B23. In an integrated circuit that is realized by an ASIC or the like and performs digital signal processing by clock synchronization, the clock distribution shown in FIG. Circuit 11
As shown by, this is dealt with by increasing the number of stages of the inverter B.

In the clock distribution circuit 11, in order to increase the number of output channels, each of the inverters B21, B
22 and B23, three inverters B31, B32, and B33; B34, B35, and B36;
B37, B38 and B39 are provided, and an inverter B0 for phase adjustment is provided before or after the inverter B1 (in the example shown in FIG. 7) corresponding to this. In this manner, the output clock signal C with reduced clock skew is supplied from the many output terminals P1 to P9 to the load circuit.
K1 to CK9 are output respectively.

[0008]

In the above prior art, as the number of load circuits to which a clock signal is to be input increases, that is, as the circuit scale of an integrated circuit increases, the number of clock tree stages increases. There is a problem that the internal delay of the clock signal in the integrated circuit becomes large, and the clock signal becomes unsuitable for high-speed operation. For example, there may be hundreds to thousands of load circuits such as registers.

Further, it is difficult to make the wiring lengths between the inverters B21 to B23 and B31 to B39 of each stage uniform, respectively, and the transmission delay time of the clock signal by the wirings varies, thereby reducing the clock skew. There is a problem that it becomes difficult. There is also a problem that the transmission delay time is further increased due to an increase in wiring resistance due to miniaturization of a process even if the wiring length is the same.

An object of the present invention is to provide a clock distribution circuit capable of reducing the internal delay of a clock signal and reducing clock skew.

[0011]

According to a first aspect of the present invention, a clock distribution circuit is connected in parallel with a clock transmission circuit for converting a voltage level of an input clock signal into a current level. receiving the output current level, viewed contains a plurality of the clock receiving circuit which converts and amplifies the voltage level specified in the output clock signal, the click
A lock transmitting circuit is responsive to the input clock signal.
Cascaded first and second two-stage C
A MOS inverter, wherein the clock receiving circuit comprises:
Detect the output current difference of each CMOS inverter and convert it to voltage difference
A current detection type sense amplifier for conversion and an increase in the voltage difference.
Voltage differential amplifier and the output clock signal
And a waveform shaping circuit for shaping the voltage to a predetermined voltage level .

According to the above configuration, when a clock signal is distributed by a buffer constituted by an inverter or the like, in order to invert the logic of the buffer, it is necessary to move sufficient charges to change the input voltage. On the other hand, in the present invention, before reaching the voltage change, each clock receiving circuit detects a change in the current from the clock transmitting circuit, inverts the logic, and outputs the inverted signal.

Therefore, the influence of the load capacitance of the wiring and the like is small, and each clock receiving circuit quickly detects a change in the output current from the clock transmitting circuit and inverts the logic at the same time. The delay time can be reduced, clock skew can be suppressed, and high-speed operation can be performed.

[0014]

[0015] According to the above configuration, from each of the CMOS inverters of two stages of the clock transmission circuit, to each clock receiver circuit via a sense line, the voltage level of the input clock signal, i.e. the level corresponding to a logical Will be output.

Therefore, in the clock receiving circuit, it is only necessary to determine which current level of the two sense lines is higher or lower by the sense amplifier.
The movement of the charge can be detected quickly.

[0017] Furthermore in the clock distribution circuit according to the invention of claim 2, wherein the first CMOS inverter, a source connected to the high potential power supply, said input clock signal is input to the gate, drain serves as the output terminal First MOS
A second MOSFET having a source connected to a low-potential power supply, a gate to which an input clock signal is input together with the gate of the first MOSFET, and a drain having an output terminal together with the drain of the first MOSFET; The second CMOS inverter has a source connected to a high-potential power supply, an output of the first CMOS inverter input to a gate, and a third transistor having a drain serving as an output terminal.
An OSFET, a source connected to a low potential power supply, and a gate connected to the first CM together with the gate of the third MOSFET.
The output of the OS inverter is input and the drain is the third
A fourth MOSFET serving as an output terminal together with the drain of the MOSFET, and the sense amplifier has a fifth MOSFET whose source is connected to a high-potential power supply and whose gate is connected to a low-potential power supply; Sixth MOSFE connected to a potential power supply and having a gate connected to the low potential power supply
T, a seventh MOSFET having a source connected to the drain of the fifth MOSFET and receiving the output of the first CMOS inverter, and a source having the sixth MOS.
An eighth MOSFET connected to the drain of the FET and receiving the output of the second CMOS inverter, a source connected to a low-potential power supply, and a gate together with a drain and a drain of the seventh MOSFET;
A ninth MOSFET connected to the gate of the FET, a source connected to the low potential power supply, and a gate together with the drain, the drain of the eighth MOSFET and the seventh MO.
And a tenth MOSFET connected to the gate of the SFET, wherein the voltage differential amplifier has an eleventh MOSFET having a source connected to the high potential power supply and a gate connected to the drain.
An SFET, a twelfth MOSFET having a source connected to the high potential power supply, a gate connected to the gate and drain of the eleventh MOSFET, and a drain connected to the first MOSFET.
Drain and gate of the first MOSFET and the twelfth M
The gate of the OSFET is connected to the gate of the OSFET.
And a thirteenth MOSFET to which an output from the drain of the ninth MOSFET is input, and a drain connected to the twelfth MOSFET.
The fourteenth MOSFET is connected to the drain of the MOSFET and the gate receives the output from the drains of the eighth and tenth MOSFETs. The source is connected to the low-potential power supply, and the gate is connected to the high-potential power supply. And the drain is the source of the thirteenth MOSFET and the fourteenth MOSFET.
Fifteenth MOSF connected to the source of MOSFET
ET, the waveform shaping circuit has a source connected to a high-potential power supply, and a gate connected to the twelfth and fourteenth MOs.
Sixteenth M to which the output from the drain of the SFET is input
The OSFET and the source are connected to a low potential power supply, and the gate is connected to the twelfth MOSFET together with the gate of the 16th MOSFET.
And a seventeenth MOSFET to which an output from the drain of the fourteenth MOSFET is inputted, and an output clock signal is derived from the drains of the sixteenth and seventeenth MOSFETs.

According to the above configuration, each configuration of the clock transmission circuit and the clock reception circuit can be specifically configured on an integrated circuit.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 5.

FIG. 1 is a block diagram showing a schematic configuration of a clock distribution circuit 21 according to an embodiment of the present invention. The clock distribution circuit 21 is a clock drive circuit D, which is a clock transmission circuit, and a clock reception circuit, and a plurality of n-channel clock receive circuits R1, R2,. (Referred to as R below).

The clock drive circuit D has an input terminal 22
Voltage level of the input clock signal CK, that is, the current level C of the two sense lines L1 and L2 corresponding to the logic level.
1 and C2 are complementarily changed to perform voltage-current conversion. That is, for example, when the input clock signal CK is at a high level, the current level C1 of the sense line L1 is made higher than the current level C2 of the sense line L2, whereas when the input clock signal CK is at a low level. , The current level C1 of the sense line L1 is made smaller than the current level C2 of the sense line L2.

A clock receiving circuit R is connected in parallel to each of the sense lines L1 and L2. Each clock receiving circuit R performs a current-voltage conversion in the opposite manner to the clock driving circuit D, A voltage level corresponding to the difference between the current levels C1 and C2 of the lines L1 and L2 is output to corresponding output terminals T1 to Tn (hereinafter collectively referred to as T). That is, for example, when the current level C1 of the sense line L1 is higher than the current level C2 of the sense line L2, a high-level output is derived, and when the current level C1 of the sense line L1 is lower than the current level C2 of the sense line L2, the output is low. Derive the level output.

FIG. 2 is an electric circuit diagram showing a specific configuration of the clock drive circuit D. The clock drive circuit D includes first and second two-stage inverters INV
1 and INV2 are connected in cascade. The inverter INV1 includes a P-channel MOSFET Q1 and an N-channel MOSFET Q1.
This is a CMOS inverter having a channel MOSFET Q2.

The source of the MOSFET Q1 is connected to a power supply line 23 of high level + VDD, for example, 3V, which is a high potential power supply.
The source of Q2 is connected to a ground line which is a low potential power supply. An input clock signal CK to the input terminal 22
Are commonly input to the gates of the MOSFETs Q1 and Q2, and the drains of these MOSFETs Q1 and Q2 output the sense line L1 and the inverter INV2 at the subsequent stage.
, The current level C1 is output. These MOS
The FETs Q1 and Q2 are formed so that their driving capabilities are equal to each other.

Therefore, when the voltage level of the input clock signal CK becomes higher than the operating point voltage set to, for example, 1/2 of the voltage VDD, the MOSFET Q1 is turned off, the MOSFET Q2 is turned on, and the current flows from the sense line L1. , The sense line L1 is at a low level substantially equal to the ground level. On the other hand, the input clock signal C
When K becomes lower than the operating point voltage, the MOSFET Q
1 conducts and the MOSFET Q2 shuts off, causing current to flow out to the sense line L1, and the sense line L1 is almost at the high level of + VDD. Thus, the logic of the input clock signal CK is inverted and output to the sense line L1.

The inverter INV2 includes a P-channel MOSFET Q3 and an N-channel MOSFET Q4.
And the same configuration as that of the inverter INV1. However, the output of the current level C1 from the inverter INV1 is input to the gates of the MOSFETs Q3 and Q4, and the output of the current level C2 from the drain is Output to sense line L2.

FIG. 3 is an electric circuit diagram showing a specific configuration of the clock receiving circuit R1. The clock receiving circuit R1 is generally provided with a sense amplifier 31, a voltage differential amplifier 32, and a waveform shaping circuit 33.

The sense amplifier 31 has a P-channel M
OSFET Q5 to Q8 and N-channel MOSFET Q
9, Q10. A pair of MOSF
The sources of ETQ5 and Q6 are high level + VD
D is connected to the power supply line 34, and the gate is commonly connected to the ground line. Therefore, these MOSF
The ETs Q5 and Q6 are always conductive and output a constant current from the drain. The drains of the MOSFETs Q5 and Q6 are connected to the sources of the MOSFETs Q7 and Q8, respectively, and the connection points thereof are connected to the sense lines L1 and L2, respectively. MOSFET Q7
Is connected to the drain and gate of MOSFET Q9 and the gate of MOSFET Q8. The drain of MOSFET Q8 is connected to MOSFET Q1.
0 and the gate of MOSFET Q7. The drains of the MOSFETs Q9 and Q10 are each connected to a ground line.

The MOSFETs Q5 and Q6 are always conducting as described above, and therefore, the MOSFETs Q7 and Q8
The same current flows into the sources. On the other hand, the current flowing from the sense lines L1 and L2 or the current flowing to the sense lines L1 and L2 causes
A potential difference occurs between the drain of TQ7 and the drain of MOSFET Q8. More specifically, for example, when the input clock signal CK at which the sense line L1 goes low and the sense line L2 goes high is at a high level, the drain current of the MOSFET Q5 is sucked out to the sense line L1, and the drain current of the MOSFET Q6 is , The current from the sense line L2 is added. Therefore, the source potential of MOSFET Q8 is MO
It becomes higher than the source potential of the SFET Q7, and these potentials are output from the drains of the MOSFETs Q8 and Q7 to the lines L12 and L11, respectively.

The voltage differential amplifier 32 includes P-channel MOSFETs Q11 and Q12 and an N-channel MOSFET.
ETQ13, Q14, and Q15 are provided. The source of MOSFET Q11 is high level + VD
D is connected to the power supply line 35, and the gate is connected to the drain of the MOSFET Q13 together with the drain. On the other hand, the source of the MOSFET Q12 forming a pair with the MOSFET Q11 is connected to the power supply line 35, the gate is connected to the gate and drain of the MOSFET Q11, and the drain is
14 and a line L13 for leading an output. The gates of the MOSFETs Q13 and Q14
The MOSF is connected via lines L11 and L12, respectively.
The source potentials of the ETQ7 and Q8 are input, and the sources are commonly connected to the drain of the MOSFET Q15. The gate of the MOSFET Q15 is connected to a high-level + VDD power supply line 36, and the source is connected to a ground line. Therefore, MOSFET
Q15 is always conductive and MOSFETs Q13, Q14
A constant current will be drawn from the source.

When the input clock signal CK at which the line L11 goes high and the line L12 goes low is at a low level, the MOSFET Q13 is turned on and the MOSFET Q14 is turned off.
TQ11 and Q12 are conducting, so that line L
A high level is output to the waveform shaping circuit 33 via the line 13. On the other hand, when the line L11 is at a low level and the line L12 is at a high level, the input clock signal CK is at a high level.
The SFET Q14 conducts, and the MOSFETs Q11 to Q13
Is cut off, and the line L13 goes low. In this manner, the voltage differential amplifier 32 amplifies the source potential difference to an electric power that can sufficiently drive the load circuit and outputs the amplified electric power.

Further, similarly to the inverters INV1 and INV2, the waveform shaping circuit 33 includes a P-channel MO.
It comprises an SFET Q16 and an N-channel MOSFET Q17. MOSFET Q16, Q17
Are connected to a power supply line 36 and a ground line, respectively, and the gate is commonly connected to the line L1.
3, the output of the voltage differential amplifier 32 is input, and the output clock signal CK is commonly sent from the drain to the output terminal T1.
1 will be output. The remaining clock receiving circuits R2 to Rn are configured in the same manner as the clock receiving circuit R1.

FIGS. 4 and 5 show the experimental results of the present inventor. FIG. 4 shows an example of the clock distribution circuit 21 according to the present invention, in which the horizontal axis shows the elapsed time after the input clock signal CK is input to the clock drive circuit D, and the vertical axis shows the output voltage from the clock receive circuit R. Is shown. In FIG. 4, reference numerals α1, α2 and α3 indicate the case where the lengths of the sense lines L1 and L2 are 1 mm, 2 mm and 3 mm, respectively. As is apparent from FIG. 4, the rise time difference W between the voltage waveform indicated by the reference numeral α3 having the longest wiring length and the voltage waveform indicated by the reference numeral α1 having the shortest wiring length is 0.
04 (nsec).

On the other hand, in the clock distribution circuit 1 of the prior art shown in FIG.
The wiring length between the inverters B21, B22 and B23 is
Similarly to the above, the voltage waveforms of the output clock signal at 1 mm, 2 mm, and 3 mm are denoted by reference numerals α1a, α2a, and α2a, respectively.
It is indicated by α3a. The time difference Wa between the voltage waveform indicated by the reference symbol α1a having the shortest wiring length and the voltage waveform indicated by the reference symbol α3a having the longest wiring length is 0.17 (nsec).
It has become.

Accordingly, it is understood that clock skew is significantly reduced.

As described above, in the clock distribution circuit 21 according to the present invention, the change in the voltage of the input clock signal CK is converted into the change in the current level of the two sense lines L1 and L2 by the clock drive circuit D. The sense amplifier 31 converts the current level difference into a potential difference to generate a voltage differential amplifier 32 and a waveform shaping circuit 33.
Amplify the output clock signals CK1-C
Since it is output as Kn, it is not affected by the load capacitance of the sense lines L1 and L2, and therefore, even if the wiring lengths of the sense lines L1 and L2 to each clock receiving circuit R are different from each other, the transmission delay of the clock signal is different. Reduce the time,
In addition, clock skew can be reduced, and high-speed operation of an integrated circuit on which the clock distribution circuit 21 is mounted can be enabled. As described above, the clock according to the present invention
Circuit distributes the voltage level of the input clock signal to the current
And the clock transmission circuit that converts the
Receiving the output current level of the clock transmission circuit.
And amplifies it to the voltage level specified by the output clock signal.
And a plurality of clock receiving circuits for converting
You. According to the above configuration, it is configured by an inverter, etc.
When the clock signal is distributed by the buffer
Has sufficient charge to invert the logic of the buffer.
While it is necessary to move and change the input voltage,
In the present invention, before the voltage change, the clock transmission
Each clock receiving circuit detects the change in current from the path,
Outputs the logic inverted. Therefore, load capacity such as wiring
The effect of the amount is small, and each clock receiving circuit
Changes in the output current from the
The logic is inverted, and the internal delay of the clock signal is
The time can be reduced and the clock
Queues can be suppressed and high-speed operation can be performed.
Become like

[0037]

As described above, the clock distribution circuit according to the first aspect of the present invention converts a voltage level of an input clock signal into a current level and transmits it from the clock transmission circuit, and is provided for each load circuit. A clock receiving circuit receives the current level, amplifies the current level to a voltage level defined by an output clock signal, and converts the voltage level. In addition, the clock transmission
The communication circuit is composed of a two-stage CMOS inverter,
Input clock signal to each clock receiving circuit
Signal level, that is, the current level corresponding to the logic
The clock receiving circuit is configured to output the difference
Detect the output current difference of MOS inverter and convert it to voltage difference
And a current detection type sense amplifier for amplifying the voltage difference.
Voltage differential amplifier and the voltage specified by the output clock signal.
And a waveform shaping circuit for shaping to a pressure level.

Therefore, each clock receiving circuit quickly detects a change in the output current from the clock transmitting circuit and inverts the logic at the same time. The delay time can be reduced, clock skew can be suppressed, and high-speed operation can be performed.

[0039]

Further , in the clock receiving circuit, it is only necessary to determine which current level of the two sense lines is higher or lower by the sense amplifier, and the movement of the electric charge can be detected promptly.

[0041] Furthermore clock distribution circuit according to a second aspect of the invention, as described above, the first CMOS inverter constituted by the first and second MOSFET, said second CMOS inverter 3 and Fourth MOSFE
T, and the sense amplifier is a fifth to tenth MOS.
FETs, and the voltage differential amplifier is composed of
And the waveform shaping circuit is composed of sixteenth and seventeenth MOSFETs.

In this way, each configuration of the clock transmission circuit and the clock reception circuit can be specifically configured on the integrated circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a clock distribution circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a specific configuration of a clock drive circuit in the clock distribution circuit.

FIG. 3 is an electric circuit diagram showing a specific configuration of a clock receiving circuit in the clock distribution circuit.

FIG. 4 is a graph showing experimental results of the present inventor on characteristics of a clock distribution circuit according to the present invention.

FIG. 5 is a graph showing experimental results by the present inventor on characteristics of a typical prior art clock distribution circuit.

FIG. 6 is a block diagram showing an electrical configuration of a typical conventional clock distribution circuit.

FIG. 7 is a block diagram showing an electrical configuration of another conventional clock distribution circuit.

[Explanation of symbols]

 Reference Signs List 21 clock distribution circuit 22 input terminal 23 power supply line (high potential power supply) 31 sense amplifier 32 voltage differential amplifier 33 waveform shaping circuit 34 power supply line (high potential power supply) 35 power supply line (high potential power supply) 36 power supply line (high potential power supply) D) clock drive circuit (clock transmission circuit) L1 sense line L2 sense line Q1 first MOSFET Q2 second MOSFET Q3 third MOSFET Q4 fourth MOSFET Q5 fifth MOSFET Q6 sixth MOSFET Q7 seventh MOSFET Q8 eighth MOSFET Q9 ninth MOSFET Q10 tenth MOSFET Q11 eleventh MOSFET Q12 twelfth MOSFET Q13 thirteenth MOSFET Q14 fourteenth MOSFET Q15 fifteenth MOSFET Q16 sixteenth M OSFET Q17 Seventeenth MOSFET R Clock receiving circuit (clock receiving circuit) T Output terminal

Claims (2)

(57) [Claims] A voltage level of an input clock signal is set to a current level.
A clock transmitting circuit for converting the clock signal into a clock signal and an output power of the clock transmitting circuit.
Current level and the voltage specified in the output clock signal
Multiple clock receiver circuits that amplify and convert to a level
Wherein the clock transmission circuit corresponds to the input clock signal.
Cascade-connected first and second 2
And a clock receiving circuit, each of which includes an output of each CMOS inverter.
Current detection type sense that detects current difference and converts it to voltage difference
An amplifier; a voltage differential amplifier for amplifying the voltage difference;
To the voltage level specified by the output clock signal
Features and to torque lock distribution circuit that comprises a waveform shaping circuit. 2. The method according to claim 1, wherein the first CMOS inverter has a source.
Is connected to a high-potential power supply, and the input clock signal is
Signal is input, and a first MOSF having a drain as an output terminal
ET, the source is connected to a low potential power supply, and the gate is
Input clock signal with gate of first MOSFET
And the drain is the drain of the first MOSFET.
And a second MOSFET serving as an output terminal
The source of the second CMOS inverter is a high-potential power supply.
And the gate of the first CMOS inverter
A third MOS to which an output is input and a drain is an output terminal
The FET and source are connected to a low potential power supply, and the gate is
The first CMOS together with the gate of the third MOSFET
The output of the inverter is input, and the drain is connected to the third M
Fourth MO that becomes an output terminal together with the drain of the OSFET
And an SFET, wherein the sense amplifier has a source connected to a high potential power supply,
Fifth MOSFET whose gate is connected to a low potential power supply
And the source is connected to the high potential power supply and the gate is connected to the low potential power supply.
A sixth MOSFET connected to a source;
5 is connected to the drain of the first MOSFET.
Seventh MOSFE to which the output of the MOS inverter is input
T and the source is connected to the drain of the sixth MOSFET.
Output of the input of the pre-Symbol second CMOS inverter is continued
8th MOSFET and source connected to low potential power supply
The gate is connected to the seventh MOSFE together with the drain.
Connected to the drain of T and the gate of the eighth MOSFET
And the source is connected to the low potential power supply.
The gate is connected to the eighth MOSF together with the drain.
Connects to the drain of ET and the gate of the seventh MOSFET
And a voltage differential amplifier having a source connected to a high potential power supply.
And an eleventh MOSFE having a gate connected to the drain
T, the source is connected to a high potential power supply, and the gate is
Connected to the gate and drain of 11 MOSFETs
A twelfth MOSFET and a drain connected to the eleventh M
OSFET drain and gate and twelfth MOSF
Connected to the gate of the ET.
The output from the drain of the ninth MOSFET is input
A thirteenth MOSFET and a drain connected to the twelfth MO
Connected to the drain of the SFET and the gate
And the output from the drain of the tenth MOSFET is input
14th MOSFET and the source is connected to the low potential power supply
Connected, the gate is connected to the high potential power supply, and the drain is
The source of the thirteenth MOSFET and the fourteenth MO
A fifteenth MOSFET connected to the source of the SFET;
It has the waveform shaping circuit has a source connected to the high potential power supply,
The drains of the twelfth and fourteenth MOSFETs are
A sixteenth MOSFET to which an output from the input is input;
The source is connected to a low potential power supply, and the
12th and 14th together with the gate of the MOSFET
17th to which the output from the drain of the MOSFET is input
16th and 17th MOS
2. The clock distribution circuit according to claim 1 , wherein an output clock signal is derived from a drain of the FET .