JP3123445B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an offset gate formed by offsetting a gate electrode to a source electrode side in a Schottky barrier gate field effect transistor operating in an ultra-high frequency band. It relates to a forming method.

[0002]

2. Description of the Related Art Gallium arsenide field effect transistors (GaAs FETs) and heterojunction type field effect transistors (HJ FETs) for microwave amplification have high performance characteristics in an ultra-high frequency band regardless of whether they are for low noise or power. Because it can be realized, it is widely used for communication equipment and radar equipment.

In such field-effect transistors and heterojunction field-effect transistors, a groove called a recess is provided between a drain electrode and a source electrode in order to improve performance and increase electric breakdown strength. In many cases, a structure in which a gate electrode is provided is adopted.

In the field effect transistor having the recess structure, the series resistance Rs between the source electrode and the gate electrode is:
It depends strongly on the distance between the recess end on the source electrode side and the gate electrode. In particular, for low-noise devices operated with small currents,
The two-dimensional electron gas concentration immediately below the gate electrode is limited low,
The series resistance Rs below the bottom of the recess increases to a degree that largely affects the noise performance of the device. Therefore, it is desirable that the distance between the recess end on the source electrode side and the gate electrode be as short as possible in element design.

On the other hand, the distance between the drain electrode side recess end and the gate electrode depends on the capacitance Cg between the drain electrode and the drain electrode.
In relation to d, when the distance becomes small, this Cgd increases, so that the power gain performance of the element deteriorates during high-frequency operation. When the gate electrode is used as a high-output FET by improving the reverse breakdown voltage and the drain breakdown voltage of the gate electrode, the distance between the recess end on the drain electrode side and the gate electrode is larger than the distance between the recess end on the source electrode side and the gate electrode. It is desirable to design. In this type of field-effect transistor, an offset gate structure provided at a position where a gate electrode is offset in a recess is being studied.

FIGS. 8A to 8D are cross-sectional views in the order of steps for explaining a conventional method of forming an offset gate. First, as shown in FIG. 8A, an insulating film 23 is provided on a GaAs substrate 21 on which an operation layer 20 is provided. Next, after the resist layer 24 is applied, the resist layer 24 is patterned by an optical exposure method so as to have an opening width corresponding to a width of a recess called a so-called recess.

[0008] Next, as shown in FIG.
After etching is removed, etching is performed using the insulating film 23 as a mask to form a recess region 25.

Further, in order to form the gate electrode in the recess so as to be offset to the source side, as shown in FIG. 8C, the resist layer 26 is positioned and patterned.
At this time, since the gate length is limited to about 0.5 μm by a normal optical exposure method, it is necessary to use a means such as electron beam exposure to form a finer pattern.

After opening the resist layer 26, a gate metal is deposited, and a part of the gate metal is removed together with the resist layer 26 using methyl ethyl ketone (this step and method are called lift-off), as shown in FIG. 2D. Then, a gate electrode 27 is formed from the remaining gate metal. In this case, to offset the gate electrode 7 to the source side,
As the alignment accuracy, a high accuracy of about ± 0.02 μm is required. The alignment accuracy of an i-line stepper used for optical exposure and an electron beam exposure machine used for electron beam exposure is as follows:
Both are about ± 0.05 μm, which is insufficient for accurately forming an offset gate.

In order to solve the problem in the conventional example shown in FIG. 8, the following two methods have been proposed.
A conventional example described in JP-A-3-293732 will be described. First, as shown in FIG.
The channel layer 28 and n ⁺ − are formed on the entire surface of the aAs substrate 21.
After forming the conductive layer 29, a pair of ohmic electrodes 30 is formed by AuGe. Subsequently, as shown in FIG. 9B, an insulating film 31 of SiO ₂ is formed on the entire ohmic electrode 30 and the channel layer 28 by a sputtering method.

Next, as shown in FIG. 9C, a part of the insulating film 31 is thinned by an etching method. At this time, the step caused by the partial thinning of the insulating film 31 substantially corresponds to the position of the gate electrode described later.

Next, as shown in FIG. 9D, a resist layer 32 used for finally forming a gate electrode is formed. Here, the resist layer 32 is patterned into a gate electrode pattern, and the gate electrode formation region is formed so as to include the step formed in the insulating film 31 in the previous step.

As described above, by subjecting the substrate 21 loaded with the patterned resist layer 32 to a reactive ion etching process, as shown in FIG.
The insulating film 31 is partially removed. At this time, first, the insulating film 31 is vertically etched in a region where the resist layer 32 is missing, and then the insulating film 31 located below the resist layer 32 is also partially etched by side etching. Select the etching conditions.

As described above, since the insulating film 31 is partially thinned, by performing such etching, in the region where the insulating film 31 is thinned, the side etching proceeds quickly, The etched region of the insulating film 31 is formed asymmetrically with respect to the defective region of the resist layer 32.

Next, using the insulating film 31 asymmetrically etched as described above as a mask, the n ⁺ -conductive layer 29 and the channel layer 28 are etched to obtain a structure shown in FIG.
As shown in (f), a recess 28a corresponding to the defective region of the insulating film 31 is formed.

Finally, by a lift-off method using a resist layer 32, as shown in FIG.
7 is formed. At this time, as described above, the resist layer 32
Since the recess 28a is formed asymmetrically with respect to the defective region, the formed gate electrode 27 is
It is formed offset within a.

Next, a conventional example described in JP-A-5-218090 will be described. As shown in FIG. 10A, a resist in which openings for forming a first insulating film 33, a second insulating film 34, and a first recess are patterned on a GaAs substrate 21 in which an active region is formed. The layer 35 is formed. The first insulating film 33 is made of SiO ₂
A film is used, and a SiN film is used as the second insulating film 34.

Next, as shown in FIG. 10B, after etching the second insulating film (SiN) 34 and the first insulating film (SiO) 33 using the resist layer 35 as a mask,
A first recess 36 is formed. After removing the resist layer 35, as shown in FIG. 10C, an opening is provided in the resist layer 37 so as to be offset in one direction of the first recess 36 (usually on the source electrode side).

After that, as shown in FIG. 10D, a second recess 38 is formed so as to obtain a desired pinch-off voltage or a drain saturation current, and then the first insulating film (wet etching) is formed by wet etching. After the SiO) 33 was side-etched, a gate metal was deposited, and a resist layer 37 was formed.
The gate electrode 27 is formed by a lift-off method utilizing the method (FIG. 4E). The gate length by this forming method depends on the pattern of the resist layer 37 and the second insulating film (SiN) 3.
4.

[0020]

In the prior art shown in FIG. 9, which has been proposed to solve the problem of the prior art shown in FIG. 8 described above, the expected gate formation position is limited to the alignment accuracy of the exposure process. And the offset amount within the wafer varies, resulting in poor reproducibility.

Further, in the conventional example shown in FIG.
Since the resist is applied to the recess, there is concern about contamination of the bottom surface of the recess.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of realizing an offset structure with high accuracy and high reproducibility without causing contamination of the bottom surface of the recess.

[0023]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an offset gate structure, wherein an active region is formed on a surface of a semiconductor substrate. Forming, and forming a first insulating film defining a recess width on the active region, depositing a second insulating film on the semiconductor substrate,
Covering the first insulating film, forming a resist layer on the second insulating film, and forming an opening in the resist layer including a boundary between the first insulating film and the second insulating film. Process and
Said resist layer as a mask, etching the second insulating film to the first insulating film is exposed, and a depth not Kira disconnect the second insulating film, d for the first insulating film
Etching rate for the second insulating film
After selectively removing the first insulating film using Toyori large etchant, forming a recess by selectively etching the active region exposed the second insulating film as a mask, the active region And depositing a conductive film forming a Schottky junction in the recess to form a gate electrode.

Further, the first insulating film and the second insulating film are
These are a silicon oxide film and a silicon nitride film, respectively.

Further, the first insulating film and the second insulating film are
Each is etched by a dry etching method and a wet etching method.

[0026]

According to the present invention, two different types of insulating films are formed below a resist layer provided with a gate opening. An offset gate electrode is formed by making the substrate surface exposed to the gate opening asymmetric by utilizing the difference in etching rate between the two types of insulating films.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) First, Embodiment 1 of the present invention
A method for manufacturing a semiconductor device according to the first aspect will be described.

FIGS. 1 (a) and 1 (b) and FIGS.
As shown in FIG. 2B, an operation layer 2 made of an n-type GaAs layer is formed on the surface of a semi-insulating GaAs substrate 1.
Is patterned to form a mesa having a rectangular planar shape. Next, a first insulating film 3 such as a silicon oxide film having a thickness of 50 nm is deposited by a plasma CVD method,
Using the resist layer 4 as a mask, wet etching is performed with an HF-based etchant to partially dispose the first insulating film 3 on the operation layer 2. The first insulating film 3 defines a width of a recess 9 described later.

Next, as shown in FIGS. 3 (a) and 3 (b),
A second insulating film 5 such as a silicon nitride film having a thickness of 100 nm is deposited on the GaAs substrate 1 by a CVD method. Thereby, different types,
That is, the insulating films 3 and 5 having different etching rates are laminated and formed in two layers.

Next, as shown in FIGS. 4A and 4B,
A resist layer 6 is formed on the second insulating film 5, and a resist opening 7 is formed by i-line exposure. At this time, the resist opening 7 is formed so as to partially overlap the edge of the first insulating film 3 partially arranged on the operation layer 2. Edge of insulating film 3 and resist opening 7 arranged on operation layer 2
The gate length is determined at the edge of.

Next, as shown in FIGS. 5A and 5B,
Using the resist layer 6 provided with the resist opening 7 as a mask, the second insulating film 5 is dry-etched with a CF ₄ / H ₂ gas, for example, to form a gate opening 8. At this time, the etching amount of the second insulating film 5 is, for example, 130 nm so that the second insulating film 5 is not completely removed and a part of the first insulating film 3 is exposed. This allows
Step 5 a is formed in second insulating film 5.

Next, as shown in FIGS. 6A and 6B,
A first insulating film 3 such as a silicon oxide film partially disposed on the operation layer 2 has a higher etching rate than an insulating film 5 such as a silicon nitride film, such as HF. It is removed by a wet etching method using an etchant. The operating layer 2 exposed by the removal of the first insulating film 3 is made of H ₂ SO ₄ and H ₂ O ₂
To form a recess 9.

Next, as shown in FIGS. 7A and 7B,
Using the resist layer 6 as a mask, a gate metal forming a Schottky connection with GaAs is deposited on the operation layer 2 by vapor deposition, a part of the gate metal is removed together with the resist layer 6 using methyl ethyl ketone, and the remaining gate metal is used as a gate. The electrode 10 is formed.

In the first embodiment, the edge of the first insulating film 3 which has been partially disposed must be located below the resist opening 7, but the alignment accuracy of the i-line stepper is ±. When the resist opening 7 is exposed to 0.5 μm or more, there is a sufficient margin. The relative positional relationship between the junction surface of the gate electrode on the source side and the recess is not the alignment accuracy of the exposure machine,
It is determined by the etching amount for forming the recess 9. The etching accuracy is ± 0.0
It is about 2 μm, and the accuracy is higher than that of the method of forming by registration (the conventional example in FIG. 8).

(Embodiment 2) Next, Embodiment 2 of the present invention
A method for manufacturing a semiconductor device according to the first aspect will be described.

The difference from the first embodiment will be described.
In the second embodiment, a low dielectric constant film based on a cyclic olefin-based resin, for example, a polyolefin film having a thickness of 100 nm is formed as the second insulating film 5, and a gate opening 8 is provided by photolithography. Subsequent steps are the same as in the first embodiment. The polyolefin film is not etched by the HF-based etchant. Since the dielectric constant of silicon nitride is 5 and the dielectric constant of the polyolefin film is as low as 2.4, the gate parasitic capacitance can be further reduced.
Assuming that the cutoff frequency is 20 GHz, 30 GHz
Can be improved to the extent.

In the above embodiment, the case where GaAs is used as the semiconductor material has been described.
The present invention can also be applied to a device using another semiconductor material used as an FET, such as InGaAs or InGaAs.

In the above embodiment, the gate electrode 1
Since 0 is in contact with the step 5a of the second insulating film 5 and in contact with the operation layer 2, there is an advantage that the resistance value can be suppressed low.

[0040]

As described above, according to the present invention, the surface of a semiconductor is covered with a first insulating film having a first opening,
Depositing a second insulating film having a small etching rate, forming a resist opening shifted from the first opening, forming a gate opening in the second insulating film using the resist layer as a mask, A recess is formed in the semiconductor substrate exposed by removing the insulating film, and further a gate electrode is formed, so that the gate electrode can be provided with an offset with respect to the recess, and the gate electrode is formed with the first insulating film. No contact and second
Can be formed so as to contact only one side with the insulating film.

[Brief description of the drawings]

FIG. 1A is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a cross-sectional view taken along line XX ′ of FIG.

FIG. 2A is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a cross-sectional view taken along line XX ′ of FIG.

FIG. 3A is a plan view for explaining a method of manufacturing a semiconductor device according to the embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a cross-sectional view taken along line XX ′ of FIG.

FIG. 4A is a plan view for explaining a method for manufacturing a semiconductor device according to the embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a cross-sectional view taken along line XX ′ of FIG.

FIG. 5A is a plan view for explaining a method for manufacturing a semiconductor device according to the embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a cross-sectional view taken along line XX ′ of FIG.

FIG. 6A is a plan view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a cross-sectional view taken along line XX ′ of FIG.

FIG. 7A is a plan view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a cross-sectional view taken along line XX ′ of FIG.

FIG. 8 is a sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example in the order of steps.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example in the order of steps.

FIG. 10 is a sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 GaAs substrate 2 working layer 3 first insulating film 4 resist layer 5 second insulating film 6 resist layer 7 resist opening 8 gate opening 9 recess 10 gate electrode

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device having an offset gate structure, comprising: forming an active region on a surface of a semiconductor substrate; and forming a first insulating film defining a recess width on the active region. Performing a step of: depositing a second insulating film on the semiconductor substrate and covering the first insulating film; forming a resist layer on the second insulating film; Forming an opening including the boundary with the second insulating film in the resist layer; using the resist layer as a mask, the first insulating film is exposed, and to a depth that does not cut out the second insulating film. A step of etching the second insulating film, and an etching rate for the first insulating film is set to the second insulating film.
Use etchant larger than etching rate for
After the first insulating film is selectively removed it is, eggplant and forming a recess by selectively etching the active region exposed the second insulating film as a mask, the active region and the Schottky junction Depositing a conductive film in the recess to form a gate electrode. 2. The method according to claim 1, wherein the first insulating film and the second insulating film are a silicon oxide film and a silicon nitride film, respectively. 3. The method according to claim 1, wherein the first insulating film and the second insulating film are etched by a dry etching method and a wet etching method, respectively.