JP3118562B2 - Superconducting integrated circuit structure and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting integrated circuit structure comprising a superconducting integrated circuit and a substrate supporting the same, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a plurality of superconducting integrated circuits are manufactured on a relatively large insulating substrate having a diameter of 3 inches to 4 inches, and then cut into individual chips to individually form "die". And their respective dies are mounted on a support substrate called a "chip carrier".
The chip carrier is mounted on an electronic device by mounting the chip carrier on a printed wiring board or the like. The insulating substrate on which the superconducting integrated circuit is manufactured is often made of silicon, quartz, sapphire, etc., whereas the material of the chip carrier is often ceramics.

In each die, a required number of electrodes for connecting a superconducting integrated circuit formed on the insulating substrate to an external circuit are exposed at a predetermined arrangement on the outermost surface opposite to the insulating substrate. On the other hand, a corresponding number and arrangement of electrode groups are also provided on the already wired chip carrier, and solder bumps are provided on each of them by plating or vapor deposition. Therefore, the die is turned over and placed on the chip carrier, and while the electrodes of the die and the chip carrier are in contact with each other, the solder bumps are melted and then solidified to mount the die on the chip carrier. And can be electrically and physically connected. Generally, such a method is called a flip chip bonding method.

[0004]

However, such a flip chip bonding method requires a special and expensive position control alignment device in order to accurately match the electrodes of the die and the chip carrier with each other. Is an obstacle in reducing the

Further, since the die is turned upside down and mounted on the chip carrier, the back surface of the insulating substrate of the die becomes the front surface of the entire circuit structure, and of course there are no electrodes or the like there. It is not possible to mount a superconducting circuit three-dimensionally by mounting another die on the substrate. If the design dimensions, such as wiring width, are relatively large and small, such as for high-frequency integrated circuits, there is also a technology to pierce the insulating substrate from the back of the die and embed an electrode material that conducts to the superconducting integrated circuit. Not to mention, but conversely, such techniques are too inefficient to manufacture large scale integrated circuits and cannot be applied.

In spite of this, even if some new measures are taken, the technique of simply constructing a superconducting integrated circuit directly on a supporting substrate such as a ceramic substrate serving as a chip carrier is not enough. A problem arises in that the upper wirings are complicated, and the number of wirings required to cope with the higher density cannot be obtained.

[0007]

In order to solve such a problem, the present invention does not require flip-chip bonding, and a plurality of insulating layers overlapping each other so as to cope with high integration density. A three-dimensional wiring laminated substrate structure including a substrate, a wiring pattern is formed on each insulating substrate in advance, and wiring patterns on different insulating substrates are electrically connected by longitudinal connection lines penetrating the insulating substrate. And a superconducting integrated circuit constructed on the three-dimensional wiring laminated substrate structure and electrically connected to the wiring pattern.

The number of superconducting integrated circuits built in the circuit structure of the present invention may be basically one, but if each substrate used for the laminated substrate structure having three-dimensional wiring is large,
The superconducting integrated circuits are independent of each other, and if necessary, after being constructed, are divided into one by one by a mechanical method using a dicing saw or an optical cutting method using a laser together with the underlying laminated substrate. It can consist of several possible pieces.

The present invention can also be considered in terms of a method category. In other words, in the present invention, first, a wiring pattern and a longitudinal connection line penetrating the insulating substrate are formed in advance on each of a plurality of insulating substrates overlapping each other, and then superimposed, and the wiring patterns on different insulating substrates are superposed. A three-dimensional wiring laminated substrate structure having a structure in which the patterns are electrically connected to each other by the vertical connection lines is prepared in advance, and a superconducting integrated circuit electrically connected to the wiring pattern is formed on the three-dimensional wiring laminated substrate structure. A method for manufacturing a superconducting integrated circuit structure characterized by building is also proposed.

[0010] Furthermore, as a more practical invention of a lower aspect, after the above-mentioned three-dimensional wiring laminated substrate structure is manufactured in advance,
A plurality of superconducting integrated circuits are formed on the three-dimensional wiring laminated board structure, each of which is electrically connected to the wiring pattern, and the plurality of superconducting integrated circuits are mutually independent. Also proposed is a method of manufacturing a superconducting integrated circuit structure, characterized in that the structure is divided into individual structures.

The material of the insulating substrate is essentially arbitrary, but is preferably a ceramic material, particularly preferably alumina or alumina nitride. The wiring pattern material and the material of the vertical connection line may be a conductive material, but tungsten or molybdenum is desirable.
Further niobium or niobium compound _{(NbN, Nb 3 Al, Nb} 3 Sn , etc.) superconductor line can be realized by using the.

[0012]

FIG. 1 shows an example of a manufacturing process of a three-dimensional wiring laminated substrate structure used in the present invention, and one structural example of a finally manufactured superconducting integrated circuit structure of the present invention. First, for the former, an appropriate ceramic material, preferably fine powder of alumina nitride or alumina, is prepared and pulverized by a pulverizer for a long time so that the particle size becomes uniform. The obtained powder is dissolved in an organic solvent to form a paste. The sheet is processed into a sheet shape by, for example, a roller-type press, and then punched into a square to make it easy to handle. The diameter is preferably about 3 to 4 inches in terms of the diameter of a square envelope circle.

FIG. 1A shows a ceramic substrate 11 (not yet fired) processed into a sheet as described above, and a via hole is formed at a predetermined position on the ceramic substrate 11. In the future, if multiple boards are laminated in the future, terminals for interconnection of wiring patterns of different boards and connection to external circuits, or on the top layer board if it is The conductive paste 13 serving as a vertical connection line constituting a terminal for electrical connection with a superconducting integrated circuit to be built is filled. As described above, the material of the conductive paste 13 is preferably a high melting point metal such as tungsten (W) or molybdenum (Mo), or a superconducting material having a high melting point, such as niobium or a compound thereof. Here, description is made on the assumption that a high melting point metal is used.

Next, as shown in FIG. 1B, a conductive paste 15 of a high melting point metal is preferably applied in the same manner as described above through a metal mask 14 for obtaining a predetermined wiring pattern. Is removed to obtain a predetermined wiring pattern. At this time, as shown in FIG. 1 (C), a horizontal gap portion (a portion between adjacent wiring patterns 15) formed around the vertical connection line 13 may be left as it is in the space. However, as shown in FIG. 1 (D), it is preferable to fill with an insulating paste 16 of the same material as the substrate 11.

Thus, the wired ceramic substrate
Since one original shape is completed, this process is repeated for a required number of substrates so that a wiring pattern 15 having a predetermined shape and a vertical connection line 13 provided at a predetermined position are formed for each substrate.

Then, a plurality of ceramic substrates 11 prepared in a required number in advance are superimposed in a predetermined order while paying attention to the consistency of the positions of the longitudinal connection lines 13 and temporarily fixed. It is cut into a shape, and if necessary, a corner is chamfered, and then heat treatment is performed to remove the solvent contained in each paste.

After that, it is placed in a high-temperature furnace and fired. If necessary, a mirror polishing of the surface and a flattening step are carried out. As shown in FIG. 1 (E), a plurality of ceramic substrates 11 are laminated. In addition, the three-dimensional wiring laminated board structure 10 in which the wiring patterns 15 provided respectively are electrically connected at predetermined positions by the vertical connection lines 13 is completed.

For convenience, the case shown in the figure shows a case where the number of laminated ceramic substrates 11 is six, and the suffix "-1" to
“-6” is indicated, and among them, the ceramic substrates 11-1 to
The same suffix is attached to each of the wiring patterns 11-5 (in the illustrated case, the wiring pattern is not provided on the uppermost substrate 11-6). However, in the following, when the description is made without any particular suffix, the description is applicable to any substrate or any wiring pattern.

In the case of FIG. 1 (E), the ceramic substrate 11-1 shown at the bottom corresponds to the pattern whose cross section is shown as an example in FIGS. 1 (A) to 1 (D). The wiring pattern 15-1 actually constitutes a ground conductor (opposite conductor) having a microstrip line structure used for signal transmission in a superconducting integrated circuit of this type. Except for the above, it is provided on almost the entire surface of the substrate. The wiring pattern 15 constituting the ground conductor is also provided on every other board 11-3, 11-5, and is provided on the board 11-2, 11-4 sandwiched therebetween. Wiring pattern
15-2 and 15-4 constitute a signal line pattern facing the opposite conductor. The surface of the uppermost substrate 11-6 serves as an underground for directly constructing a superconducting integrated circuit to be described later, and in the illustrated case, a wiring pattern is provided thereon as described above. The end face of the vertical connection line 13 is exposed as a terminal. On the other hand, on the lower surface of the bottom substrate 11-1,
The axial end surface of the vertical connection line 13 is exposed, and can be used as a terminal for connecting to a printed wiring board or the like of an electronic device (not shown). In this regard, there is a technique generally referred to as a ball grid array method, and a technique has been already provided in which solder balls SB are provided in advance on conductive pads 13P periodically provided at points, so that the superconducting integrated circuit of the present invention is provided. It is preferable that such a ball grid array be provided on the lower surface of the lowermost ceramic substrate 11-1 by using this method also in the structure. The exposed end face of the vertical connection line 13 is electrically connected to the corresponding solder ball via any one of the plurality of conductor pads 13P.

On the other hand, in order to construct a microstrip line structure, in view of the not too high line impedance required in this type of superconducting circuit, the thickness of each ceramic substrate 11 cannot be so large. . The line impedance increases in proportion to the distance between the signal line and the opposing conductor, i.e., increases in proportion to the thickness of the ceramic substrate 11 and is inversely proportional to the line width.However, even with the current technology, the ceramic substrate 11 described above has a thickness of 20 μm. A sufficiently thin microstrip line structure can be obtained by adjusting the signal line width and the like. In the future, it is possible to reduce the line width to about 10 μm, so that the line width can be considerably reduced, and the wiring density of the line patterned on one substrate can be sufficiently increased. be able to.

In addition, this point is one of the features of the present invention. However, all the necessary wiring patterns can be shared by a plurality of wiring patterns 15-2 and 15-4 which are in a stacked relationship. Can be connected to each other by the vertical connection line 13 penetrating the substrate between them, so that a complicated and precise wiring pattern can be formed on a relatively large scale for each substrate, and the whole is developed in a plane. As a result, a sufficiently high-density wiring pattern can be obtained while maintaining high productivity and yield.

In the present invention, a superconducting integrated circuit 20 for satisfying a required electronic circuit function is constructed directly on such a three-dimensional wiring laminated substrate structure. In the case of FIG. 1 (E), an example having one Josephson junction JJ and a resistor Rx in one section thereof is shown. Hereinafter, an example of a process of constructing such a superconducting integrated circuit will be described. .

2 (A) and subsequent figures, only the uppermost layer portion of the three-dimensional wiring laminated substrate structure 10 shown in FIG. 1 (E) is shown.
After cleaning the surface of the uppermost ceramic substrate 11-6, preferably by using argon gas plasma, the surface will be connected to the ground plane 21a of the superconducting integrated circuit 20 shown in FIG. The superconducting film 21 serving as the line 21b is deposited by, for example, a sputtering method. Although not limited, here, for convenience, it is assumed that the used superconducting film 21 is niobium (Nb), and the same applies to all superconducting films used in the subsequent steps.

An appropriate etching resist film 22 is formed thereon.
Is attached, and by the known existing lithography technology, FIG. 1 (B)
As shown in FIG. 5, the resist film 22 is patterned and etched so as to leave a portion to be a ground plane 21a and a vertical connection line 21b in the future. At this time, if dry etching is performed using an etching gas such as CF4 or SF4, when alumina nitride or alumina is used as the ceramic substrate 11 as described above, the ceramic substrate material functions as an etching stopper. Ceramic substrate without strict time management
11-6 remains almost unetched.

Next, as shown in FIG.
An insulating film, for example, a SiO ₂ film 23 is deposited on the entire surface of the substrate while leaving 22, and then immersed in an organic solvent, and the resist film 22 and the insulating film 23 thereon are removed by a so-called lift-off method.

As a result, as shown in FIG.
First, a ground plane 21a of the superconducting integrated circuit and a vertical connection line (more precisely, a part thereof) 21b are formed on the uppermost layer of the three-dimensional wiring laminated substrate structure 10, and a horizontal gap between them is an insulating film. It is filled with 23 and becomes insulated. In the following steps, an insulating film selectively used is represented by an SiO ₂ film.

As shown in FIG. 2E, a superconducting film 24 is deposited on the structure by sputtering again, preferably after a surface cleaning treatment with argon gas plasma.

Then, as shown in FIG. 3A, a resist film 25 is again formed thereon, and the resist film 25 is shaped into a predetermined pattern by a known existing lithography technique. The superconducting film 24 thereunder is etched into a predetermined pattern. The remaining superconducting film portions 24a and 24b each become a part of the longitudinal connection line.

After the insulating film 26 and an etching stopper layer 27 effective during etching in a later step are sequentially deposited on the entire surface region while leaving the resist pattern 25, as shown in FIG. Then, the resist pattern 25, the insulating film 26 and the etching stop layer 27 deposited thereon are removed by a lift-off method using an organic solvent. Etch stop layer 27 may desirably be magnesium oxide (MgO).

After the lift-off step, if necessary, a surface cleaning treatment using argon gas plasma is performed.
As shown in the figure, the lower superconductor layer that can be composed of niobium
A tunnel barrier layer 32 composed of aluminum oxide (AlO _x ) and an upper superconductor layer 33 composed of niobium are sequentially laminated by a sputtering method. However, when the above-mentioned AlO _x is used as the tunnel barrier layer 32, what is actually deposited is an aluminum layer, which is oxidized in an oxygen atmosphere after the deposition. From the three-layer laminated structure (31 + 32 + 33) formed in this way, a small Josephson junction
JJ is cut out.

On the three-layer laminated structure (31 + 32 + 33), FIG.
After forming a resist film 34 as shown in FIG. 3 and processing it into a predetermined pattern by lithography, etching is performed, and a three-layer structure is formed into a portion continuous to the longitudinal connection lines 24a and 24b and a slightly larger area therebetween. Divide. As described above, if the dry etching technique using an etching gas such as CF4 or SF4 is applied to the etching at this time, it is automatically performed at the place where the etching stop layer 27 is provided without strictly controlling the etching time. You can stop it.

When an insulating film 35 is deposited on the entire surface while the patterned resist film 34 is left, the result is as shown in FIG. 4A. Thereafter, when lift-off is performed by using an organic solvent, FIG. As shown in the figure, the three-layer structure (31
+ 32 + 33) and the surrounding portion are insulated by the insulating film 35.

Thereafter, as shown in FIG. 4C, the resist film 36 applied to the entire surface is processed into a predetermined pattern which defines a planar area of the Josephson junction by appropriate lithography, and is preferably dry-etched. Then, only the upper superconductor layer 33 is cut out into a small plane area. In this case, if dry etching using an etching gas of CF4, SF4 or the like, if the tunnel barrier layer 32 is AlO _X layer, it also serves as an etch stop layer, strict time management is not required.

The three-layer structure portion (3) defined by the plane area of the fine upper superconductor layer 33 cut out in this manner.
1 + 32 + 33) is the so-called Josephson junction JJ. This part is shown by imaginary lines.

As shown in FIG. 4 (D), an insulating film 37 such as SiO ₂ is deposited on the entire surface while the resist film 36 is left, and immersed in an organic solvent to lift off, as shown in FIG. 5 (A). Only the surface of the upper superconductor layer 33 of the Josephson junction JJ is exposed, and the other is covered with the insulating film 37. And
Portions 31a and b, which are on both sides of the three-layer structure portion where the Josephson junction JJ is formed and which are apart from each other but originally correspond to a part of the lower superconductor layer 31, are respectively formed vertically. It forms a part of a continuous longitudinal connection line that is positionally aligned with the directional connection lines 24a, b.

On this, the resist film 38 applied over the entire surface is again processed into a predetermined pattern as shown in FIG. 5 (B), and is preferably subjected to dry etching to form a Josephson junction JJ. Part of the lower superconducting layer 31 that is continuous with the three-layer structure part and the longitudinal connection line that is also part of the lower superconducting layer 31 and is separated from the Josephson junction JJ
Drill a via hole to expose the surface of part 31a, b. At this time, the Josephson junction JJ
The part of the lower superconductor layer 31 which is continuous with the first and second layers and the tunnel barrier layer 32 on the longitudinal connection lines 31a and 31b separated on both sides thereof are also removed.

Next, as shown in FIG. 5C, a superconducting film 39 is deposited on the entire surface by a sputtering method or the like. Thereafter, the remaining resist film 38 and the superconducting film 39 thereon are removed by a lift-off method by immersion in an organic solvent, as shown in FIG.
As shown in the figure, the part 33 to be the upper electrode of the Josephson junction JJ, and the vertical connection line conducting to the lower electrode
39c and the surfaces of the extensions 39a, b extending further upward of the longitudinal connection lines on both sides are exposed.

After that, as shown in FIG. 6A, the resist film 40 applied on the entire surface is processed into a predetermined pattern by an appropriate lithography technique, and finally the resistor Rx shown in FIG. To obtain a suitable resistive material (eg, here
Pd) is deposited by, for example, an electron beam evaporation method.

This is immersed in an organic solvent, and the resist film 40 and the unnecessary resistive layer 41 thereon are removed by a lift-off method. As shown in FIG. 6B, a resistor Rx is formed at a predetermined position. be able to.

If necessary, in order to clean the surface, etching is performed over an appropriate depth, and a superconducting film 42 is deposited on the entire surface as shown in FIG. 6C.

As shown in FIG. 6D, a resist film 43 is applied thereon and processed into a predetermined pattern, the surface on the resistor Rx is removed, and the superconducting film 42 contacts only on both sides thereof. As described above, the superconducting film 42 extending to the right of the resistor Rx is connected to the upper electrode 33 of the Josephson junction JJ, and the portion connected to the lower electrode 31 via the vertical connection line 39c is provided on the surface of the vertical connection line 39b. The superconducting film 42 is desirably dry-etched so as to make contact.

Thereafter, if the remaining resist film 43 is removed with an organic solvent, the superconducting integrated circuit 20 directly and integrally constructed on the three-dimensional wiring laminated substrate structure 10 is obtained as shown in FIG. be able to.

As can be understood from the above description, the vertical connection line 13 shown in FIG. 1 (E) is partially formed in each step and is vertically extended. It is an aggregate of directional conductive lines. Further, the end face of the vertical connection line 13 exposed on the lower surface of the lowermost ceramic substrate 11-6 is preferably mounted on a printed circuit board (not shown), preferably via a ball grid array structure as described above. Signal terminal. Meanwhile, ground plane 21
The ground terminal connected to a is, for example, the first in the illustrated case,
Wiring patterns 15-1, 15-3, 15 of three and five layers 11-1, 11-3, 11-5
-5 can be taken out from the part exposed on the side, and if impedance conditions allow, a vertical connection line is provided between the wiring patterns (not shown) Specifically, the ball grid array can be taken out from the back surface of the lowermost substrate 11-6. In this case, the ball grid array can be used effectively.

Of course, the superconducting integrated circuit 20 to be constructed may be any circuit, any wiring pattern, and is not limited to a single circuit. Rather, in general, a plurality of the same kind or, in a special case, different kinds are formed side by side on one large three-dimensional wiring laminated substrate structure 10 and completed as shown in FIG. It seems that there are many cases where the lower laminated substrate structures are individually cut. Also in this case, the dividing method is arbitrary, and may be a mechanical method using a dicing saw, an optical method using a power laser beam, or the like.

Further, in the superconducting integrated circuit structure manufactured according to the present invention, the electrodes can be exposed on the surface of the superconducting integrated circuit 20. If necessary, a separately manufactured superconducting integrated circuit structure is turned over. Alternatively, it is easy to develop into a three-dimensional integrated circuit structure, for example, by sequentially constructing a second or later superconducting integrated circuit on the exposed electrode structure.

Regarding the wiring density, as described above,
By effectively using the vertical connection lines 13, the required number of wires and arrangement can be shared by those formed on a plurality of substrates, so that the entire wiring can be achieved without having to bring adjacent wirings so close to each substrate. As a result, an extremely high wiring density can be obtained with a good yield.

[0047]

According to the present invention, there is no need to perform an operation of bonding a die and a chip carrier by a flip chip bonding method using an expensive alignment device, so that the die is integrated on the chip carrier. , Increasing productivity and reducing costs. Further, since the electrodes are present on the surface of the superconducting integrated circuit, it is easy to form a three-dimensional integrated circuit. Furthermore, since the required number of wires required on the chip carrier side can be shared by a plurality of stacked substrates, the wiring density is extremely high as a whole without increasing the wiring density so much for each substrate. Can be obtained, which is convenient for obtaining a good yield.

[Brief description of the drawings]

FIG. 1 is a schematic structural diagram of an example of a superconducting integrated circuit structure of the present invention including a superconducting integrated circuit built on the laminated substrate structure and a manufacturing process of a three-dimensional wiring laminated substrate structure used in the present invention.

FIG. 2 is an explanatory diagram in an initial stage of an example of a process group for constructing a superconducting integrated circuit on a three-dimensional wiring laminated substrate structure used in the present invention.

FIG. 3 is an explanatory diagram of a process group following FIG. 2;

FIG. 4 is an explanatory diagram of a process group following FIG. 3;

FIG. 5 is an explanatory diagram of a process group following FIG. 4;

FIG. 6 is an explanatory diagram of a process group immediately before the final process following FIG. 5;

[Explanation of symbols]

10 Three-dimensional wiring laminated board structure, 11 ceramic substrate, 13 vertical connection line, 15 wiring pattern, 20 superconducting integrated circuit, 21a ground plane of superconducting integrated circuit, 21b vertical direction connecting to vertical connecting line of three-dimensional wiring laminated substrate structure Connection line, 31 Josephson junction lower electrode, 32 Josephson junction tunnel barrier layer, 33 Josephson junction upper electrode, JJ Josephson junction, Rx resistor.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-137698 (JP, A) JP-A-64-57699 (JP, A) JP-A-64-37100 (JP, A) JP-A 64-64 27294 (JP, A) JP-A-59-147472 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 39/24 H01L 39/02 H05K 3/46

Claims (5)

(57) [Claims] 1. A semiconductor device comprising: a plurality of insulating substrates overlapping with each other; a wiring pattern formed on each of the insulating substrates in advance; and wiring patterns on different insulating substrates penetrating through the insulating substrates. A superconducting integrated circuit comprising: a three-dimensional wiring laminated substrate structure electrically connected by a line; and a superconducting integrated circuit constructed on the three-dimensional wiring laminated substrate structure and electrically connected to the wiring pattern. Construction. 2. The superconducting integrated circuit structure according to claim 1, wherein said superconducting integrated circuit comprises a plurality of independent circuits. 3. The superconducting integrated circuit structure according to claim 2, wherein each of the plurality of superconducting integrated circuits is divided into ones together with the three-dimensional wiring laminated substrate structure thereunder. Superconducting integrated circuit structure. 4. A wiring pattern and a vertical connection line penetrating the insulating substrate are formed in advance on each of a plurality of insulating substrates overlapping with each other and then overlapped, and the wiring patterns on different insulating substrates are vertically connected to each other. Forming in advance a three-dimensional wiring laminated substrate structure having a structure electrically connected by the directional connection lines, and constructing a superconducting integrated circuit electrically connected to the wiring pattern on the three-dimensional wiring laminated substrate structure. A method for manufacturing a superconducting integrated circuit structure. 5. A wiring pattern and a vertical connection line penetrating the insulating substrate are formed in advance on each of a plurality of insulating substrates overlapping with each other and then overlapped, and the wiring patterns on different insulating substrates are vertically connected to each other. A three-dimensional wiring laminated substrate structure having a structure electrically connected by the directional connection lines is prepared in advance, and a plurality of superconducting circuits independent of each other are electrically connected to the wiring patterns on the three-dimensional wiring laminated substrate structure, respectively. A method of manufacturing a superconducting integrated circuit structure, comprising: constructing an integrated circuit and dividing the plurality of superconducting integrated circuits together with the three-dimensional wiring laminated substrate structure thereunder one by one.