JP3105074B2 - Voltage switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage switching circuit for reducing power supply noise, and more particularly to an LCD (Liquid Cryst).
al Display) driver.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view of a general LCD panel. In the figure, reference numeral 40 denotes a glass plate, on which a plurality of row electrodes 41 are formed. Reference numeral 42 denotes a glass plate, on which a plurality of column electrodes 43 are formed. The electrode forming surfaces of the glass plates 40 and 42 are opposed to each other so as to form a gap therebetween, and the peripheral portion is sealed by a member indicated by 44. Reference numeral 45 denotes a liquid crystal filling a space formed between the glass plates 40 and 42. Then, as shown in the plan view of FIG.
The respective row electrodes 41 and column electrodes 43 are arranged so as to be perpendicular to each other.

By applying a voltage between an arbitrary row electrode 41 and a column electrode 43, the display state of the liquid crystal at the intersection of the row electrode 41 and the column electrode 43 is determined. Each row electrode 41 and each column electrode 43 are supplied with a voltage from a separate voltage switching circuit. The voltage switching circuit described below is designed for a positive power supply process. The voltage switching circuit for supplying a voltage to each row electrode 41 includes, for example, voltages V0 (30 V), V1 (27 V), V4
(3 V) or V5 (0 V). Also,
The voltage switching circuit that supplies a voltage to each column electrode 43 supplies, for example, any one of the voltages V0, V2 (24V), V3 (6V), and V5. To bring the liquid crystal 45 into a display state, it is necessary to apply a difference between the voltages V0 and V5 as a display voltage to the liquid crystal. The difference needs to be applied to the liquid crystal. Therefore, to make the display state, the voltage V0 is supplied to the row electrode 41 and the voltage V5 is supplied to the column electrode 43, or the opposite voltage is supplied to each electrode. In order to make the display non-display state, the voltage V1 is supplied to the row electrode 41 and the voltage V3 is supplied to the column electrode 43, or the voltage V4 is supplied to the row electrode 41 and the voltage V2 is supplied to the column electrode 43. Or the opposite voltage is applied to each electrode. Which voltage of the display or non-display is output by the voltage switching circuit is determined by the voltage of the data signal input to the voltage switching circuit. For example, when the voltage of the data signal is VDD
At (30 V), the voltage V0 or V5 for display is output from the voltage switching circuit, and the voltage of the data signal becomes VSS.
(Ground voltage), the voltage V2 or V3 for non-display
Is output from the voltage switching circuit.

When a DC voltage is applied to a liquid crystal, the liquid crystal undergoes an electrochemical change and deteriorates. Therefore, the applied voltage must be an AC voltage. Therefore, whether the voltage applied to the liquid crystal is a display voltage or a non-display voltage, the direction of the voltage is inverted at regular intervals generated by the frame signal (alternating electric field signal) FR. Specifically, when the voltage V0 is applied to the row electrode 41 and the voltage V5 is applied to the column electrode 43 in the display state, the signal F
When the voltage of R changes, the voltage switching circuit supplying the voltage to the row electrode 41 supplies the voltage V5 from the voltage V0, and the voltage switching circuit supplying the voltage to the column electrode 43 changes the voltage from the voltage V5. The voltage V0 is supplied. Further, in the non-display state, the voltage V1 is applied to the row electrode 41,
If the voltage of the signal FR changes while the voltage V3 is being applied to the voltage 43, the voltage switching circuit supplying the voltage to the row electrode 41 supplies the voltage V1 to the voltage V4, and the voltage to the column electrode 43. The voltage switching circuit supplying the voltage supplies the voltage V2 from the voltage V3.

The power supply switching circuit changes the output voltage between V0 and V5.
In this case, since the difference between the voltages V0 and V5 is as large as 30 V, a large rush current flows through the output terminal of the power supply switching circuit. As a result, the voltage V
Noise occurs in the power supply voltage supplying 0 or the power supply voltage supplying the voltage V5.

Here, the voltage change of the frame signal FR causes the conventional voltage switching circuit to change the output voltage between the voltages V0 and V0.
5 will be described with reference to the circuit diagram of the column electrode voltage switching circuit of FIG. 6 and the operation waveform diagram of FIG.

In this voltage switching circuit, a data signal DATA is input to an input terminal 60 and an inverted signal / FR of a frame signal is input.
Is input to the input terminal 61, and a voltage is output to the output terminal 62. The input terminal 60 is connected to the input of the inverter circuit 63,
The inverter circuit outputs an inverted signal / DATA of the data signal. Numeral 64 denotes a two-input NAND circuit in which a signal / DATA is input to one input and a signal / FR is input to the other input.
Is input to the gate of the P-channel MOS transistor 65. The transistor 65 has a source connected to the supply terminal 66 of the voltage V2 (24 V) and a drain connected to the output terminal 62. Reference numeral 67 denotes a two-input NAND circuit. The signal DATA is input to one input, the signal / FR is input to the other input, and the output is input to the gate of the P-channel MOS transistor 68. The transistor 68 has a source connected to the supply terminal 69 of the voltage V0 (30 V), and a drain connected to the output terminal 62. 70 is 2-input NOR
Circuit, and a signal / DATA is input to one input,
A signal / FR is input to the other input, and an output is input to the gate of the N-channel MOS transistor 71. The transistor 71 has a source connected to the supply terminal 72 of the voltage V5 (0 V), and a drain connected to the output terminal 62. 73 is 2
This is an input NOR circuit in which a signal DATA is input to one input, a signal / FR is input to the other input, and an output is set to N.
The signal is input to the gate of the channel MOS transistor 74. The transistor 74 has a source connected to the supply terminal 75 of the voltage V3 (6 V) and a drain connected to the output terminal 62.

The above-mentioned voltage switching circuit outputs the output voltages V0 and V5.
Will be described with reference to the operation waveform diagram of FIG. The signal DATA is a logic level voltage VDD on the Hi side.
(30 V), the output signal / DATA of the inverter 63 is at the low-side logic level voltage VSS (ground voltage). Therefore, the signals / DATA and / FR
Is input to the NAND circuit 64, one of the input voltages is always V
SS, the output voltage is always VDD and the signal D
Since one input voltage of the NOR circuit 73 to which ATA and / FR are input is always VDD, the output voltage is always VSS. Therefore, a P-channel MOS transistor 65 whose gate is connected to the output of NAND circuit 64 and an N-channel MOS transistor whose gate is connected to the output of NOR circuit 73
The S transistor 74 is always off (non-conductive).

Next, a description will be given according to a change in the signal / FR. First, when the voltage of the signal / FR rises to VDD, the NAND circuit to which the signals DATA and / FR are input
The output voltage of the transistor 67 falls to VSS, and the transistor 68 whose gate receives the output voltage of the NAND circuit 67 is turned on (conductive state). Also, the signals / DATA and / FR
Is input, the output voltage of the NOR circuit 70 falls to VSS, and the transistor 71 whose gate receives the output voltage of the NOR circuit 70 is turned off. Therefore, the output terminal
62 has a voltage V supplied to the source of the transistor 68;
0 (30 V) is applied. Therefore, an inrush current for charging a capacitance component of the LCD panel connected to the terminal 62 flows from the voltage supply terminal 69, and noise occurs in the voltage V0. By the way, the threshold voltage of the P-channel transistor 68 is N
It is higher than the threshold voltage of the channel transistor 71. Therefore, the voltages applied to the gates of the transistors 68 and 71 simultaneously fall, but after the transistor 68 is turned on from the off state, the transistor 71 is turned off from the on state. Therefore, at the time indicated by t in the operation waveform diagram, the transistors 68 and 71 are simultaneously turned on, and the drains of both the transistors 68 and 71 are connected to the output terminal 62. A through current flows.

Next, the voltage of the signal / FR falls to V
When it becomes SS, the signals DATA and / FR are input to NA
The output voltage of the ND circuit 67 rises to VDD, and the transistor 68 whose gate receives the output voltage of the NAND circuit 67 is turned off. Further, the output voltage of the NOR circuit 70 to which the signals / DATA and / FR are input rises to VDD, and N
The transistor 71 whose gate receives the output voltage of the OR circuit 70 is turned on. Therefore, the voltage V5 (0) supplied to the source of the transistor 71 is applied to the output terminal 62.
V) is added. Therefore, an inrush current for discharging the capacitance component of the LCD panel connected to the output terminal 62 which has been charged with the voltage V0 (30 V) in advance is applied to the terminal 72.
, And noise occurs in the voltage V5. The voltages applied to the gates of the transistors 68 and 71 rise at the same time, but the transistor 71 changes from off to on after the transistor 71 changes from off to on due to the difference in threshold voltage. Therefore, a time t occurs when the transistors 68 and 71 are simultaneously turned on, so that the above-mentioned through current flows.

As described above, when the output voltage is switched between V0 and V5 by the voltage change of the frame signal, noise occurs in the power supply voltages V0 and V5, and a through current flows. There's a problem. Also,
The voltage switching circuit switches the output voltage between V2 and V3 when the voltage of the frame signal changes when the voltage of the signal DATA is VSS. In this case, noise occurs in the power supply voltages V2 and V3 as in the case of switching between the voltages V0 and V5, and further, a through current occurs.

In view of the above, in the prior art, a voltage switching circuit is configured as shown in the circuit diagram of FIG. The circuit diagram of FIG. 8 shows the voltages V0 and V of the voltage switching circuit.
Only the circuit portion for switching 5 is extracted.
Parts corresponding to those in FIG. 6 are denoted by the same reference numerals. This circuit differs from the circuit of FIG.
Only the conduction resistance of the MOS transistors forming the D circuit 67 and the NOR circuit 70 is the same.

The NAND circuit 67 has a power supply voltage VDD between the sources and drains of P-channel MOS transistors 80 and 81.
(30V) is inserted in parallel between the supply terminal 82 and the node X, and the source of the N-channel MOS transistors 83 and 84 is
The configuration is such that a portion between the drains is inserted in series between the node X and a ground line supplying the power supply voltage VSS. The signal DATA is input to the gates of the transistors 81 and 84, and the signal / FR is input to the gates of the transistors 80 and 83. If the conduction resistance of each of the transistors 80, 81, 83 and 84 is R80, R81, R83 and R84, the conduction resistance is R80
<R81 = R84 <R83.

In the NOR circuit 70, the source and drain of the P channel MOS transistors 85 and 86 are inserted in series between the supply terminal 87 of the power supply voltage VDD and the node Y, and the source and drain of the N channel MOS transistors 88 and 89 are connected. Are inserted in parallel between the node Y and the ground line supplying the power supply voltage VSS. And transistor 85
Signal / DATA is input to the gate of
The signal / FR is input to the gate of 88. Transistor 85,
The conduction resistance of each of 86, 88, 89 is R85, R86, R88, R
Assuming that the resistance value is 89, the conduction resistance is set to satisfy the relationship of R88 <R85 = R89 <R86.

[0015] The voltage switching circuit having the above configuration changes the output voltage to V0.
The operation of switching between V5 and V5 will be described with reference to the operation waveform diagram of FIG. Therefore, the voltage of the signal DATA is VDD.
Fixed to. Therefore, P-channel MOS transistor 81 to which signal DATA is input to the gate is always off, and N-channel MOS transistor 84 is always on. P-channel MOS transistor 85 to which signal / DATA is input to the gate is always on, and N-channel MOS transistor 89 is always off. A signal / F for operating this voltage switching circuit is provided.
The rise / fall time of the voltage of R is determined by the signal input terminal 61.
The signal / FR is made longer than the signal / FR shown in FIG.

First, the voltage of the signal / FR is changed from VSS to VD
When rising to D, the transistor 80 changes from the on state to the off state, and the transistor 83 changes from the off state to the on state. Then, since the transistors 83 and 84 are both on, the gate capacitance of the transistor 68 is discharged, and the voltage of the node X (the output voltage of the NAND circuit 67) falls to VSS. Further, when the voltage of the signal / FR is VD
When rising to D, the transistor 86 changes from the on state to the off state, and the transistor 88 changes from the off state to the on state. Then, since the gate capacitance of the transistor 71 is discharged, the voltage of the node Y (the NOR circuit 70) is discharged.
Output voltage) falls to VSS.

Since the conduction resistance of the transistor 83 is high and the conduction resistance of the transistor 88 is low, the fall time of the voltage at the node X is longer than the fall time of the voltage at the node Y. Therefore, after the transistor 71 changes from the on state to the off state by the voltage of the node Y, the transistor 68 changes from the off state to the on state by the voltage of the node X. As a result, transistors 68 and 71
Are not turned on at the same time, and no through current flows from the voltage source of the voltage V0 to the voltage source of the voltage V5. Also,
In addition to the high conduction resistance of the transistor 83, the signal /
Since the rise time of the voltage of FR is delayed, the conduction resistance of the transistor 83 does not decrease rapidly. Therefore, the voltage of the node X gradually falls. Therefore, even when the transistor 68 is turned on, the conduction resistance does not decrease sharply. As a result, the output terminal 62 is
Rush current hardly flows, and noise generated in the power supply voltage is reduced.

Next, when the voltage of the signal / FR falls to VSS, the transistor 80 changes from the off state to the on state, and the transistor 83 changes from the on state to the off state. Then, since the gate capacitance of the transistor 68 is charged by the voltage VDD of the voltage supply terminal 82, the node X
Rises to VDD. Further, when the voltage of the signal / FR falls to VSS, the transistor 86 changes from the off state to the on state, and the transistor 88 changes from the on state to the off state. Then, since the transistors 85 and 86 are both turned on, the voltage at the node Y rises to VDD because the gate capacitance of the transistor 71 is charged by the voltage VDD at the voltage supply terminal 87.

Since the conduction resistance of the transistor 80 is low and the conduction resistance of the transistor 86 is high, the rise time of the voltage at the node X is shorter than the rise time of the voltage at the node Y. Therefore, after the transistor 68 changes from the on state to the off state by the voltage of the node X,
The transistor 71 changes from the off state to the on state according to the voltage of the node Y. As a result, the transistors 68 and 71 do not turn on at the same time, and no through current flows from the voltage source of the voltage V0 to the voltage source of the voltage V5. Further, in addition to the high conduction resistance of the transistor 86, the signal / F
Since the fall time of the voltage of R is delayed, the conduction resistance of the transistor 86 does not drop sharply. Therefore, the voltage of the node Y rises slowly. Therefore, even when the transistor 71 is turned on, the conduction resistance does not decrease sharply. As a result, a voltage V5 (0 V) is output from the output terminal 62.
Makes it difficult for the rush current to flow into the voltage supply terminal 72, and noise generated in the power supply voltage is reduced.

[0020]

In the voltage switching circuit shown in FIG. 8, the rise / fall time of the voltage of the signal / FR is extended, and the conduction resistance of the transistor is increased to reduce the noise generated in the power supply voltage. It is carried out.

The rise / fall time of the voltage of the signal / FR is set by the parasitic capacitance and the parasitic resistance of the preceding circuit, and the circuit constant including the parasitic capacitance and the parasitic resistance varies depending on the manufacturing process. The noise reduction effect varies from circuit to circuit. Further, there is a problem that a transistor having a high conduction resistance has a large circuit area due to a long channel length.

As described above, the pre-stage circuit must be considered for noise reduction. Since a plurality of voltage switching circuits are integrated, the parasitic capacitance and the resistance differ for each pre-stage circuit. For this reason, the rise / fall time of the voltage of the signal / FR output from each preceding circuit is different, so that the design becomes complicated in order to determine the conduction resistance of the transistor constituting the voltage switching circuit in accordance with each signal. I have.

The present invention has been made in view of the above circumstances, and has an object to reduce the influence on the noise reduction effect even if the circuit constants vary in the manufacturing process, to further reduce the circuit area, and to design the circuit. It is to provide an easy voltage switching circuit.

[0024]

SUMMARY OF THE INVENTION A voltage switching circuit according to the present invention has a source connected to a first power supply voltage and a drain connected to an output terminal, a first conductivity type first MOS transistor, and a source. A second MOS transistor of a first conductivity type, which is inserted between the drains between the input terminal of the first input signal and the gate of the first MOS transistor, and a second input signal is input to the gate; The first in the sauce
Is supplied, a drain is connected to the gate of the first MOS transistor, and a gate of the third MOS transistor of the first conductivity type is supplied with an inverted signal of the second input signal. A MOS transistor, a second conductivity-type fourth MOS transistor having a source connected to the second power supply voltage and a drain connected to the output terminal;

A second source is inserted between the source and the drain between the input terminal of the inverted signal of the first input signal and the gate of the fourth MOS transistor, and the second input signal is input to the gate. A voltage capable of making the fourth MOS transistor non-conductive is supplied to the conductive fifth MOS transistor and the source, the drain is connected to the gate of the fourth MOS transistor, and the gate is connected to the second input signal. The sixth MO of the second conductivity type to which the inverted signal of
And a conductive resistance of the second MOS transistor is set higher than a conductive resistance of the sixth MOS transistor, and a conductive resistance of the fifth MOS transistor is set to be higher than the third MOS transistor. Is set to be higher than the conduction resistance.

[0026]

The voltage switching circuit having the above configuration has the following two functions.

First, when the conduction resistance of the second and fifth transistors is set to be high, and the second or fifth transistor is turned on, the first or fourth transistor is turned off.
Charge or discharge time of the gate capacitance of the transistor becomes longer. Therefore, the first and fourth
Does not drop sharply. Therefore, it is possible to prevent a large rush current from flowing to the output terminal.

Since the conduction resistance of the third and sixth transistors is set low, when the third or sixth transistor is turned on, the first or fourth transistor is turned off from the conduction state. The change to the state occurs in a shorter time than the change from the non-conductive state to the conductive state.
Therefore, when the conduction state of the first and second transistors changes in synchronization with the change in the voltage of the second input signal, one of the transistors becomes non-conductive and then the other transistor becomes conductive. become. Therefore, the first
Both the second transistor and the second transistor are CMOS inverters each having a drain connected to an output terminal, but no through current flows when the voltage of the second input signal changes.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a voltage switching circuit according to one embodiment of the present invention. In this embodiment, a voltage switching circuit for column electrodes of an LCD panel is designed for a positive power supply process. In the figure, 10 and 11 are signal input terminals,
The terminal 10 receives the data signal DATA, and the terminal 11 receives the frame signal FR. 12 and 13 are inverter circuits. The input side of the inverter circuit 12 is connected to the input terminal 10, and the input side of the inverter circuit 13 is connected to the input terminal 11. Reference numeral 14 denotes a P-channel MOS transistor, whose source and drain are inserted between the node a and the terminal 10, and whose gate is connected to the input terminal 11. 15 is P
The channel MOS transistor has a source connected to the supply terminal 16 for the power supply voltage VDD (30 V), a drain connected to the node a, and a gate connected to the output side of the inverter circuit 13. Reference numeral 17 denotes a P-channel MOS transistor. The source is connected to the supply terminal 18 for the voltage V2 (24 V), the drain is connected to the voltage output terminal 19, and the gate is connected to the node a.

Reference numeral 20 denotes an N-channel MOS transistor, whose source and drain are inserted between the node b and the input terminal 10, and whose gate is connected to the input terminal 11. twenty one
Is an N-channel MOS transistor, the source is connected to the ground line supplying the power supply voltage VSS, the drain is connected to the node b, and the gate is connected to the output side of the inverter circuit 13. Reference numeral 22 denotes an N-channel MOS transistor. The source is connected to the supply terminal 23 for the voltage V5 (0 V), the drain is connected to the output terminal 19, and the gate is connected to the node b.

Reference numeral 24 denotes an N-channel MOS transistor.
And the gate is connected to the input terminal 11. Reference numeral 25 denotes an N-channel MOS transistor having a source connected to the ground line, a drain connected to the node c, and a gate connected to the output side of the inverter circuit 13. 26 is an N-channel MOS transistor,
The source is connected to the supply terminal 27 for the voltage V3 (6V), the drain is connected to the output terminal 19, and the gate is connected to the node c.

Reference numeral 28 denotes a P-channel MOS transistor.
And the gate is connected to the input terminal 11. 29 is a P-channel MOS transistor, the source of which is connected to the supply terminal 30 of the power supply voltage VDD,
The drain is connected to the node d, and the gate is connected to the output side of the inverter circuit 13. 31 is a P-channel MOS
It is a transistor, the source is connected to the supply terminal 32 of the voltage V0 (30 V), the drain is connected to the output terminal 19, and the gate is connected to the node d. The conduction resistance of the transistors 14, 20, 24, 28 is set higher than the conduction resistance of the transistors 15, 21, 25, 29. Next, an operation of the voltage switching circuit having the above-described configuration according to a voltage change of the frame signal will be described.

First, when the voltage of the data signal DATA is VDD.
The operation according to the voltage change of the frame signal FR at the time of is described. When the voltage of the signal FR falls from VDD to the voltage VSS as shown in the operation waveform diagram of FIG.
Of the transistors 14, 20, 24, and 28 to which R is input, P
Channel type 14 and 28 change from off state to on state,
N-channel types 20 and 24 change from the on state to the off state. Transistors 15, 2 in which the signal / FR obtained by inverting the signal FR by the inverter circuit 13 is input to the gate.
Of 1, 25, and 29, P-channel type 15 and 29 change from the on state to the off state, and N-channel type 21 and 25 change from the off state to the on state.

Then, P-channel MOS transistor 17
When the transistor 15 is turned on, the voltage VDD of the terminal 16 is applied to the gate and the transistor 16 is turned off. However, even when the transistor 15 is turned off, the transistor 14 is turned on. Voltage VDD is applied, and the circuit remains off. Also, N-channel MOS
When the transistor 20 is on, the transistor 22 is on when the voltage VDD of the signal DATA is applied to the gate. However, when the transistor 20 is off and the transistor 21 is on, the gate has a ground line voltage. V
SS is added to turn off. Also, N-channel MOS
The transistor 26 is turned off when the transistor 24 is on, and the gate of the transistor 26 is supplied with the voltage VSS of the signal / DATA obtained by inverting the signal DATA by the inverter circuit 12. Since the transistor 25 is turned on, the voltage VSS of the ground line is applied to the gate, and the gate remains off. Also, P
The channel MOS transistor 31 is off when the voltage VDD of the terminal 30 is applied to the gate when the transistor 29 is on, but when the transistor 30 is off and the transistor 28 is on, the signal /
The voltage VSS of DATA is applied to turn on.

Therefore, among the transistors connected to the output terminal 19, only the transistor 31 has the drain turned on, and the voltage V 0 (30 V) supplied to the source of the transistor 31 appears at the terminal 19. By the way, since both the transistors 22 and 31 constitute a CMOS inverter having a drain connected to the terminal 19, a through current flows from the voltage supply terminals 32 to 23 when they are simultaneously turned on. However, compared to transistor 21, transistor 28
, The discharge of the gate capacitance of the transistor 22 is performed in a shorter time than the discharge of the gate capacitance of the transistor 31. Therefore, the voltage of the node b falls earlier than the voltage of the node d, so that the transistor 31 is turned on after the transistor 22 is turned off. Therefore, the transistors 22 and 31 are not simultaneously turned on, so that no through current flows. Further, since the conduction resistance of the transistor 28 is set high, it takes time to discharge the gate capacitance of the transistor 31. Therefore, the gate voltage of the transistor 31 (the voltage at the node d) does not drop sharply, so that the conduction resistance of the P-type transistor 31 does not drop sharply. Therefore, since a large rush current does not flow from the voltage source of the voltage V0 (30 V) to the output terminal 19, no large noise is generated in the voltage V0.

Next, the voltage of the signal FR is changed from VSS to VDD.
Rises, among the transistors 14, 20, 24, and 28 whose gates receive the signal FR, the P-channel transistors 14 and 28 change from the on state to the off state, and the N-channel transistors 20 and 24
Changes from the off state to the on state. Also, signal / FR
Of the transistors 15, 21, 25, and 29 whose gates are input, the P-channel type 15 and 29 change from the OFF state to the ON state, and the N-channel type 21 and 25 change from the ON state to the OFF state. .

Then, P-channel MOS transistor 17
Is the signal DA at the gate when the transistor 14 is on.
Although the voltage VDD of TA is applied and the transistor 14 is turned off, even if the transistor 14 is turned off, since the transistor 15 is turned on, the voltage VDD of the terminal 16 is applied to the gate and the transistor remains off. Also, N-channel MOS
When the transistor 21 is on, the transistor 22 is off when the voltage VSS of the ground line is applied to the gate, but the transistor 21 is off and the transistor 22 is off.
When the signal 20 is turned on, the voltage V of the signal DATA is applied to the gate.
DD is added to turn on. Also, N-channel MOS
When the transistor 25 is on, the transistor 26 is off because the voltage VSS of the ground line is applied to the gate, but the transistor 25 is off and the transistor 26 is off.
When 24 is turned on, the gate is supplied with the voltage VSS of the signal / DATA and remains off. When the transistor 28 is on, the gate of the P-channel MOS transistor 31 is applied with the voltage VSS of the signal / DATA. However, when the transistor 28 is off and the transistor 29 is on, Terminal
A voltage VDD of 30 is applied to turn off.

Therefore, among the transistors connected to the output terminal 19, only the transistor 22 has the drain turned on. Therefore, the voltage V5 (0 V) supplied to the source of the transistor 22 appears at the terminal 19. Since the conduction resistance of the transistor 20 is set higher than that of the transistor 29, charging the gate capacitance of the transistor 22 takes longer than charging the gate capacitance of the transistor 31. Therefore, since the voltage at the node d rises faster than the voltage at the node b, the transistor
After the transistor 31 is turned off, the transistor 22 is turned on. For this reason, the transistors 22 and 31 constitute a CMOS inverter, but since the two transistors are not simultaneously turned on, no through current flows. Further, since the conduction resistance of the transistor 20 is set to be high, it takes time to charge the gate capacitance of the transistor 22, so that the gate voltage of the transistor 22 (the voltage at the node b) does not rise rapidly. Therefore, the conduction resistance of the N-channel transistor 22 does not decrease rapidly. As a result, the voltage V5 (0 V) (0 V) is obtained from the capacitance component of the circuit connected to the output terminal 19, which is charged in advance with the voltage V0 (30 V).
The discharge current does not flow into the voltage source V) as a large inrush current, and no large noise is generated in the voltage V5.

Next, an operation according to a change in the voltage of the signal FR when the voltage of the signal DATA is VSS will be described. FIG.
When the voltage of the signal FR falls from VDD to the voltage VSS as shown in the operation waveform diagram of FIG. 7, the P-channel transistor 14 among the transistors 14, 20, 24, and 28 whose gates receive the signal FR.
And 28 change from the off state to the on state, and the N-channel type
20 and 24 change from the on state to the off state. In addition, among the transistors 15, 21, 25, and 29 to which the signal / FR obtained by inverting the signal FR by the inverter circuit 13 is input to the gate, the P-channel type 15 and 29 change from the on state to the off state, Channel types 21 and 25 change from the off state to the on state.

Then, P-channel MOS transistor 17
When the transistor 15 is turned on, the voltage VDD of the terminal 16 is applied to the gate and the transistor 16 is turned off.However, when the transistor 15 is turned off and the transistor 14 is turned on, the voltage VSS of the signal DATA is applied to the gate. In addition, it is turned on. The N-channel MOS transistor 22
Is the signal DA at the gate when the transistor 20 is on.
Although the voltage VSS of TA is applied and the transistor 20 is turned off, even if the transistor 20 is turned off, the transistor 21 is turned on and the gate VSS is applied to the gate and remains off. Also, N-channel MOS
When the transistor 24 is on, the transistor 26 is on when the voltage VDD of the signal / DATA is applied to the gate. However, when the transistor 24 is off and the transistor 25 is on, the voltage VSS is applied to the gate. In addition, it is turned off. The P-channel MOS transistor 31 is off when the voltage VDD of the terminal 30 is applied to the gate when the transistor 29 is on.
Even if the transistor 29 is turned off, the transistor 28
Is turned on, the voltage VDD of the signal / DATA is applied to the gate, and the gate remains off.

Therefore, among the transistors connected to the output terminal 19, only the transistor 17 has the drain turned on. Therefore, the voltage V 2 (24 V) supplied to the source of the transistor 17 appears at the terminal 19. By the way, the conduction resistance of the transistor 14 is
Therefore, the discharge of the gate capacitance of the transistor 26 is performed in a shorter time than the discharge of the gate capacitance of the transistor 17. Therefore,
Since the voltage at the node c falls earlier than the voltage at the node a, the transistor 17 is turned on after the transistor 26 is turned off. Therefore, transistor 17 and
26 constitutes a CMOS inverter, but no through current flows because the two transistors are not simultaneously turned on. In addition, since the conduction resistance of the transistor 14 is set high, it takes time to discharge the gate capacitance of the transistor 17, so that the gate voltage of the transistor 17 (the voltage at the node a) does not drop sharply. Therefore, the conduction resistance of the transistor 17 does not decrease rapidly, and a large rush current does not flow from the voltage source of the voltage V2 (24 V) to the output terminal 19, so that no large noise is generated in the voltage V2.

Next, the voltage of the signal FR is changed from VSS to VDD.
Rises, among the transistors 14, 20, 24, and 28 whose gates receive the signal FR, the P-channel transistors 14 and 28 change from the on state to the off state, and the N-channel transistors 20 and 24
Changes from the off state to the on state. Also, signal / FR
Of the transistors 15, 21, 25, and 29 whose gates are input, the P-channel type 15 and 29 change from the OFF state to the ON state, and the N-channel type 21 and 25 change from the ON state to the OFF state. .

Then, P-channel MOS transistor 17
Is the signal DA at the gate when the transistor 14 is on.
The transistor VSS is turned off and the transistor 15 is turned on, although the voltage VSS of the TA is applied and turned off. When the voltage VDD of the terminal 16 is applied to the gate, the transistor 14 is turned off. The N-channel MOS transistor 22
When the transistor 21 is turned on, the ground line voltage VSS is applied to the gate and the transistor 21 is turned off. However, even when the transistor 21 is turned off, the transistor 20 is turned on. Voltage VSS is applied, and remains in the off state. Also, N-channel MOS
When the transistor 25 is on, the voltage VSS is applied to the gate and the transistor 26 is off. However, when the transistor 25 is off and the transistor 24 is on, the gate of the signal / DATA is applied to the signal VDD.
Is added to turn on. Further, the P-channel MOS transistor 31 is off when the transistor 28 is on and the voltage VDD of the signal / DATA is applied to the gate. However, when the transistor 28 is off and the transistor 29 is on, The voltage at terminal 30 is V
DD is added and remains off.

Therefore, among the transistors connected to the output terminal 19, only the transistor 26 has the drain turned on. Therefore, the voltage V 3 (6 V) supplied to the source of the transistor 26 appears at the terminal 19. Since the conduction resistance of the transistor 24 is set higher than that of the transistor 15, the charging of the gate capacitance of the transistor 17 is performed in a shorter time than the charging of the gate capacitance of the transistor 26. Therefore, the voltage at the node a rises earlier than the voltage at the node c, so that the transistor 17 is turned off and then the transistor 26 is turned on. For this reason, the transistors 17 and 26 constitute a CMOS inverter, but no through current flows because the two transistors are not simultaneously turned on. Also,
Since the conduction resistance of the transistor 24 is set to be high, it takes time to charge the gate capacitance of the transistor 26, so that the gate voltage of the transistor 26 (the voltage at the node c) does not rise rapidly. Therefore, the conduction resistance of the N-type transistor 26 does not decrease rapidly. As a result, the voltage V3 (6V) is obtained from the capacitance component of the circuit connected to the output terminal 19, which is charged in advance with the voltage V2 (24V).
The discharge current does not flow into the voltage source V) as a large inrush current, and no large noise is generated in the voltage V3.

The voltage switching circuit of this embodiment can suppress noise generated in the power supply voltage without increasing the rise / fall time of the voltage of the frame signal as in the related art. Therefore, in the circuit of the embodiment, even if the circuit constants including the parasitic capacitance and the parasitic resistance of the preceding circuit connected to the input terminal of the frame signal vary in manufacturing, the influence on the noise reduction effect is small. The circuit of the embodiment is a NAND or NO
Since the number of elements is smaller than that of the conventional voltage switching circuit using the R circuit, the circuit area is small. Furthermore, the circuit of the embodiment can be easily designed because the noise of the power supply voltage can be reduced without considering the circuit in the preceding stage. Although the circuit of the embodiment is designed for a positive power supply process, it goes without saying that the present invention can be applied to a voltage switching circuit for a negative power supply process.

[0047]

As described above, according to the present invention, there is provided a voltage switching circuit which has a small influence on a noise reduction effect even if a circuit constant varies in a manufacturing process, has a small circuit area, and is easy to design. can do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a voltage switching circuit according to one embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the voltage switching circuit according to one embodiment of the present invention.

FIG. 3 is an operation waveform diagram of the voltage switching circuit according to one embodiment of the present invention.

FIG. 4 is a sectional view of an LCD panel.

FIG. 5 is a plan view of row electrodes and column electrodes of the LCD panel.

FIG. 6 is a circuit diagram of a conventional voltage switching circuit.

FIG. 7 is an operation waveform diagram of a conventional voltage switching circuit.

FIG. 8 is a circuit diagram of a conventional voltage switching circuit.

FIG. 9 is an operation waveform diagram of a conventional voltage switching circuit.

[Explanation of symbols]

10, 11 ... signal input terminal, 12, 13 ... inverter circuit, 14,
15, 17, 28, 29, 31 ... P-channel MOS transistors,
20, 21, 22, 24, 25, 26 ... N-channel MOS transistors, 16, 18, 23, 27, 30, 32 ... voltage supply terminals, 19 ... voltage output terminals.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Ken Suyama 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa In-house Toshiba Microelectronics Corporation (56) References JP-A-2-236593 (JP, A) JP-A Sho 56-65190 (JP, A) JP-A-5-35211 (JP, A) JP-A-59-46687 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 G09G 3/36

Claims (1)

(57) [Claims] 1. A first conductive type first transistor having a source connected to a first power supply voltage and a drain connected to an output terminal.
An OS transistor and a source and a drain of the first conductivity type are inserted between the input terminal of the first input signal and the gate of the first MOS transistor, and the second input signal is input to the gate. A voltage capable of making the first MOS transistor non-conductive is supplied to the second MOS transistor and the source, the drain is connected to the gate of the first MOS transistor, and the inverted signal of the second input signal is supplied to the gate. A third MOS transistor of a first conductivity type to be input, a fourth MOS transistor of a second conductivity type having a source connected to the second power supply voltage and a drain connected to the output terminal, and a source / drain A space is inserted between the input terminal of the inverted signal of the first input signal and the gate of the fourth MOS transistor, and the gate receives the second input signal. A voltage capable of making the fourth MOS transistor non-conductive is supplied to the source of the fifth MOS transistor of the second conductivity type, the drain is connected to the gate of the fourth MOS transistor, and the gate is connected to the second MOS transistor. A sixth MOS transistor of a second conductivity type to which an inverted signal of the input signal is input, wherein a conduction resistance of the second MOS transistor is set higher than a conduction resistance of the third MOS transistor. A voltage switching circuit, wherein the conduction resistance of the fifth MOS transistor is set higher than the conduction resistance of the sixth MOS transistor.