JP3147849B2 - Protection circuit for semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a layout structure of an electrostatic protection circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, an electrostatic protection circuit is provided between a bonding pad and an internal circuit in the semiconductor integrated circuit device as a protection function against an external overvoltage input.

FIG. 7 is a plan view showing an example of a conventional electrostatic protection circuit of a semiconductor integrated circuit device. In FIG. 7, 1
Is a bonding pad, 2 is an electrostatic protection circuit, 3 is a metal wiring, and 4 is an internal circuit.

FIG. 8 is a sectional view taken along the line CC 'in FIG. Referring to FIG. 8, an N-type well 12 and a P-type well 8 are formed on an upper portion of a silicon substrate through ion implantation and diffusion processes.
The P-type diffusion layers 5, 9, 10,
Gate electrodes 38 and 39 are formed via N-type diffusion layers 6, 7 and 11 and a gate oxide film, and N-channel MOS transistor 13 and P-channel MOS transistor 14 are formed.
Are formed.

[0005] The N-type diffusion layer 6 of the N-channel MOS transistor 13 is connected to GND, and the N-type diffusion layer 7 is connected to the bonding pad 1 through the metal wiring 3. Also,
The P-type well 8 of the N-channel MOS transistor 13 is
It is connected to GND through the mold diffusion layer 5.

The P-type diffusion layer 10 of the P-channel MOS transistor 14 is connected to the power supply VDD and the P-type diffusion layer 9 is connected to the metal wiring 3.
Through to the bonding pad 1 respectively.
The N-type well 12 of the P-channel MOS transistor 14 is connected to the power supply VDD through the N-type diffusion layer 11.

The metal wiring 3 connects the bonding pad 1 and the internal circuit 4.

FIG. 9 shows an equivalent circuit of the above configuration.

In the first example described above, a protection circuit is formed by the snap-back characteristic of the N-channel transistor 13 and the diode characteristic by the PN junction of the N-type diffusion layer 7 and the P-type well 8. Snapback characteristics of channel transistor 14 and P-type diffusion layer 9
The protection circuit is formed by the diode characteristics of the N-type well 12 and the PN junction of the N-type well 12, thereby protecting the internal circuit from the high voltage input from the bonding pad.

FIG. 4 is a plan view showing a second example of a conventional electrostatic protection circuit of a semiconductor integrated circuit device. In FIG. 4, 15 is a bonding pad, 17 is an electrostatic protection circuit,
16 is a metal wiring, and 18 is an internal circuit.

FIG. 5 is a sectional view taken along the line BB 'in FIG. Referring to FIG. 5, on the top of the silicon substrate,
N-type well 22 and P through ion implantation and diffusion processes
A mold well 20 is formed.
The metal wiring 16 is provided above the P-type well 20.

The metal wiring 16 connects the bonding pad 15 and the internal circuit 18.

An N-type diffusion layer 19 is formed in a P-type well 20 immediately below the bonding pad 15.
A protection diode 23 is formed by a PN junction between the type diffusion layer 19 and the P-type well 20.

A protection diode 24 is formed in a portion from the bonding pad 15 to the internal circuit 18.

The protection diode 24 utilizes a PN junction between the P-type diffusion layer 21 implanted in the N-type well 22 and the N-type well 22. The P-type diffusion layer 21 is formed on the upper part through a contact hole. It is connected to the metal wiring 16.

The N-type well 22 is connected to a power supply VDD through a portion not shown. The P-type well 20 is connected to GND through a portion not shown. FIG. 6 shows these in an equivalent circuit.

In this second example, a protection circuit is formed by the diode characteristics of the PN junction diode 23 immediately below the bonding pad and the PN junction diode 24 formed between the bonding pad 15 and the internal circuit 18. It functions to protect the internal circuit from the high voltage input from the bonding pad 15.

[0018]

However, the above-mentioned conventional electrostatic protection circuit of a semiconductor integrated circuit device has the following problems.

(1) In the first example, the integration density of the internal region cannot be improved, and the integration degree of the internal circuit is reduced.

The reason is that the N-channel MOS transistor 13 and the P-channel MOS transistor 14 constituting the protection circuit 2 are formed between the bonding pad 1 and the internal circuit 4, and are relatively difficult to form the protection circuit 2. Because it requires a large area,

(2) The second example also has a problem that the integration density of the internal region cannot be improved.

The reason is that the PN constituting the protection circuit 17 is
This is because the junction diode 23 is formed between the bonding pad 15 and the internal circuit 18 and requires a relatively large area to form the protection circuit 17.

It is to be noted that, in order to save the space of the protection circuit,
As a conventional method for improving the degree of integration, for example, Japanese Unexamined Patent Publication No.
Japanese Patent No. 206768 proposes a configuration in which a protection diode is formed in a semiconductor substrate directly below a bonding pad (electrode pad) and formed between the semiconductor substrate and the semiconductor substrate to save space in the protection circuit. And
Japanese Patent Application Laid-Open No. 57-0164571 discloses a configuration in which an input protection circuit is provided directly below a part or all of a pad, a contact hole is provided, and a semiconductor region of a conductivity type opposite to that of a semiconductor substrate is provided therebelow. There has been proposed a semiconductor integrated circuit having such a configuration.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit device which prevents a reduction in the degree of integration of internal circuits due to an electrostatic protection circuit region. It is in.

[0025]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention comprises an electrostatic protection circuit region required as a semiconductor integrated circuit device, disposed immediately below and between bonding pads. An electrostatic protection circuit is not arranged between the bonding pad and the internal circuit. The present invention
Providing two MOS transistors connected in series,
The diffusion layer forming the serial connection of the two MOS transistors
The two MOSs connected to the bonding pad;
The first MOS transistor among the transistors;
The diffusion layer that is not the column connection is connected to the power supply,
Diffusion of MOS transistor other than the series connection
Has an electrostatic protection circuit in which the layer is connected to ground potential
You.

The protection element between the bonding pads is configured to be shared by the respective bonding pads.

[0027]

Embodiments of the present invention will be described below. In a preferred embodiment of the semiconductor integrated circuit device according to the present invention, the electrostatic protection circuit region (2 in FIG. 1)
7) is disposed immediately below the bonding pad and between the bonding pads (25 and 26 in FIG. 1), and no electrostatic protection circuit is disposed between the bonding pad and the internal circuit (28 in FIG. 1). Therefore, the internal area is enlarged as compared with the above-described conventional configuration, and the degree of integration of the internal circuit can be improved.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an example of a semiconductor integrated circuit device according to one embodiment of the present invention. In FIG. 1, 2
5, 26 are bonding pads, 27 is a protection circuit, 28
Is an internal circuit.

Referring to FIG. 1, in this embodiment, there is no protection circuit between the bonding pads 25 and 26 and the internal circuit 28, and the electrostatic protection circuit is provided immediately below the bonding pads 25 and 26 and Bonding pad 25,
26.

FIG. 2 is a sectional view taken along the line AA 'of FIG. Referring to FIG. 2, a P-type well 37 is formed on an upper portion of a silicon substrate through ion implantation and diffusion processes.
Further, P-type diffusion layers 30, 36 and N-type diffusion layers 31, 32, 33, 3
4 and 35 are formed. Bonding pads 25 and 26 are formed on the upper part.

The N-type diffusion layers 32 and 34 are connected to the bonding pads 25 and 26 through contact holes, respectively.

The N-type diffusion layer 33 is connected to a power supply VDD through a power supply (VDD) line (not shown), and the N-type diffusion layers 31 and 35 and the P-type diffusion layers 30 and 36 are connected through a ground (GND) line (not shown). Connected to GND. With these configurations, N-channel transistors 40 and 41 are formed. The N-channel transistors 40 and 41 use the bonding pad 25 itself as a gate electrode, an interlayer film between the pad and the substrate as a gate insulating film, and have a threshold VT having a gate electrode made of gate polycide or the like. Higher than the transistor.

FIG. 3 is a diagram showing the configuration shown in FIG. 2 by an equivalent circuit. In this embodiment, the internal circuit is decomposed from the high voltage input from the bonding pad 25 by the ON characteristics and the snapback characteristics of the N-channel transistors 40 and 41 immediately below the bonding pad 25 and between the bonding pads 25 and 26. It serves to protect 28.

The N-type diffusion layer 33 formed between the bonding pads 25 and 26 is a protection element that functions as a common element for both the bonding pads 25 and 26.

In this embodiment, the electrostatic protection circuit is provided immediately below the bonding pad and between the bonding pads, thereby performing an electrostatic protection function. Therefore, a protection circuit is provided between the bonding pad and the internal circuit. It is unnecessary to do it.

[0036]

As described above, according to the present invention,
By arranging the electrostatic protection circuit directly under the bonding pad and between the bonding pads, the area configured only as the protection circuit is reduced and the internal area is expanded, thereby improving the integration degree of the internal circuit. This has the effect of performing

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an embodiment of the present invention, and FIG.
3 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is a diagram showing a configuration of an embodiment of the present invention by an equivalent circuit.

FIG. 4 is a layout diagram showing a second example of a conventional semiconductor integrated circuit device.

5 is a diagram showing a second example of a conventional semiconductor integrated circuit device, and is a cross-sectional view taken along line BB 'of FIG.

FIG. 6 is a diagram showing a second example of a conventional semiconductor integrated circuit device in an equivalent circuit.

FIG. 7 is a layout diagram showing a first example of a conventional semiconductor integrated circuit device.

8 is a diagram showing a first example of a conventional semiconductor integrated circuit device, and is a cross-sectional view taken along line BB 'of FIG.

FIG. 9 is a diagram showing a first example of a conventional semiconductor integrated circuit device as an equivalent circuit.

[Explanation of symbols]

1, 15, 25, 26 Bonding pads 12, 22 N-type wells 8, 20, 37 P-type wells 6, 7, 11, 19, 31, 32, 33, 34, 35
N-type diffusion layer 5, 9, 10, 21, 30, 36 P-type diffusion layer 3, 16, 29 Metal wiring 4, 18, 28 Internal circuit 23, 24 PN junction diode 13, 30, 41 N-channel transistor 14 N-channel Transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 21/8238 H01L 27/06 H01L 27/092 H01L 29/78

Claims (3)

(57) [Claims] 1. A series connection under a bonding pad
Two MOS transistors are provided, and the two MOS transistors are provided.
The diffusion layer forming the series connection of the transistor is
Connected to the first and second MOS transistors.
Of these, the series connection of the first MOS transistor
One of the diffusion layers is connected to the power supply and the second MOS transistor
The diffusion layer other than the series connection part of the
A semiconductor integrated circuit device having an electrostatic protection circuit connected to the circuit. 2. The bondin just under a bonding pad.
Of the second conductivity type connected to the contact pad and the contact hole.
One diffusion layer and the bonding pad row.
The second diffusion layers disposed on both sides of the first diffusion layer along the direction.
Second and third diffusion layers of a conductivity type;
4 is provided in the well or substrate of the first conductivity type,
The second and fourth diffusion layers are grounded, and the third diffusion layer is
Connect each layer to a power supply and
Immediately below the two bonding pads with the bonding pad as the gate electrode
The semiconductor integrated circuit device characterized by comprising a transistor. 3. A first diffusion layer of a second conductivity type, which is connected to the bonding pad by a contact hole, immediately below the bonding pad, and the first diffusion layer along a direction in which the row of bonding pads is arranged. Second arranged on both sides of the
A second conductivity type second diffusion layer and a first conductivity type fourth diffusion layer provided in a first conductivity type well or substrate;
The second and fourth diffusion layers are connected to a ground, the third diffusion layer is connected to a power supply, and two transistors each having the bonding pad as a gate electrode are provided immediately below the bonding pad; Wherein the third diffusion layer provided between the first and second transistors is shared with one transistor provided immediately below the adjacent bonding pad.