JP3039585B2 - Synchronous word detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a time division multiple access (TD).
D) The present invention relates to a synchronous word detection circuit used to receive a burst signal of a communication system.

[0002]

2. Description of the Related Art When a burst signal of the TDD communication system is demodulated and received, a pattern called a synchronization word having a very low correlation with a data signal is inserted at a fixed position of each burst signal on the transmission side, and the synchronization word position is determined. Is detected, the data position in the burst signal is specified, and the reception timing such as the decoding timing of the encoded data and the extraction timing of the control signal is generated. Therefore, if the synchronization word is not detected or erroneously detected, data loss occurs, and the line quality is significantly deteriorated.

In a conventional synchronous word detection circuit, even if a synchronous word containing a bit error is received, the position of the synchronous word can be detected correctly. If the number of inconsistencies with the synchronization word is equal to or smaller than ε bits, the synchronization word is detected using a correlation detector that correctly detects the synchronization word.

FIG. 3 shows a configuration example of a conventional synchronous word detection circuit to which a correlation detector is applied. The received data 101 is input to the shift register 11, the number of mismatches with the reference synchronizing word pattern 102 held in the register 12 is calculated by the mismatch number adding circuit 13, and the number of mismatches is determined by the comparator 14 to be the allowable error bit number (ε). ) A detection pulse is output at a bit position less than 103. Thereafter, the logical product of the gate 15 and the aperture window 104 is output as a synchronizing word detection pulse 105.

According to this circuit, even if a bit error of up to ε bits occurs in the received synchronization word, the synchronization word can be correctly detected, and both the non-detection rate and the false detection rate of the synchronization word are low. By optimizing to a certain value, the probability of data loss can be reduced. The optimization of ε has been studied in the field of satellite communications (for example, W. Schrem
pp and T. Sekimoto: "Uniqueword detection in digital
burst communications ", IEEE Trans.on Commun.Techno
l.COM-16, No. 4, pp. 597-605 (Aug. 1968)). Based on these studies, the synchronization word length of 16 bits and the synchronization word of Hamming distance 6 under the thermal noise environment with a line error rate of 0.01
FIG. 4 shows the false detection rate characteristics. Ε at which both the non-detection rate and the false detection rate are low is 3, and the synchronous word non-false detection rate is 2 × 1.
0 ^-5 .

Furthermore, when the Doppler frequency is lower than the signal transmission speed and the signal propagation path is short, the time-varying component of the received clock does not exceed one symbol length in one frame, and the continuity of the received clock is reduced. Since the synchronization word is kept, once the synchronization word is detected, the position of the synchronization word can be specified by the self-running counter. That is, when the transmission timing of the transmitting station is not changed, there is no difference between the free-running frame and the data position detected by the synchronization word.

[0007]

However, in the conventional circuit, if the sync word is not detected by the correlation detector, the received data is discarded as a sync word non-detection. There is a problem that the probability is significantly deteriorated. To prevent this by using the above-described self-running counter, if the transmitting station cannot detect the synchronizing word of the burst signal in the frame whose transmission timing has been changed, the synchronizing word output by the self-running counter will not be detected. Position pulses are not applied correctly, again causing data loss. Since the transmission timing is controlled for each symbol, the probability of correctly detecting the synchronization word position after one non-detection of the synchronization word is 1/3, and when the transmission timing is changed, data loss occurs with a probability of 2/3.

[0008] In the case of erroneous detection of a synchronizing word, although a detection pulse is output, its position is erroneous, causing data loss similar to that of non-detection. Therefore, generally, an optimal pattern is calculated and provided by computer simulation or the like.
Therefore, what can be improved by the synchronization word detection method is the non-detection rate of the synchronization word.

[0009] The present invention has been made in view of the above,
The goal is to reduce the probability of non-detection of the sync word,
An object of the present invention is to provide a synchronous word detection circuit that can reduce the data loss probability.

[0010]

To achieve the above object, a synchronous word detecting circuit according to the present invention demodulates a burst signal of a time division multiple access communication system and detects a synchronous word from the demodulated signal. A storage means for storing the demodulated signal for two burst signals, and a correlation between a sync word included in a demodulated signal of each of the stored burst signals and a reference sync word. And a correlation detector for detecting, when the sync word of the first burst signal cannot be detected, the sync word position of the first burst signal is estimated by the sync word detection pulse of the second burst signal. The gist is that data of the first burst signal is read out by detecting the synchronization word.

[0011]

In the synchronous word detecting circuit of the present invention, the first synchronous word of the two consecutive burst signals is simultaneously detected, so that the first synchronous word is detected.
Even when the synchronization word of the second burst signal is not detected, the first reception timing is generated using the second synchronization word detection pulse, and the data of the first burst signal is read. .

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a synchronous word detection circuit according to one embodiment of the present invention. In the figure, received data 101 for two burst signals from a demodulator (not shown) is input to an elastic buffer 31.
Two correlation detectors 33 and 34 separated by a burst length
, The synchronization word of each of the two burst signals is detected. The number of allowable error bits (ε) for each of the two detectors
103 and an aperture window 104 for detecting a synchronous word are set in advance. When the synchronization word of the first burst signal is detected by the correlation detector 34, the first burst signal is read using the detected pulse. Meanwhile, the first
If the sync word of the second burst signal is not detected by the correlation detector 34, the first burst signal is read using the second sync word detection pulse, and then the second burst signal is read. In order to perform such an operation, the synchronizing word detection circuit of the present embodiment uses either the output circuit of the correlation detector 34 to ignore the detection pulse of the correlation detector 33 or the output pulse of the two correlation detectors. The addition circuit 36 for taking a logical sum so that the synchronous word detection pulse 10 can be output from the elastic buffer 31.
Read control circuit 3 which outputs read data 304 in accordance with 5
2 is provided.

In the case where the transmission timing of the transmitting station is changed by applying the synchronous word detecting circuit of the present configuration, the synchronous word detection position is erroneously detected when the first burst signal having no symbol shift is not detected. The data loss probability is 2.times. (1 / 3.times.1 / 2) because it is only when the sync word detection position of the second burst signal is shifted by. +-. 1 symbol.
= 1/3.

When the non-detection rate of the synchronizing word of the synchronizing word detection circuit of the present invention is Ppm, the false detection rate is Pfm, the non-detection rate of the synchronizing word in the correlation detector is Pm, and the false detection rate is Pf, respectively. Can be derived. First, since the non-detection rate is the probability of not being detected by any of the two independent correlation detectors, it is given by the product of the non-detection probabilities of each detector.

[0016]

Ppm = Pm × Pm (1) On the other hand, the erroneous detection rate is a value obtained by subtracting from 1 the probability of correct detection by any of the two independent correlation detectors.

[0017]

Pfm = 1− (1−Pf) ² = 2 × Pf−Pf ² (2) Synchronous word in a thermal noise environment with a line error rate of 0.01 calculated from equations (1) and (2) FIG. 2 shows the non-detection / erroneous detection probability characteristics of a synchronization word having a length of 16 bits and a Hamming distance of 6. The number of allowable error bits at which both the non-detection rate and the erroneous detection rate are low is 2, and the non-detection / false detection rate is 3 × 10 ^-7 , which can be reduced by one digit or more as compared with the conventional circuit.

Since the data loss probability when the transmission timing of the transmitting station is changed is 1/3, the data loss probability when the transmission timing is changed by 50% can be reduced as compared with the conventional circuit.

[0019]

As described above, according to the present invention,
Even if the synchronization word of the first burst signal is not detected by detecting the synchronization words of two consecutive burst signals at the same time, the first reception timing can be adjusted using the second synchronization word detection pulse. Since the data is generated and the data of the first burst signal is read, the received burst signal is not discarded, so that no data loss occurs.
Further, even if a synchronization word is not detected in a frame in which the transmission timing of the transmitting station has been changed, the synchronization word position is estimated from the burst signal of the next frame, so that the probability of data loss can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a synchronous word detection circuit according to one embodiment of the present invention.

FIG. 2 is a graph showing a synchronizing-word non-false detection rate characteristic of the synchronizing-word detecting circuit shown in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a conventional synchronous word detection circuit.

FIG. 4 is a block diagram showing a conventional synchronous word detection circuit shown in FIG.
It is a graph which shows an erroneous detection rate characteristic.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Shift register 12 Register 13 Mismatch number addition circuit 14 Comparator 31 Elastic buffer 32 Read control circuit 33, 34 Correlation detector 35 Prohibition circuit 36 Addition circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/10

Claims (1)

(57) [Claims] 1. A synchronizing word detecting circuit for demodulating a burst signal of a time division multiple access communication system and detecting a synchronizing word from the demodulated signal, and accumulating means for accumulating the demodulated signal for two burst signals. A correlation detector for detecting a correlation between a synchronization word included in a demodulated signal of each of the stored burst signals and a reference synchronization word, wherein the synchronization word of the first burst signal is If the detection is not possible, the synchronization word position of the first burst signal is estimated by the synchronization word detection pulse of the second burst signal, the synchronization word is detected, and the data of the first burst signal is read. And a synchronous word detection circuit.