JP3036037B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of forming a stacked semiconductor device.

[Prior Art] In recent years, the integration of semiconductor elements has been advanced, and 4MDRAM, 1MSRAM
The mass production of 16M, 64MDRAM, 4MSRAM, etc. are being actively developed and prototyped. In the future, as the density of these semiconductor devices further increases, it is expected that expectations for the realization of semiconductor devices having a three-dimensional structure will further increase. Taking SRAM as an example, in a 4M or larger SRAM, a high-resistance poly-
4-T type SRAM using Si or 6-T type SRAM with n-channel and p-channel MOSFETs formed on silicon substrate
Instead, an SRAM with a stacked CMOS structure has been studied and prototyped. In a stacked COMS structure, an n-channel
MOSFET is formed and p-channel poly
-SiTFT layered structure, 4-T type and 6
-Has the advantages of the T type. That is, the p-channel is formed of poly-Si TFT, and the p-channel
A CMOS structure can be realized with almost the same cell size as the die, and an SRAM excellent in high integration, soft error resistance, low power consumption, etc. can be realized.

[Problems to be Solved by the Invention] However, the conventional semiconductor device in which poly-Si TFTs are stacked has the following problems. (1) A method of forming a poly-Si film at about 590 ° C. to 630 ° C. by LPCVD or a method of growing a poly-Si film by a solid phase growth method has been mainly used. The crystallinity of the obtained poly-Si film is not always good, and it is difficult to form a high-quality poly-Si film having a crystallization ratio of more than 95% or a high-quality poly-Si film having few defects such as twins in crystal grains at a low temperature. there were. Therefore, it has been difficult to reduce the off-state current and increase the on-state current of the TFT.
(2) The method of forming source / drain regions of a poly-Si TFT by an ion implantation method and activating it at about 600 ° C. to 900 ° C. has been generally used. However, in this method, impurities are horizontally transferred during activation annealing. In order to diffuse and reduce the effective channel length, it has been difficult to form a TFT with a gate length of 1 μm or less with good reproducibility. Further, by reducing the thickness of the polycrystalline silicon layer forming the channel region to about 500 ° or less, preferably to about 50 ° to 250 °, high performance such as reduction of off-current and Vth can be realized. However, when the source / drain regions are formed in such a thin film, there is a problem that the sheet resistance cannot be sufficiently reduced.

Therefore, the present invention provides a simpler and more practical method for forming polycrystalline silicon having high crystallinity at low temperature with good reproducibility and forming a high-performance poly-Si TFT at low temperature. Further, the present invention provides a fine po
A method for forming a ly-Si TFT is also provided.

[Means for Solving the Problems] In a method for manufacturing a semiconductor device according to the present invention, a step of forming a gate electrode on a substrate, a step of forming an insulating film forming a gate insulating film on the gate electrode, Forming a first silicon layer serving as a source / drain region on the film; patterning the first silicon layer on the gate electrode so as to remove the first silicon layer; annealing the first silicon layer to activate impurities And then forming a second silicon layer to be a channel on the gate electrode and the first silicon layer.

FIG. 3 is an example of a cross-sectional view of a conventional semiconductor device.
In FIG. 3, a stacked type CMOS is taken as an example of the semiconductor element. In FIG. 3, 301 is a silicon substrate, 302
Is a p-well region, 303 is an element isolation region formed by the LOCOS oxidation method, 304 is a gate insulating film, 305 a gate electrode using poly-Si or the like as an element material, 306 is an n + diffusion region, and 307 is an insulating material forming a gate insulating film. Layer, 308 is a polycrystalline silicon layer forming a channel region, 309 is ap + diffusion region forming a source / drain region, and after implanting boron by ion implantation,
A method of activating at about 600 ° C. to 900 ° C. is generally used. However, in this method, impurities are diffused in the lateral direction during activation annealing and the effective channel length is reduced, so that it is difficult to form a TFT having a gate length of 1 μm or less with good reproducibility. The thickness of the polycrystalline silicon layer forming the channel region is about 500 ° or less, preferably 50 ° to 2 °.
By reducing the film thickness to about 50 °, the off-current can be reduced and Vth
Higher performance such as reduction of noise can be realized. However, in the conventional element structure, when the polycrystalline silicon film is thinned for the above-described reason, there is a problem that the sheet resistance of the source / drain regions cannot be sufficiently reduced. The present invention solves such a problem, and details thereof will be described below based on embodiments.

FIG. 1 is an example of a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 1 shows a stacked CMOS as an example of the semiconductor element. In FIG. 1, 101 is a silicon substrate, 102 is a p-well region, 103 is an element isolation region formed by LOCOS oxidation, 104 is a gate insulating film, 105 poly.
A gate electrode using -Si or the like as an element material; 106, an n + diffusion region; 107, an insulating layer forming a gate insulating film; 109, a polycrystalline silicon layer doped with impurities forming source / drain regions;
108 is a polycrystalline silicon layer forming a channel region.
In the present invention, since the source / drain regions of the poly-Si TFT are formed of a polycrystalline silicon layer doped with an impurity, the impurity does not diffuse laterally during activation annealing, and there is no problem that the effective channel length is reduced. TFTs having a length of 1 μm or less can be formed with good reproducibility. That is, in the TFT having a laminated structure according to the present invention, the effective channel length can be controlled only depending on the pattern accuracy of the photo process, so that a submicron poly-Si TFT can be formed with high reproducibility. The thickness of the polycrystalline silicon layer forming the channel region is about 500 mm or less, preferably 50 mm or less.
By reducing the thickness to about {circle around (2)} to about 250}, high performance such as reduction of off-state current and reduction of Vth can be realized. However,
In the conventional structure, the source / drain region is formed in the same thin film as the polycrystalline silicon in the channel region.
There is also a problem that the sheet resistance becomes high. However, in the present invention, since the source / drain region is formed separately from the channel region, the thickness of the channel region and the thickness of the source / drain region can be set independently, and the above problem can be avoided.

FIG. 2 is an example of a manufacturing process diagram of the semiconductor device according to the embodiment of the present invention. FIG. 2 shows a simple application example (stacked CMOS) to a three-dimensional transistor.

In FIG. 2, (a) shows p-w on a silicon substrate 201.
This is a step of forming the ell region 202 and forming the element isolation region 203 by the LOCOS oxidation method.

(B), after forming the gate insulating film 204, the gate electrode 205
Is formed using poly-Si or the like as an element material, and then patterned into a predetermined shape to form an n ⁺ diffusion layer 206 forming source / drain regions.

(C), forming an insulating layer 207 forming a gate insulating film;
A contact hole is opened, and a polycrystalline silicon layer 210 doped with impurities forming a source / drain region is formed to a thickness of 500 to 4000
工程 This is a step of forming a pattern and forming a pattern in a predetermined shape. As a method for forming the polycrystalline silicon layer, plasma CV
There is a method of forming a polycrystalline silicon film with a film thickness of about 500 to 3500 at a low temperature of about 300 ° C. to about 450 ° C. by a D method (PCVD method). The following is an example of the film forming conditions. Monosilane (SiH ₄ ), dichlorosilane (SiH ₂ C)
l ₂ ) and H ₂ , and the mixing ratio is, for example, SiH ₄ : SiH ₂ Cl ₂ = 1: 20
To 1: about _{200, SiH 4: H 2 =} 1: 100~1: set to about 1000,
Diborane (B ₂ H ₆ ) or the like is used as a doping gas, and for example, SiH ₄ : B ₂ H ₆ is mixed at a mixing ratio of about 1: 0.002 to 1: 0.04. The substrate temperature is maintained at about 300 ° C. to 450 ° C., rf power is applied to decompose the reaction gas, and a low-resistance polycrystalline silicon doped with impurities is formed. The sheet resistance of the polycrystalline silicon thus formed is 60 to 100 Ω at a thickness of 1000 mm.
/ □, low-resistance polycrystalline silicon could be formed at a low temperature. When the film is formed at a relatively high substrate temperature of about 450 ° C. to 600 ° C., the above-mentioned sheet resistance value is 40 to 60.
It can be lowered to about Ω / □. The method for forming polycrystalline silicon is not limited to this. For example, low-resistance polycrystalline silicon can be formed by a solid-phase growth method. Hereinafter, an example will be described. First, an a-Si film doped with impurities is formed by a PCVD method. The reaction gas is
SiH4 and H2 gases were used, and B2H6 gas was used as a doping gas. Substrate temperature is 150-250 ° C, internal pressure is 0.8 Torr, 13.56
A MHz rf power supply was used. The flow ratio of B2H6 and SiH4 is [B2H6]
/ [SiH4] = 3 × 10−3 to 4 × 10−2. After forming the a-Si film, pre-annealing is performed at 450 ° C. for 30 min. N2 to remove H2 contained in the a-Si. This is because if solid phase growth annealing is performed while H2 is contained in a-Si, H2
This is for the purpose of preventing the portion from which has been removed from becoming a pore and becoming a porous film. Thereafter, the process proceeds to a solid phase growth annealing step. Annealing conditions are 4 in N2 gas at 550-650 ° C.
~ 72 hours. By this solid phase growth annealing, a-
Si is polycrystallized, and the average grain size of Si grains in the gate electrode is reduced to about 1 to 3 μm, and many grains having a grain size of 5 μm or more appear. This completes p + poly-Si. Annealing is not limited to N2 annealing, but may be laser beam annealing, halogen lamp annealing, or the like. When a laser beam or a halogen lamp is used, the annealing time can be reduced as compared with N2 annealing. During the annealing step, the B atoms mixed in during the a-Si film formation are also activated at the same time. As a result, the resistivity of the polycrystalline silicon is p + poly−
The resistance is reduced to about 1 to 3 × 10 −3 Ω · cm by Si. Next, N2 annealing, lamp annealing, or laser annealing at about 700 ° C. to 800 ° C. is performed as necessary to more completely activate the impurities in the source and drain regions. By this activation annealing, complete activation of B atoms and an increase in the crystallization rate are simultaneously achieved, and the resistivity of p + poly-Si is 1-5 × 10 −4 Ω · cm (10-50 Ω at a thickness of 1000 °).
/ □).

(D), after performing light etching for the purpose of cleaning the surface of the insulating layer 207 forming the gate insulating film, forming the polycrystalline silicon layer 208, and subsequently reducing defects existing at crystal grain boundaries. This is a step of performing a hydrogenation treatment such as a hydrogen plasma treatment for the purpose. As a method for forming a polycrystalline silicon layer, a substrate temperature of 300 ° C. to 450 ° C. is used by a plasma CVD method (PCVD method).
It is effective to form a polycrystalline silicon film at a low temperature of about 100 ° C. with a film thickness of about 50 ° to 1500 °. In the PCVD method, usually, monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), or the like is used as a reaction gas.
At a substrate temperature of about 50 ° C., at most microcrystalline silicon of amorphous silicon is formed, and it is difficult to form high-quality polycrystalline silicon. However, by mixing an appropriate amount of a reaction gas containing elements such as fluorine (F) and chlorine (Cl) in addition to the above-mentioned SiH ₄ , Si ₂ H _{6 and the} like, a high-quality polycrystalline silicon film is obtained. Can be formed at a low temperature. By mixing an appropriate amount of a reaction gas containing elements such as fluorine (F) and chlorine (Cl) in addition to SiH ₄ and Si ₂ H ₆ as a reaction gas, a high-quality polycrystalline silicon film can be formed at a low temperature. . An example of the film forming conditions is shown below. As a reaction gas, Si
Using H ₄ , dichlorosilane (SiH ₂ Cl ₂ ), and H ₂ , the mixing ratio is, for example, about SiH ₄ : SiH ₂ Cl ₂ = 1: 20 to 1: 200, and SiH ₄ : H ₂ = 1:
The substrate temperature is set at about 100 to 1: 1000, the substrate temperature is maintained at about 300 to 450 ° C., and rf power is applied to decompose the reaction gas to form a polycrystalline silicon film. Regarding the film thickness, it is known that when the thickness of the polycrystalline silicon layer is reduced, the off current decreases and Vth (threshold voltage) decreases. Therefore, the thickness of the polycrystalline silicon layer is desirably 500 ° or less, and
Å is particularly desirable. Therefore, it is particularly important to form such thin film and high quality polycrystalline silicon. When the substrate temperature is 300 ° C or lower, the crystallization rate is low,
<220> No orientation is observed, but the substrate temperature is 400 ° C to 450 ° C.
At a temperature of about 50 ° C, a crystallization rate of 9
At 8% or more, high-quality polycrystalline silicon oriented in <220> can be formed. In terms of increasing the crystallization rate, a film formed at a substrate temperature of about 450 ° C. to 600 ° C. is more favorable, and a crystallization rate of 99.5% or more can be achieved.
This is effective for increasing the ON current of T and reducing the OFF current.

As described above, according to the present invention, a high-quality polycrystalline silicon film can be formed at a low temperature, so that a high-performance three-dimensional IC including the stacked CMOS shown in this embodiment can be manufactured at a low temperature. . In this example, SiH ₂ Cl was used as the reaction gas.
_{Although the} case of using ₂ has been described, the present invention is not limited to this. For example, SiCl ₄ , SiH ₂ Cl ₂ , SiHCl ₃ , Cl ₂ , SiF ₄ , SiH
Etching reaction gas containing at least one element of F (fluorine) or Cl (chlorine) such as F ₃ , SiH ₂ F ₂ , SiH ₃ F, Si ₂ F ₆ , F ₂ , HCl and SiH ₄ By mixing an appropriate amount of a reaction gas such as Si ₂ H ₆ or Si ₃ H ₈ , high-quality polycrystalline silicon can be formed at a low temperature.

The field-effect mobility of a polycrystalline silicon TFT (N-channel) formed by using the method of manufacturing a semiconductor device according to the present invention is about 150 to ²⁰⁰ cm ² / V · sec, and the on / off ratio is 8 to 9 digits (Ion: Vd = 5 V, Vg = 10 V, Ioff: Vd = 5 V, Vg = 0 V), and a high-performance poly-Si TFT could be formed at a low temperature.

Also, doping the channel region with an impurity,
Means for controlling (threshold voltage) is also very effective.
In a polycrystalline silicon TFT formed by the solid-phase growth method, Vth of the N-channel transistor tends to shift in the depletion direction, and P-channel transistor tends to shift in the enhancement direction. When the TFT is hydrogenated, the tendency becomes more remarkable. Therefore, if the channel region is doped with an impurity of about 10 ¹⁵ to 10 ¹⁹ / cm ³ , Vt
h shift can be suppressed. For example, there is a method in which an impurity such as B (boron) is implanted at a dose of about 10 ¹¹ to 10 ¹³ / cm ^{2 by} an ion implantation method or the like.

It should be noted that the present invention can be applied not only to the stacked CMOS shown in the embodiment of FIGS.
This is a very effective manufacturing method when a semiconductor element such as a photoelectric conversion element such as an electrostatic induction transistor, a solar cell or an optical sensor is formed using a polycrystalline semiconductor as an element material.

[Effects of the Invention] As described above, according to the present invention, a polycrystalline silicon film having a large grain size and a high crystallization rate can be formed at a low temperature by a simpler manufacturing process. As a result, a high-performance semiconductor element can be formed on an insulating amorphous material, and a stacked semiconductor device such as a three-dimensional IC can be manufactured at a low temperature by a simple process.

In addition, the present invention is shown in the embodiment of FIGS. 1 and 2.
In addition to TFT, it can be applied to insulated gate type semiconductor devices in general, and semiconductor devices such as bipolar transistors, electrostatic induction type transistors, photoelectric conversion devices such as solar cells and optical sensors, etc. are formed using polycrystalline semiconductors as device materials. This is an extremely effective manufacturing method.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. 2 (a) to 2 (d) are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a sectional view of a conventional semiconductor device. 101, 201, 301 ... silicon substrate 102, 202, 302 ... p-well region 103, 203, 303 ... element isolation region 104, 204, 304 ... gate insulating film 105, 205, 305 ... gate electrode 107, 207, 307 ... gate insulating film 108, 208, 308 ... polycrystalline silicon layer 109, 209, 309 ... source / drain region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/786 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/092 H01L 29/784 H01L 27/00 301 H01L 27/10 381

Claims (1)

(57) [Claims] A step of forming a gate electrode on the substrate; a step of forming an insulating film forming a gate insulating film on the gate electrode; and forming a first silicon layer serving as a source / drain region on the insulating film. Forming, patterning so as to remove the first silicon layer on the gate electrode, and annealing the first silicon layer to activate impurities. A method of manufacturing a semiconductor device, comprising: forming a second silicon layer serving as a channel on the first silicon layer.