JP3035815B2 - Jitter generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter generator for outputting a modulated signal subjected to phase modulation and for calibrating and indicating the degree of modulation of the modulated signal.

[0002]

2. Description of the Related Art Various circuits and devices for handling digital signals may not operate properly if an input signal has a phase fluctuation (jitter). For this reason, it is necessary to measure in advance the maximum amount of jitter (jitter tolerance) at which a circuit or device can operate normally.

In order to perform such a measurement, conventionally,
The jitter generator 10 shown in FIG. 6 is used. The jitter generator 10 inputs a modulation signal having a constant amplitude generated by a modulation signal generator 11 to a variable attenuator 12, and varies the amount of attenuation of the variable attenuator 12 by a modulation degree setting device 13 to thereby adjust the modulation signal. The amplitude is varied and input to the phase modulator 14, and a clock signal phase-modulated by the modulation factor indicated by the indicator 13a of the modulation factor setting device 13 is output from the output terminal 16 as a modulated signal. ing.

[0004] The jitter generator 10 constructed as described above.
When measuring the jitter tolerance of the circuit under test using
A pattern signal synchronized with the clock signal output from the jitter generator 10 is input to a circuit under test and the like,
The modulation factor is increased by the modulation factor setting device 13 to determine the modulation factor when an abnormality (error) occurs in the circuit under test.

Therefore, in order to perform such a measurement with high accuracy, the modulation degree of the clock signal actually output from the jitter generator 10 and the set modulation degree must coincide with high accuracy.

However, the former is susceptible to fluctuations due to environmental changes such as temperature, changes over time, and the like, resulting in a difference in the degree of modulation between the two. This difference in the degree of variability also occurs in a jitter generator equipped with a modulation meter, and a difference occurs between the modulation degree of the clock signal actually output and the modulation degree indicated by the modulation meter.

For this purpose, conventionally, as shown in FIG. 7, the output terminal 16 of the jitter generator 10 is connected to the spectrum analyzer 1, and the modulation of the phase-modulated signal is performed as shown in FIG. The calibration operation of the jitter generator 10 was performed using the Bessel function curve B representing the relationship between the degree and the level of the carrier component of the signal (frequency of the signal before phase modulation) (FIG. 8 shows the phase-modulated signal). Shows the relationship between the modulation degree of the carrier component and the level of the carrier component).

That is, the modulation factor of the jitter generator 10 is gradually increased from zero by manual operation, and the jitter generation when the carrier component of the spectrum displayed on the screen of the spectrum analyzer 1 becomes almost zero is generated. Apparatus 10
Of the Bessel function curve B in FIG.
Have been calibrated to match the modulation factors m1, m2,.

[0009]

However, in the above-mentioned calibration method, a spectrum analyzer is required every time the calibration is performed, and the connection work and operation become complicated. However, there was an inconvenience that a spectrum analyzer had to be brought.

[0010] Therefore, there is a demand for a jitter generator capable of checking the authenticity of data at any time, with a simple structure, easy operability, and anytime, especially when measuring at the site of equipment maintenance or construction.

An object of the present invention is to provide a jitter generating apparatus which solves this problem.

[0012]

In order to achieve the above object, a jitter generating apparatus according to the present invention generates a modulated signal, and modulates the amplitude of the modulated signal to output the modulated signal. Phase modulating means (24 to 26) for phase-modulating a clock signal with a modulation signal from said modulation signal output means and outputting said phase-modulated clock signal.
And a modulation factor instructing means (44, 46) for instructing the modulation factor of the clock signal output from the phase modulating device. A filter (36) for extracting the carrier component, a level detecting means (37) for detecting the level of the carrier component extracted by the filter, and a level of the carrier component detected by the level detecting means is minimized. (53), a Bessel function memory (56) in which a theoretical value of the degree of modulation at which the level of the phase-modulated signal is minimized is stored in advance, and a carrier component is detected by the minimum detection means. A modulation degree varying means (51) for changing the amplitude of the modulation signal so that a level minimum is detected; Correction data calculating means (57) for calculating correction data for making the indicated value specified by the modulation degree indicating means coincide with the theoretical value of the modulation degree stored in the Bessel function memory (56); Correction means (45) for instructing the modulation degree instructing means to indicate the modulation degree calibrated based on the correction data calculated by the arithmetic means is provided integrally, and the automatically calibrated modulation degree is indicated. I have.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a jitter generator 20 according to one embodiment.

In FIG. 1, a modulation signal generator 21 forms a modulation signal generation means of this embodiment together with a variable attenuator 22, and generates a sine wave modulation signal having a constant amplitude K at a certain frequency to be variable. Output to the attenuator 22.

The variable attenuator 22 is a programmable attenuator whose attenuation changes in accordance with the modulation degree setting signal M. The variable attenuator 22 converts the amplitude of the modulation signal from the modulation signal generator 21 into the modulation degree setting signal M. And output to the switch 23.

The switch 23 converts the modulation signal output from the variable attenuator 22 into a frequency designation signal F of the first, second, and third phase modulators 24, 25, and 26. Input to the specified phase modulator.

The first phase modulator 24 phase-modulates a clock signal having a frequency f1 (for example, about 155.52 MHz) with a modulation factor corresponding to the amplitude of the modulation signal input via the switch 23, and outputs the clock signal. The second phase modulator 25 phase-modulates and outputs a clock signal having a frequency f2 (= 4 · f1) at a modulation factor corresponding to the amplitude of the modulation signal input via the switch 23, and outputs a third phase signal. The modulator 26 is connected to the switch 2
The clock signal having a frequency f3 (= 4 · f2) is phase-modulated at a modulation factor corresponding to the amplitude of the modulation signal input through the output terminal 3 and output. Each of the frequencies f1 to f3 is a frequency corresponding to the transmission speed currently used for data transmission.

As shown in FIG. 2, for example, each of the phase modulators 24 to 26 includes a voltage controlled oscillator 27 for oscillating and outputting a clock signal, and a frequency divider 28 for dividing the frequency of the clock signal output from the voltage controlled oscillator 27. A phase comparator 29 for detecting a phase difference between the frequency-divided output of the frequency divider 28 and the reference signal R and outputting a voltage signal corresponding to the phase difference;
And an adder 30 that adds the modulation signal to the output signal of the first control unit and inputs the result to the voltage controlled oscillator 27. The output voltage of the phase comparator 29 is output from each of the phase modulators 24 to 26 as a monitor signal corresponding to the degree of modulation of the clock signal output from the voltage controlled oscillator 27. In other words, this monitor signal is also a jitter amount according to the modulation degree.

The monitor signals of the phase modulators 24 to 26 are as follows:
Receiving the frequency designation signal F, the signal is input to the A / D converter 32 via the switch 31 linked with the switch 23, converted into a digital signal, and output to the modulation degree output means 44 described later.

On the other hand, the first to third phase modulators 24 to 26
Is output to the output terminal 34 and the frequency divider 35 via the switch 33 which interlocks with the switch 23 in response to the frequency designation signal F.

The frequency divider 35 receives the frequency designation signal F and operates so as to interlock with each of the switches 23, 31, and 33 so that the frequency dividing ratio N
When each switch is connected to the first phase modulator 24, the frequency division ratio N is set to 1, and each switch is connected to the second phase modulator 25. When the switches are connected to the third phase modulator 26, the frequency division ratio N is set to four.

The clock signal divided by the frequency divider 35 is input to the band-pass filter 36. The pass center frequency of the band pass filter 36 is set to the frequency f1 of the clock signal of the first phase modulator 24, and the pass bandwidth is set to be sufficiently smaller than twice the frequency fm of the modulation signal. Therefore, the band-pass filter 36 outputs the carrier component of the clock signal output from the first phase modulator 24 and the signal obtained by dividing the clock signal output from the second phase modulator 25 by ４. Carrier component,
The clock signal output from the third phase modulator 26 is 1
Only the carrier component of the signal divided by / 16 is extracted, and the sideband component generated by the phase modulation is removed.

The carrier component output from the band pass filter 36 is input to a level detector (detection circuit) 37, and the level is detected.

The output signal of the level detector 37 is converted into a digital signal by the A / D converter 38 and output to a calibration processing section 50 described later.

The modulation degree setting means 40 changes the modulation degree setting signal M for the variable attenuator 22 in accordance with the operation of the modulation degree setting operation section 41. Further, the modulation degree setting means 40
Receives the control signal from the calibration processing unit 50 and changes the modulation factor setting signal M.

The frequency designating means 42 changes the frequency designating signal F in accordance with the operation of the frequency designating operation unit 43 or the control signal from the calibration processing unit 50 to change each of the switches 23, 3
1, 33 and the frequency division ratio of the frequency divider 35 are switched.

The modulation degree output means 44 is provided for each phase modulator 24.
Display unit 4 displays the modulation degree of the clock signal output from
6 is configured to receive a monitor signal output from the A / D converter 32 and output a modulation degree corresponding to the value of the monitor signal. For example, the modulation factor corresponding to the monitor signal value is stored in the memory using the value of the monitor signal as an address, and the modulation factor corresponding to the monitor signal is read from the memory, or the monitor signal is multiplied by a constant coefficient. It is configured to convert into a modulation degree and output.

The output value of the modulation degree output means 44 needs to match the modulation degree of the clock signal output from each of the phase modulators 24 to 26. The modulation characteristics of modulators 24-26 and A /
If the characteristic of the D converter 32 changes and the relationship between the actual modulation degree of the clock signal and the monitor signal deviates, the output value of the modulation degree output means 44 and the modulation degree of the clock signal actually output are changed. An error occurs between them.

For this purpose, in this embodiment, the output of the modulation degree output means 44 is corrected by the correction means 45, and the corrected value is displayed on the display 46.

The correction means 45 receives correction data necessary for eliminating the error from the calibration processing unit 50, and corrects the output of the modulation degree output means 44 based on the correction data. The correction means 45 converts the correction data of the frequency band designated by the frequency designation signal F into a calibration processing unit 50.
To receive from.

The calibration processing section 50 checks the difference between the output value of the modulation factor output means 44 and the actual modulation factor when the power of the jitter generator 20 is turned on, for example, and obtains correction data corresponding to the difference. The modulation degree setting means 40 controls the modulation degree varying means 51 for monotonically decreasing the attenuation of the variable attenuator 22 from the maximum, and the frequency designating means 42 for controlling each of the switches 23, 31, 33 and Circulator 35
Frequency switching means 52 for varying the frequency division ratio of the signal, minimum detection means 53 for detecting that the level of the signal output from the A / D converter 38 has become minimum and outputting a detection signal,
An instruction value memory 54, an instruction value writing means 55 which receives a detection signal output from the minimum detection means 53 which has detected the level minimum, and writes an output value of the modulation instruction means 44 into the instruction value memory 54 at that time. The theoretical value m of the modulation factor at which the Bessel function curve B shown in FIG. 7 becomes zero (the signal level is minimal)
A Bessel function memory 5 in which 1, m2,.
6, and a correction for matching the actual modulation degree of the clock signal with the modulation degree displayed on the display 46 based on the value stored in the indicated value memory 54 and the value stored in the Bessel function memory 56. It is composed of a correction data calculating means 57 for calculating data, and a correction data memory 58 for storing the correction data calculated by the correction data calculating means 57.

FIG. 3 is a flowchart showing a processing procedure of the calibration processing section 50. Hereinafter, the calibration process of the jitter generator 20 will be described with reference to FIG.

When the power is turned on to the jitter generator 20, the calibration process starts, and the switches 23, 31,
33 is connected to the first phase modulator 24 side, and the frequency divider 35
Is set to 1 and the attenuation of the variable attenuator 22 is set to the maximum (substantially unmodulated state) (S1 to S
3).

Then, the attenuation of the variable attenuator 22 gradually decreases, and the degree of modulation increases (S4). As the degree of modulation increases, the level of the carrier component of the clock signal output from the first phase modulator 24 gradually decreases according to the Bessel function curve B shown in FIG. When the first minimum of the level of the carrier component is detected, the output value X1 of the modulation output means 44 at this time is stored in the instruction value memory 54 (S5, S6).

When the modulation degree is further increased and the twentieth minimum is detected, the output value X20 of the modulation degree output means 44 at that time is stored in the instruction value memory 54 (S7 to S).
9).

Then, correction data is calculated from the values X1 and X20 stored in the instruction value memory 54 and the theoretical modulation values m1 and m20 stored in the Bessel function memory 56.

That is, the carrier component of the clock signal is the first
The values X1 and X20 are on the straight line Pa shown in FIG. 4 with respect to the true modulation degrees m1 and m20 at the time of the minimum at the second and twentieth times, and the straight line Qa of m = X (the straight line when there is no error) ), The slope a of the straight line Pa and m = 0
The value b at the time is calculated by the following equation: a = (X20−X1) / (m20−m1) b = X1−m1 · (X20−X1) / (m20−m1) The correction data when the first phase modulator 24 is used is stored in the correction data memory 58 (S10, S11).

Next, each of the switches 23, 31, and 33 is set to the second
Is switched to the phase modulator 25 side, the frequency division ratio N of the frequency divider 35 is switched to 4, and the attenuation of the variable attenuator 22 is gradually decreased from the maximum similarly to the above. The output value Y1 of the modulation factor output means 44 when the output of the D converter 38 first becomes the minimum and the output value Y5 when the output becomes the fifth minimum are stored in the instruction value memory 54 (S12). To S20).

In this case, since the clock signal output from the second phase modulator 25 is frequency-divided by 1/4, the actual modulation degree is multiplied by the division ratio of m1 (in this case, 4 times). )
, The modulation degree of the signal output from the frequency divider 35 becomes m1, and the level of the signal output from the band-pass filter 36 is minimized. Therefore, the values Y1 and Y5 stored in the instruction value memory 54 are m1,
It is necessary to match the value to four times m5.

For example, the values Y1 and Y5 for the true modulation factors 4 · m1 and 4 · m5 are on the straight line Pb shown in FIG.
When the deviation is from the straight line Qb of m = Y (the straight line when there is no error), the slope c of the straight line Pb and the value d when m = 0
C = (Y5−Y1) / 4 · (m5−m1) d = Y1−m1 · (Y5−Y1) / (m5−m1), and this (c, d) is calculated by the second Is stored in the correction data memory 58 as correction data when the phase modulator 25 is used (S21, S22).

Next, the switches 23, 31, and 33 are set to the third
, The frequency dividing ratio N of the frequency divider 35 is switched to 16, the attenuation of the variable attenuator 22 is gradually reduced from the maximum, and the A / D converter The output value Z1 of the modulation factor output means 44 when the output of 38 first becomes the minimum and the output value Z2 when the output of the modulation 38 becomes the second minimum are stored in the instruction value memory 54, and are not shown. Similarly, the gradient e of the characteristic line of the output value of the modulation factor output means 44 with respect to the theoretical value of the modulation factor and the value f when m = 0 are given by: e = (Z2−Z1) / 16 · (m2−m1) f = Z1−m1 · (Z2−Z1) / (m2−m1), and (e, f) obtained by this calculation is the correction data when the third phase modulator 26 is used. Is stored in the correction data memory 58 (S23 to S33).

In this way, the correction data for each phase modulator is automatically stored in the correction data memory 58, and the calibration process is completed. Then, the jitter is actually generated and the measurement can be performed. The frequency division ratios of the switches 23, 31, 33 and the frequency divider 35 are initialized (for example, the first phase modulator 2).
4) (S34).

Therefore, the first phase modulator 24 is modulated according to the signal from the modulation degree setting operation section 41, and a monitor signal corresponding to the modulation degree is transmitted from the A / D converter 32 to the modulation degree output means 44. And the output value of the modulation degree output means 44 is input to the correction means 45 and corrected by the correction data (a, b) of the correction data memory 58 corresponding to the first phase modulator 24.

Here, the correction means 45 subtracts the correction data b (or d, f) from the output value of the modulation degree output means 44, and divides the subtraction result by the correction data a (or c, e). By this correction operation, the straight line Pa shown in FIG.
Each of the above points falls on the straight line Qa, and the correction result and the actual modulation degree match with high accuracy at an arbitrary point, and the modulation degree displayed on the display 46 is actually output. This will match the modulation degree of the clock signal with high accuracy.

Therefore, the frequency is designated by the frequency designation operation unit 43 and the modulation degree displayed on the display 46 is set to a desired value by the modulation degree setting operation unit 41, so that the display 4
The clock signal accurately phase-modulated with the modulation degree indicated by 6 can be output, and the jitter tolerance measurement and the like can be accurately performed.

In the jitter generator 20, since a frequency divider 35 capable of varying the frequency division ratio is provided between the phase modulators 24 to 26 and the band-pass filter 36, the frequency band of the clock signal is different. A common band-pass filter 36 can be used for a plurality of phase modulators, and the frequency ratio of the carrier and the sideband is widened by frequency division. Easy to do. Further, since the transmission speed of the data transmission has an integral multiple of 4 times or 16 times as described above, the configuration of the frequency divider itself becomes easy.

In the above description, the calibration process is started when the power of the apparatus is turned on. However, the calibration process may be started at an arbitrary timing by key operation or the like. Further, in the jitter generator 20, since the level of the carrier component of the clock signal output from the phase modulators 24 to 26 can be constantly monitored, for example, the modulation degree setting operation section 41 for measurement or the automatic measurement control section (not shown) for measurement. If the minimum of the carrier level is detected by the minimum detection means 53 while the modulation degree is being changed, the output value of the modulation degree output means 44 at that time is stored, and the stored value and the Bessel function memory 56 are stored. Compared with the theoretical value of the modulation factor, if there is a difference between them (or if the difference is equal to or more than a predetermined value), the correction data b (or d, f) can be finely corrected with the difference. When a difference occurs, the process may shift to the above-described calibration process.

As described above, the A / D converter 3 does not calculate and correct the output value of the modulation factor output means 44 with the correction data.
2 to correct the offset and sensitivity,
When the modulation factor is obtained from the monitor signal by calculation, the coefficient of the calculation is corrected, and the modulation factor output means 4
4 may be displayed on the display 46 as it is.

Also, in the above description, when the power is turned on, the first to the first are set.
Although the correction data for the third phase modulators 24 to 26 is automatically obtained, the correction data may be obtained only for the phase modulator in the frequency band specified by the frequency specification operation unit 43, for example. .

[0050]

[Other Embodiments] In the above-described embodiment, a common band-pass filter 36 can be used for a plurality of frequency band phase modulators by using a frequency divider 35. In one case, the frequency divider may be omitted, and if the frequency band of the clock signal is very high and the bandpass filter cannot sufficiently extract only the carrier component, the clock output from the phase modulator may be omitted. The signal and the local oscillation signal may be mixed and converted to a lower frequency, and then the carrier component may be extracted by a band-pass filter.

In the above embodiment, each phase modulator 2
And a modulation degree output means for displaying a modulation degree corresponding to the monitor signal output from each of the monitor signals on the display unit. The output value of the modulation degree output means is actually output from the phase modulator. Was corrected to match the degree of modulation of the clock signal to be performed, but this does not limit the present invention,
For example, in the case of a jitter generator that instructs a display unit the modulation degree setting signal M set by the modulation degree setting unit 40 as the modulation degree, the modulation degree setting signal M when the level of the carrier component becomes minimum is obtained. The indicated value is stored in the Bessel function memory 5
Then, correction data for matching the modulation degree stored in No. 4 is obtained, and the modulation degree setting signal may be corrected using the correction data.

[0052]

As described above, the jitter generator according to the present invention extracts the carrier component of the clock signal output from the phase modulating means by using a filter, detects the level of the carrier component, and reduces the level to a minimum. The amplitude of the modulation signal is varied, and when the level becomes minimum, correction data for matching the modulation value indicated value to the theoretical value of the modulation depth stored in advance is obtained. Is corrected so that the modulation degree indicated by the reference numeral and the modulation degree instruction value match.

For this reason, the complicated connection work and operation of connecting the spectrum analyzer every time of calibration as in the related art is not required, and the measurement of the existing device can be easily and accurately performed at the installation site.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a main part of the embodiment.

FIG. 3 is a flowchart showing a procedure of a calibration process;

FIG. 4 is a diagram showing a relationship between a modulation factor and an indicated value.

FIG. 5 is a diagram showing a relationship between a modulation factor and an indicated value.

FIG. 6 is a diagram showing a conventional apparatus and a system for calibration.

FIG. 7 is a diagram showing a Bessel function curve;

[Explanation of symbols]

 REFERENCE SIGNS LIST 20 Jitter generator 21 Modulated signal generator 22 Variable attenuator 24 to 26 Phase modulator 35 Divider 36 Band pass filter 37 Level detector 44 Modulation degree output means 45 Correction means 46 Display 50 Calibration processing unit 51 Modulation degree variable Means 53 Minimum detection means 54 Instruction value memory 55 Instruction value writing means 56 Bessel function memory 57 Correction data calculation means 58 Correction data memory

Claims (1)

(57) [Claims] 1. A modulation signal output means (21, 22) for generating a modulation signal, variably outputting the amplitude of the modulation signal, and phase-modulating a clock signal by a modulation signal from the modulation signal output means. Phase modulation means (24 to 26) for outputting the phase-modulated clock signal; and modulation degree indicating means (44, 46) for indicating the degree of modulation of the clock signal output from the phase modulation means. A filter (36) for extracting a carrier component from the clock signal phase-modulated by the phase modulation means, and a level detection means (37) for detecting a level of the carrier component extracted by the filter. A minimum detecting means (53) for detecting that the level of the carrier component detected by the level detecting means has been minimized;
A Bessel function memory (56) in which a theoretical value of a modulation degree at which the level of the phase-modulated signal is minimized is stored in advance, and the minimum detection means detects the minimum of the level of the carrier component. A modulation degree varying means (51) for changing the amplitude of the modulation signal; and a modulation degree stored in the Bessel function memory (56), the instruction value designated by the modulation degree designation means when the minimum is detected. Correction data calculating means (57) for calculating correction data for making the modulation value coincide with the theoretical value, and correction for instructing the modulation degree instructing means to the modulation factor calibrated based on the correction data calculated by the correction data calculating device. A jitter generating apparatus integrally comprising a means (45) and indicating an automatically calibrated modulation degree.