JP3034561B2 - Frame phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] An input time-division multiplexed multi-frame signal is time-converted within a frame by a time switch synchronized with a first clock signal, and the output thereof is multiplied by an integer multiple of the first clock. A frame phase synchronizing circuit for a signal processing device in which a signal is processed by a second clock having a frequency, wherein a result of processing a signal by one of two clocks is processed by a high frequency clock synchronized with the other frequency. The purpose of the present invention is to provide a frame phase synchronization circuit that maintains a predetermined frame phase so that a malfunction does not occur when the input signal is written into a communication memory of a time switch.
A first counter that counts the first clock and supplies the count value as a write address to the call memory; counts a second clock to generate an output having the same frequency as the first clock and a frame signal; And a second counter for supplying a value obtained by converting the count value by the control memory to the communication memory as a read address, wherein the second counter is configured to control the start of the frame during a period in which the first counter has a specific number of frames. Is reset by a circuit that detects the state of
The output signal of the communication memory is processed by the clock, the frame signal, and the second clock output from the counter.

[Industrial Application Field] The present invention relates to a first clock having a frequency synchronized with an input signal of a multi-frame configuration, and n of the first clock.
Second frequency synchronized with the first clock at twice the frequency
The present invention relates to a frame phase synchronizing circuit for synchronizing a clock with a frame phase.

In the technology of time division multiplex transmission, signal processing is performed by exchanging the time position of each channel signal of a digital multiplex signal having a multi-frame configuration in a frame.

In such signal processing of a time division multiplexed signal, it is necessary to perform signal processing using a clock having a higher frequency than a clock synchronized with the frequency of the input signal for processing the input signal. However, although the clock synchronized with the input signal and the high-frequency clock used for signal processing are frequency-synchronized, if the phase is not always constant, the timing of sampling the signal to be processed is not sufficient. It may become unstable and malfunction.
There is a need for a circuit that achieves accurate phase synchronization.

[Prior Art] FIG. 3 is a system configuration diagram of a conventional example, FIG. 4 is a configuration of a time switch of a conventional example, FIG. 5 (a) is a configuration of phase synchronization of a conventional example, and FIG. FIG. 5 (c) is a timing chart during normal operation, and FIG. 5 (c) is a timing chart during unstable operation.

FIG. 3 shows a system configuration for processing and outputting a time-division multiplexed signal having a multi-frame configuration.

The signal operating device 30 shown in the figure performs some kind of signal processing on the serial multiplexed data input from the data highway 31, and converts the serial multiplexed data into data highway 32 as serial multiplexed data.
Device to send to The signal input from the data highway 31 is a multiplex signal in which one frame is composed of a large number (for example, 32) of time slots (channels) and one multi-frame is composed of a large number of frames (for example, 32 frames). One time slot is composed of a plurality of bits (for example, 8 bits) and represents, for example, one line of voice PCM signal.

The multiplexed signal input from the data highway 31 is output to the circuit A by switching the channel position in each frame by the time switch TSW1 in the signal operation device 30. The circuit A includes a signal processor (DSP: digital signal processor), performs processing such as time compression processing, and outputs the processed signal to the next time switch TSW2. The time switch TSW2 inserts the input multiplexed signal into the data highway 32 by exchanging the time position in the frame again.

The clock CK1 supplied to each circuit of the signal operation device 30
Is a clock whose phase is synchronized with the bit signal of the multiplex signal on the data highway 31 and is input from the outside.
FC is a frame signal representing the beginning of a frame, MFC is a multi-frame signal representing the beginning of a multi-frame, CK2 is an externally input clock necessary for high-speed operation of the circuit A, and is n times as large as CK1. With a frequency of

The configuration of the time switches TSW1 and TSW2 will be described with reference to the configuration of the time switch TSW1 shown in FIG.

In FIG. 4, a counter CT1 counts a clock CK1 having a frequency of a serial multiplexed signal (frequency of a bit signal) input from a data highway to generate an address signal. Each digital data input from the data highway by this address signal is transferred to the speech memory SP.
Write to M sequentially.

The data written to the call memory SPM is the counter CT1
Is supplied to the control memory CM, and the address of the conversion destination written in advance for each address of the control memory CM is read and supplied as a read address to the communication memory SPM. As described above, time exchange is realized by reading at a different time position from the time of writing. The multi-frame signal MFC is supplied to the load (LOAD) input of the counter CT1, and every time the multi-frame signal MFC appears, data “0” is loaded and the counter CT1 is reset.

When such a time switch is used, the phase of the serial multiplexed data input from the time switch TSW1 input to the circuit A shown in FIG. 3 is synchronized with the clock CK1. Here, for the circuit A, since the clock CK2 that defines the processing speed performs the signal processing, it generally requires a higher speed than the clock CK1 that defines the data input / output speed. Frequency synchronization between clocks CK1 and CK2 (CK2 frequency = n times CK1 frequency)
But the phase relation is not specified in many cases.

In that case, when the circuit A requires phase synchronization between the clocks CK1 and CK2, a malfunction occurs depending on the configuration of FIG.

In order to solve such a problem, a configuration of phase synchronization as shown in FIG. 5A has been conventionally used.

In FIG. 5 (a), the time switch TSW1 and the circuit A
Corresponds to the circuit shown in FIG.

The normal operation of the configuration of FIG. 5A will be described with reference to the timing chart of FIG.

The data (DATA) output after the time exchange of the input data signal is performed by the clock CK1 and the multi-frame signal MFC by the time switch TSW1 is input to the data input terminal (denoted by D) of the flip-flop circuit FF0. As shown in FIG. 5B, an output of the data (DATA) is generated at the timing when the clock CK1 changes from high (H) to low (L) by the operation in the time switch TSW1.

Similarly, the clock CK1 is input to the flip-flop circuit FF1, and the frame signal FC (representing the start of each frame) is input to the flip-flop circuit FF2. Each of these flip-flop circuits FF0 to FF2 is driven by a clock input terminal (indicated by CK) by a clock CK2 that defines the processing speed of the circuit A.

In this case, if there is a timing relationship as shown in FIG. 5 (b), that is, a change point of FC, CK1 and DATA does not coincide with the rising edge of CK2, a flip-flop as shown in FIG. The output of circuits FF0 to FF2 is clock CK
It becomes a signal synchronized with the phase of 2. These signals are supplied to each input terminal, data (DATA), clock ck1, and frame signal fc of the circuit A in FIG. 5 (a), and the circuit A executes signal processing by the clock ck2 (synchronous with CK2) without error. can do.

On the other hand, in the case shown in FIG.
This shows a case where the transition point of CK1, FC, and DATA coincides with the transition point of the clock CK2 from low (L) to high (H). Each flip-flop FF0 to FF2 has an uncertain area as shown by shading. Is generated and the signal waveforms are deformed, so that there is a high possibility of malfunction.

That is, in these areas, the data (DATA) input to each of the flip-flop circuits FF0 to FF2, the jitter (fluctuation) of the clock CK1 and the frame signal FC, determine whether the value is before or after the rising of the clock CK2. Is undefined as to which of the flip-flops FF0 to FF2 is set, and a normal output cannot be generated. When the phase relationship between CK1 and CK2 is not constant, a normal output can be obtained at the timing of FIG. 5A, but a normal output cannot be expected at the timing of FIG. 5B.

[Problem to be Solved by the Invention] When a signal processed by one clock CK1 of two clocks that are frequency synchronized as described above is processed by a clock CK2 having a higher frequency than the clock CK1, If the phase is not constant between the clocks CK1 and CK2, there is a problem that a malfunction may occur.

When performing signal processing on a time-division multiplexed signal of a multi-frame, a high-frequency clock (CK2) used for signal processing is used for a bit clock (clock CK1) synchronized in phase with an input signal. It was not possible to prevent malfunctions due to the inability to synchronize the frame phase with CK1.

The present invention provides a frame phase synchronization circuit that maintains a predetermined frame phase so that a malfunction does not occur when a result of processing a signal by one of two clocks is processed by a high frequency clock synchronized with the other frequency. The purpose is to do.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 1 shows the principle configuration of a frame synchronization circuit in a time switch.

In FIG. 1, reference numeral 10 denotes a first counter, 11 denotes a specific frame number detecting circuit for detecting that a specific frame number has been reached, 1
2 is a matching circuit, 13 is a second counter, 14 is an address conversion circuit,
Reference numeral 15 denotes a first device, and 16 denotes a second device.

CK1 is bit-synchronized with the input signal, the first clock used for the processing operation of the first device, and CK2 is the second device 16
And the first clock CK
It has a frequency of 1 times 1. The first counter 10 is set to “0” by a multi-frame signal (m frames constitute one multi-frame), and the second counter 10
13 is set to “0” by the output of the matching circuit 12.

The present invention processes (stores) each data of an input signal based on an output of a first counter that counts a first clock of the input signal.
The second counter generates a count output synchronized with the second clock after a predetermined number of frame intervals of the frame of the input signal, and the output is the processing result (storage result) of the first device. By reading each data and supplying it to a second device operating at the speed of the second clock,
The data input to the second device is synchronized with the phase of the second clock.

[Operation] The counter 10 receives the input data (DAT
A) The first clock CK1 synchronized with the bit signal of A) is counted, the count output is supplied as a write address in the first device (for example, a call memory) 15, and data "0" is loaded by the multi-frame signal MFC. Then, when the multi-frame signal MFC is turned off, the counting of the first clock CK1 is started.

When detecting that the count value of the first counter 10 has reached the predetermined number of frames (n), the specific frame number detection circuit 11 generates an output during the frame period,
To supply.

The second counter 13 counts the second clock CK2 and outputs an output CK1 'each time it counts l (CK2 is
1 times the frequency of CK1). This output CK1 'is the first clock
This is a clock having the same frequency as CK1 and a phase synchronized with the second clock CK2.

The second counter 13 counts the CK1 'and outputs the count value as a read address of the address conversion circuit 14. Further, the second counter 13 stores the CK
1 'is counted, and at the beginning of each frame, a frame signal FC' is generated and supplied to the second device 16 and to the other input of the matching circuit 12. Then, the matching circuit 12
Generates an output when a frame signal FC 'from the second counter 13 is generated while an output (a period during which the input data signal is the nth frame) is generated from the specific frame number detection circuit 11. Then, the reset terminal of the second counter 13 is driven to reset the count value to “0”.

The data (address) read from the address conversion circuit 14 is supplied as a read address of the first device 15,
The data read from the first device 15 is the second clock
Input to the second device 16 in synchronization with CK2.

As described above, the first counter 10 and the second counter 13 always keep the phase difference by the number of frames determined by the specific frame number detection circuit 11. Further, by generating a clock CK1 'from the second counter at the same frequency as the frequency of the first clock and in synchronization with the phase of the second clock, malfunction in the second device 16 can be prevented.

[Embodiment] FIG. 2 (a) is a configuration diagram of an embodiment, and FIG. 2 (b)
Is a timing chart of the embodiment.

FIG. 2A shows an example in which the present invention is applied to a voice compression device of a time-division digital exchange.

In FIG. 2A, reference numerals 20 to 26 denote circuits whose functions correspond to those of 10 to 16 in FIG. 1. Reference numeral 20 denotes a first counter (CT1) which counts the clock CK1 and outputs the count value as an address signal.
, 21 denotes a specific frame number detection circuit for detecting the second frame, 22 denotes a match between the detection output of the specific frame number detection circuit 21 and a frame signal output from the second counter and representing the beginning of each frame. Match circuit, 23 is clock CK1
The clock CK2 having a frequency four times the frequency of the clock CK2 is counted, and the output CK having the same frequency as the clock CK1 (frequency obtained by dividing CK2 by 4) is output.
A second counter that outputs 1 ', counts CK1' and outputs the count value as an address (indicated by CT2)
It is.

Reference numeral 24 denotes a control address (indicated by CM) for generating a read address of a call memory as an output, using a count value from the second counter 23 as a read address, and reference numeral 25 denotes a serial time-division multiplex signal input from a highway. 1 counter
Write the count value of 20 as an address,
And a signal processing device 26 for performing a voice compression process on the data output from the communication memory 25 and outputting a compressed signal, and a second clock CK2. The processing is performed by

In this embodiment, the first clock CK1 = 2.048 MHz and the second clock CK2 = 8.192 MHz. Frequency synchronization (an integer multiple relationship) is established between the two clocks, but phase synchronization is established. Absent. Also, 1 bit = CK1 (one cycle of the first clock), 1 time slot = 8 bits = CK1 × 8, and 1
Frame (FC) = 32 time slots = CK1 x 8 x 32 = CK1
It has a relationship of × 256. Furthermore, one multi-frame (MFC) =
32 frames (FC).

Further, the call memory 25 constituting the time switch has a storage capacity for four frames, and the phases of the write system and the read system must be shifted by two frames. Then, the input data data of the signal processing device 26 that performs signal processing, the clock ck1 that defines input / output of data, and the frame signal fc
Are the second clocks CK2 that define the processing speed.
And the phase must be synchronized.

Hereinafter, how the operation is performed with the configuration of FIG. 2A so that the above condition is satisfied will be described with reference to the timing chart of FIG. 2B.

As in FIG. 3 of the conventional example, serial data DATA from the data highway is input to the communication memory 25 and sequentially written to the address output from the first counter 20. here,
The first counter 20 is loaded (reset) with “0” by a multi-frame (MFC) signal, and counts four frames from frame 0 to frame 3, and the frame information is represented by Fb0, Fb1. That is, Fb0
= 0, frame 0 when Fb1 = 0, frame 1 when Fb0 = 1, Fb1 = 0, frame 2, when Fb0 = 0, frame 2 when Fb1 = 1, Fb0 = 1, Fb1 =
1 indicates frame 3.

On the other hand, when reading the call memory 25, the second clock
The address given by the second counter 23 that counts CK2 is read by being converted by the control memory 24. Since the second clock CK2 has a frequency four times that of the first clock CK1, the output of the second counter 23 counting “4” of the second clock CK2 is the clock CK1 corresponding to the frequency of the first clock CK1. 'And this clock CK
The count value obtained by counting 1 'is supplied to the control memory 24, and the read address for time exchange (the call memory 25
) Is generated from the control memory 24.

At this time, the time exchange is a time slot (8 bits)
Since the conversion is performed every time, only the time slot information is converted by the control memory 24, and the bit information and the frame information are not converted by the control memory 24 (the time slot conversion within the frame is performed).

The second counter 23 counts four frames from frame 0 to frame 3 in the same manner as the first counter 20. The frame signal FC 'indicates the head of each frame.

Then, in the first counter 20, the multi-frame MFC
When the counting up to the second frame is performed after the occurrence of, the frame information becomes Fb0 = 0 and Fb1 = 1, so that the specific frame number detection circuit 21 outputs “1”. On the other hand, if the frame signal FC 'is generated from the second counter 23 at the head position of each frame while the specific frame number detection circuit 21 is outputting "1" in the second frame period, the matching circuit 22 "1" is input to the load input (LOAD) of the second counter 23, "0" which is always input to the data input terminal is loaded, and the second counter 23 is reset. After this, the second
The counter 23 starts counting from 0 frame.

Therefore, as shown in FIG. 2 (b), the first counter 20 and the second counter 23 constantly count while having a phase difference of two frames, and thereby the writing system and the reading system of the speech memory 25 are performed. Always has a phase difference of two frames. Further, with respect to the second clock CK2 which defines the data processing speed of the signal processing device 26, the phases of the clock CK1 ', the frame signal FC' and the output data of the control memory 24 are all generated based on the second clock CK2. Therefore, a predetermined phase relationship is maintained. For this reason, it is possible to prevent the occurrence of a malfunction as in the conventional example.

[Effects of the Invention] According to the present invention, the output of the call memory is phase-synchronized with the second clock CK2 that defines the processing speed.
A malfunction in a circuit that requires phase synchronization between the clock CK1 defining the input / output speed and the clock CK2 defining the processing speed can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 (a) is a block diagram of the embodiment, FIG. 2 (b) is a timing chart of the embodiment,
FIG. 3 is a system configuration diagram of a conventional example, FIG. 4 is a configuration of a time switch of a conventional example, FIG. 5 (a) is a configuration of phase synchronization of a conventional example, and FIG. FIG. 5C is a timing chart at the time of unstable operation. In FIG. 1, 10: first counter 11: specific frame number detecting circuit 12: matching circuit 13: second counter 14: address conversion circuit 15: first device 16: second device

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyohiro Shimokawa 1-5-1, Hakata-ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Inside (72) Inventor Tetsuo Ehara Hakata-ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture 1-5-1, Fujitsu Kyushu Communication System Co., Ltd. (56) References JP-A-54-7816 (JP, A) JP-A-54-6601 (JP, A) JP-A-54-6012 (JP, A) JP-A-59-112795 (JP, A) JP-A-4-137993 (JP, A) JP-A-3-270424 (JP, A) JP-B-58-49057 (JP, B2) (58) Field (Int.Cl. ⁷ , DB name) H04J 3/00-3/26 H04L ^7/ 00-7/08 H04Q 11/00-11/04 305

Claims (1)

(57) [Claims] An input time-division multiplexed multi-frame signal is time-converted in a frame by a time switch synchronizing with a first clock signal, and its output is converted to a signal having a frequency that is an integral multiple of the first clock. In a frame phase synchronizing circuit for a signal processing device which performs signal processing by a second clock, when an input signal is written into a communication memory of a time switch, the first clock is counted and the counted value is used as a write address as the write address. A first counter for supplying to the memory, counting the second clock, generating an output having the same frequency as the first clock, and generating a frame signal;
A second counter that supplies a value obtained by converting the count value by the control memory to the call memory as a read address, wherein the second counter is configured to transmit the value of the frame during a period in which the first counter is a specific number of frames. The signal processing device is reset by a circuit for detecting a state indicating the head, and the signal processing device processes the output signal of the communication memory according to the clock, the frame signal, and the second clock output from the second counter. Frame phase synchronization circuit.