JP3030751B2 - Thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (Thi) used for an active matrix liquid crystal display.
n Film Transistor).

[0002]

2. Description of the Related Art Thin film transistors (hereinafter referred to as TFTs)
A display using an active matrix type display substrate using a liquid crystal display has been actively studied because it can obtain higher image quality than a display device using a simple matrix type display substrate.

FIG. 4 is a perspective view schematically showing a liquid crystal panel of a conventional active matrix liquid crystal display. In FIG. 4, 1 is a scanning line, 2 is a data line, and 3 is T
FT, 4 is a pixel electrode for driving liquid crystal, 5 is a glass substrate, 6
Is an opposing electrode made of a transparent conductive film, 7 is an opposing substrate, 8 is a gate electrode connected to the scanning line 1, and 9 is a source electrode (or drain electrode) connected to the data line 2; 10 is the pixel electrode 4
Is electrically connected to the drain electrode (with respect to the source electrode 9).

In a normal transmission type liquid crystal display device, it is necessary to transmit light from a back light source.
The pixel electrode 4 and the counter electrode 6 must be a transparent conductive film. The elements of the scanning line 1, the data line 2, the TFT 3, and the pixel electrode 4 are formed by repeatedly forming a thin film, selective etching, and the like on the glass substrate 5 on which these are formed.

When color display is performed on the liquid crystal panel, display can be performed by forming color filters corresponding to each pixel on the glass substrate 5 on the counter substrate 7. In such a liquid crystal panel, when the TFT 3 is driven according to an image signal and the voltage applied to the liquid crystal layer is changed, the transmittance of the liquid crystal panel is changed accordingly, and an image can be displayed.

Next, a channel protection type TFT for a liquid crystal panel.
An array fabrication process will be described with reference to the drawings. FIG. 5 is a cross-sectional view of the manufacturing process, and FIG. 6 is a plan view thereof. In FIG. 5, reference numeral 4 'denotes a transparent conductive film of ITO (Ind
8 'is a Cr layer serving as the scanning line 1 and the gate electrode 8, 11 is an insulating layer of SiNx (Si nitride film), and 12 is a-
A semiconductor layer of Si (amorphous Si), 13 a channel protection layer of SiNx,

[0007]

13 'is a channel protective film, 14 is an ohmic layer of n ⁺ a-Si (n-type amorphous Si), 15 is a hole for making contact with the pixel electrode 4, 16 is a data line 2, and a source electrode 9 ,
An A1 layer serving as the drain electrode 10.

(FIG. 5 (a)) Cr is deposited on a glass substrate 5 by sputtering.
Deposit layer 8 'at 1000 °.

(FIG. 5B) The Cr layer 8 'is etched so as to leave the pattern of the scanning line 1 and the gate electrode 8 (FIG. 6).
(a)).

(FIG. 5C) An ITO film layer 4 ′ is deposited on the glass substrate 5 by DC sputtering at a thickness of 1000 °.

(FIG. 5D) The ITO film layer 4 'is etched so as to leave the pattern of the pixel electrode 4 (FIG. 6B).

(FIG. 5E) Next, the insulating layer 1 is formed by the plasma CVD method.
1 is SiNx 4000 °, and a-Si is 10 as semiconductor layer 12.
At 00 °, SiNx is deposited at 1000 ° as the channel protection layer 13.

(FIG. 5F) The channel protective layer 13 is etched by a photolithography process to form a pattern to be a channel protective film 13 '(FIG. 6C).

[0014]

(FIG. 5 (g)) As the ohmic layer 14, n ⁺ a-Si is deposited at 500 [deg.].

(FIG. 5 (h)) A hole 15 is formed in the insulating layer 11 (FIG. 6).
(d)).

(FIG. 5 (i)) The Al layer 16 is 7000
Å Deposit.

(FIG. 5 (j)) The Al layer 16 is selectively etched to form the source electrode 9 and the drain electrode 10.

[0018]

(FIG. 5 (k)) Etch and remove n ⁺ a-Si (FIG. 6 (k))
(e)).

After forming and enclosing an alignment film and a liquid crystal layer on a glass substrate 5 on which a TFT array is formed by the above process, a counter substrate 7 on which a black matrix, a color filter, and the like are formed is laminated to form a liquid crystal panel. Is completed.

In recent years, in order to make the TFT 3 smaller, the channel protective film 13 'has been eliminated, and the semiconductor layer 12 has been patterned into the shape of the gate electrode 8 by exposure from the back of the glass substrate 5. The development of type TFTs is also actively pursued. The manufacturing process in this case is as follows. FIG. 7 is a cross-sectional view of the manufacturing process, and FIG. 8 is a plan view of the manufacturing process, where 13 ″ is a channel region.

The steps up to the formation of the gate electrode 8 and the pixel electrode 4 on the glass substrate 5 shown in FIGS. 7A to 7D are the same as the case of forming the channel protective film 13 '.

[0022]

(FIG. 7 (e)) SiNx is used as the insulating layer 11 by plasma CVD.
000 °, a-Si of 1000 ° is deposited as the semiconductor layer 12, and n ⁺ a-Si of 500 ° is deposited as the ohmic layer 14.

(FIG. 7F) Etching is performed by a photolithography process so as to form a pattern of the channel region 13 ″ (FIG. 8C).

(FIG. 7 (g)) Drill a hole 15 in the insulating layer 11 (FIG. 8 (g)).
(d)).

(FIG. 7 (h)) The Al layer 16 is 7000
Å Deposit.

(FIG. 7I) The Al layer 16 is selectively etched to form the source electrode 9 and the drain electrode 10.

[0027]

(FIG. 7 (i)) The n ⁺ a-Si layer on the channel region 13 ″ is removed by etching (FIG. 8 (e)).

FIG. 9 is a plan view of an inverted staggered transistor having a channel protective film 13 ', wherein S1 denotes a gate-inverted transistor.
A GS region of the parasitic capacitance between the source and S2 is a GD region of the parasitic capacitance between the gate and the drain. Channel protective film 1
In the structure having 3 ', the GS region S1 and the GD region S2, which are hatched as shown in FIG. 9A, use the insulating layer 11 on the gate electrode 8 as a dielectric to form the gate electrode 8, the source electrode 9, and the drain. A parasitic capacitance is formed between the electrodes 10.

The value of the parasitic capacitance is determined by the pattern of the gate electrode 8, the pattern of the channel protective film 13 ', and the patterns of the source electrode 9 and the drain electrode 10. Here, the reason why the parasitic capacitance changes depending on the pattern of the channel protective film 13 'is that the channel protective film 13' functions as a conductor when the TFT 3 is in an active state.
This is because the region S1 and the GD region S2 are separated by the center of the pattern of the channel protective film 13 '.

10 is a plan view of a thin film transistor in which a channel region 13 ″ is formed in a self-aligned manner on the gate electrode 8 by exposure from the back of the glass.
The value of the parasitic capacitance at the FT depends on the pattern of the gate electrode 8 and the source electrode 9 and the drain electrode 10 as shown in FIG.
Is determined by the following pattern.

Generally, in the process of manufacturing an active matrix substrate, a patterning shift occurs between the respective layers. For example, when a shift occurs in the direction of the arrow as shown in FIG. 9B, the GS area S1 decreases and the GD area S2
Increases. On the other hand, when it is shifted, the GS area S1 increases and the GD area S2 decreases. That is, the parasitic capacitance of the TFT 3 changes due to the shift of each pattern. Similarly, in the self-aligned TFT, when a shift occurs in the direction of the arrow as shown in FIG. 10B, the GS region S1 increases and the GD region S2 decreases.

The main causes of these patterning deviations are alignment deviations at the time of exposure and distortion of the photomask itself. To solve such a problem, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent Application Laid-Open No. 267617, a structure has been proposed in which the shape of the TFT 3 is U-shaped to suppress variations in parasitic capacitance within a substrate or between substrates.

[0033]

However, in the TFT having such a configuration, when the above-described variation in the parasitic capacitance occurs in the same substrate, for example, when a display pixel is divided and exposed by a stepper, FIG. As shown in (2), this exposure boundary line is recognized, and the display quality deteriorates. Further, when the parasitic capacitance varies between the substrates, the circuit constant cannot be kept constant, and the display quality varies, which causes the image quality to deteriorate.

The main causes of these pattern deviations are alignment deviations at the time of exposure, distortion of the photomask itself, and the like. To cope with this problem, a structure in which the shape of the TFT is formed in a U-shape has been proposed. However, when such a structure is employed, the area occupied by the TFT in one pixel is increased, and the aperture ratio is reduced. There was a problem of inviting.

The present invention solves the above-mentioned problems of the prior art, and eliminates variations in the parasitic capacitance of the TFT, improves the display quality, and increases the aperture ratio of the liquid crystal panel.
It aims to provide FT.

[0036]

Means for Solving the Problems In order to achieve this object, the present invention is a form formed Ji Yan'neru protective film on the gate electrode
A organic thin film transistors, the source and drain electrodes, said only crossover opposite two sides of the region in which a channel protective film is formed, not overlapped on the other side, before Symbol source electrode and the drain electrode are both in cross-over to the gate electrode and the cross-type
And the semiconductor layer is the channel protective film,
Formed only below the source electrode and the drain electrode.
It is configured so as to have the structure described.

[0037]

[0038]

According to the above construction, the cross-over structure in which the portion of the gate electrode of the TFT and the source electrode and the drain electrode are all cross-shaped is adopted, so that the variation in the parasitic capacitance caused by the misalignment of the mask. Disappears.

[0039]

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a channel protection type T according to the first embodiment.
FIG. 2 shows a plan view of the FT. Also, the same reference numerals are given to those having the same operation and effect described in each drawing of the conventional example, and the detailed description thereof will be omitted.

The first embodiment is an example of a channel protection type TFT 3 in which a protection film is left on the channel of the TFT 3. In FIG. 1, C1 and C2 are the source electrode 9 and FIG.
(k), contact portions of the semiconductor layer 12, C3 and C4 are contact portions between the drain electrode 10 and the semiconductor layer 12, and C5 is a contact portion between the channel protective film 13 'and the source electrode 9 and the drain electrode 10. Figure 2 shows the TFT including the parasitic capacitance
3 shows an equivalent circuit.

The manufacturing process of the liquid crystal panel is the same as the conventional process. The channel protective film 13 'of the TFT 3 is formed only on the gate electrode 8, and the source electrode 9 and the drain electrode 10 are formed of the channel protective film 13'. Crosses over only two opposing sides of the region, does not overlap on the other side, and has a source electrode 9 and a drain electrode
Along with 10, it crosses over the gate electrode 8 in a cross shape.

With the above configuration, the value of the parasitic capacitance generated in the TFT 3 can be kept constant irrespective of the mask alignment accuracy. Explaining the reason, in FIG. 1A, the gate-source parasitic capacitance Cgs shown in FIG. 2 is a region indicated by the shaded GS region S1. Similarly, the parasitic capacitance Cgd between the gate and the drain is the region indicated by the shaded GD region S2.

By adopting this structure, the regions C1 to C5 do not change even when the mask is misaligned in the direction of the arrow as shown in FIGS. 1B and 1D when the active matrix substrate is manufactured. , The gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgs
gd is always the shaded GS area S1 and GD area S2,
The value is always constant regardless of the direction and amount of displacement.

From the above, at the time of manufacturing the active matrix substrate, the line of the joint portion at the boundary of the exposure shot area due to the accuracy of the photomask or the stepper disappears, and a liquid crystal panel with high display quality is realized. be able to.

Next, a second embodiment will be described with reference to the drawings. Example 2 is a case of a self-aligned TFT 3 in which the pattern of the semiconductor layer 12 is formed in the same shape as the shape of the gate electrode 8 by exposing the pattern of the semiconductor layer 12 from the back surface of the insulating substrate in the manufacturing process of the liquid crystal panel. FIG. 3 is a plan view showing the structure of the self-aligned TFT 3 according to the second embodiment.

Here, the difference from the conventional example is that, as shown in FIG. 3A, the gate electrode 8 and the source electrode 9 and the gate electrode 8 and the drain The electrodes 10 are designed so as to have a cross-over structure, and the parasitic capacitance Cgs between the gate and the source in this case is the GS region S1 indicated by oblique lines. Is the GD region S2 indicated by the hatched portion.

Therefore, even when the mask is misaligned in the direction of the arrow as shown in FIG. 3B, the parasitic capacitance Cgs between the gate and the source and the parasitic capacitance Cgd between the gate and the drain are always GS in the shaded area. The areas are S1 and GD area S2, and are always constant regardless of the direction and amount. As a result, similarly to the first embodiment, the line at the joining portion at the boundary of the exposure shot area disappears, and a liquid crystal panel with high display quality can be realized.

[0049]

As described above, according to the present invention,
In the case of a channel protection TFT in which a channel protection film is formed on a gate electrode, the source electrode and the drain electrode cross over only two opposing sides of the region where the channel protection film is formed and overlap with the other sides. And both the source electrode and the drain electrode cross over the gate electrode in a cross shape. With the above configuration, the value of the parasitic capacitance generated in the TFT section can be made constant regardless of the mask alignment accuracy.

Also, in the case of a self-aligned TFT, if the gate electrode and the source electrode and the gate electrode and the drain electrode are both cross-shaped in a cross shape on the channel region, the value of the parasitic capacitance will be out of alignment of the mask. Is constant, regardless of the direction and amount of displacement.

As described above, there is an effect that a variation in parasitic capacitance can be eliminated by using the TFT of the present invention, and a liquid crystal panel having an improved display quality and a large aperture ratio can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view of a channel protection type thin film transistor according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a thin film transistor including a parasitic capacitance.

FIG. 3 is a plan view of a self-aligned thin film transistor according to a second embodiment of the present invention.

FIG. 4 is a perspective view schematically showing a liquid crystal panel of a conventional active matrix type liquid crystal display device.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a conventional channel protection type thin film transistor array of a liquid crystal panel.

FIG. 6 is a plan view showing a manufacturing process of a conventional channel protection type thin film transistor array of a liquid crystal panel.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a conventional self-aligned thin film transistor array.

FIG. 8 is a plan view showing a manufacturing process of a conventional self-aligned thin film transistor array.

FIG. 9 is a plan view of a conventional channel protection type thin film transistor.

FIG. 10 is a plan view of a conventional self-aligned thin film transistor.

FIG. 11 is a diagram showing a boundary line at an exposure boundary generated when a parasitic capacitance varies in a substrate.

[Explanation of symbols]

1 scanning line, 2 data line, 3 TFT (thin film transistor), 4 pixel electrode, 4 'ITO film layer,
5: glass substrate, 6: counter electrode, 7: counter substrate,
8 gate electrode 8 'Cr layer 9 source electrode
10 ... drain electrode, 11 ... insulating layer, 12 ... semiconductor layer,
13 ... channel protective layer, 13 '... channel protective film,
13 ″… channel region, 14… ohmic layer, 15…
Hole, 16 ... Al layer.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Mutsumi Kimura 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. In-company (56) References JP-A-61-51972 (JP, A) JP-A-61-108171 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (1)

(57) [Claims] 1. A shape forming a Chi Yan'neru protective film on the gate electrode
A organic thin film transistors, the source and drain electrodes, said only crossover opposite two sides of the region in which a channel protective film is formed, not overlapped on the other side, before Symbol source electrode and the drain electrode are both in cross-over to the gate electrode and the cross-type
And the semiconductor layer is the channel protective film,
Formed only below the source electrode and the drain electrode.
A thin film transistor characterized in that it is.