JP3030569B2 - Manufacturing method of nonvolatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory used in electronic equipment.

[0002]

2. Description of the Related Art Conventionally, the resistance of a floating gate electrode is reduced by depositing a first silicon film 4 which is used as a floating gate electrode and which is not doped with an impurity, and then depositing the first silicon film 4 with a gas containing an impurity such as POCI _{3 in a} vertical direction. Diffusion to form a floating gate electrode. (Figure 2
(A)) After forming the insulating film 5 and the second silicon film 6,
The second silicon film is doped with impurities to form a control gate electrode. (FIG. 2B) or a method of lowering the resistance of the floating gate electrode by mixing impurities such as P by ion implantation over the entire surface of the first silicon film 4 after the first silicon film 4 is formed.

[0003]

SUMMARY OF THE INVENTION PO in the prior art
In the diffusion of impurities such as C13, post-processing after diffusion (PO
In the case of C13, treatment using hydrofluoric acid or the like to remove oxides containing P deposited on the surface during diffusion). Accordingly, there is a disadvantage that a thin insulating film below the floating gate is broken. Also, in the method using ion implantation, when the thickness of the floating gate electrode is reduced, there is a possibility that penetration into the gate insulating film below the floating gate may occur and the insulating film may be deteriorated.

[0004]

According to the present invention, a silicon film under a control gate electrode, which is etched in a self-aligned manner with the control gate electrode after forming the control gate electrode through an insulating film, is provided in the present invention. The floating gate electrode is formed by impurity diffusion from the lateral direction.

[0005]

In the nonvolatile semiconductor memory formed by impurity diffusion in the lateral direction as in the present invention, even if the thickness of the floating gate electrode is reduced, the gate insulating film is not broken and the Even when implantation is used, there is no damage to the gate insulating film since ions are not implanted into the channel region.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for manufacturing a nonvolatile semiconductor memory according to the present invention will be described below in detail with reference to the drawings. In the embodiment, a non-volatile semiconductor memory using a silicon oxide film as a gate insulating film will be described. However, it is needless to say that the present invention is not limited to the silicon oxide film. In the embodiment, the case where the floating gate electrode and the control gate electrode are mainly made of a polycrystalline silicon film will be described. However, an amorphous silicon film, a silicide film or a polycide film may be used.

Next, an example of a manufacturing process of the floating gate type memory transistor according to the first embodiment will be described. 1A shows a gate oxide film 3 on a P-type channel region of a P-type silicon substrate 9 by a thermal oxidation method, a polycrystalline silicon film as a first silicon film 4, and a second silicon film 6 with an insulating film 5 interposed therebetween. Shows a case where a polycrystalline silicon film is formed. Here, the first silicon film 4 has a thickness of 1000 ° or less, and the insulating film 5 is a continuous deposition of an ONO film (laminated multilayer film of silicon oxide film / silicon nitride film / silicon oxide film) formed by the CVD method. preferable. FIG.
2B, after the second silicon film 6 is doped with impurities to form the control gate electrode 8, the insulating film 5 and the first silicon film 4 are subjected to self-aligned etching, and the first silicon film 4 is subjected to PSG (reaction between POC 13 and oxygen). This shows that the floating gate electrode 7 is obtained by performing P doping using phosphor silica glass) and then diffusing impurities from the lateral direction by a subsequent heat treatment. At this time, impurity doping of the second silicon film may be performed simultaneously with impurity doping of the first silicon film. FIG. 1C shows that the n + source region 1 and the n + drain region 2 are formed by ion implantation through the gate oxide film 3 using the control gate electrode 8 and the floating gate electrode 7 as a mask.

Next, another example of the manufacturing process of the floating gate type memory transistor according to the second embodiment will be described. FIG. 3A shows a gate oxide film 3 on a P-type channel region of a P-type silicon substrate 9 by a thermal oxidation method, a polycrystalline silicon film as a first silicon film 4, and a second silicon film 6 with an insulating film 5 interposed therebetween. Shows a case where a polycrystalline silicon film is formed. FIG. 3B shows that the control gate electrode 8 is formed by doping the second silicon film 6 with impurities, and then the insulating film 5 is formed.
Is self-aligned and the first silicon film 4 is
PSG (phosphorus silica glass) by reaction between C13 and oxygen
Is shown, where the floating gate electrode 7 is formed by doping P with impurities and then diffusing impurities from the lateral direction by a subsequent heat treatment. At this time, impurity doping of the second silicon film may be performed simultaneously with impurity doping of the first silicon film. FIG. 3C shows that the floating gate electrode 7 is subjected to self-aligned etching using the control gate electrode 8 as a mask. FIG.
(D) is ion-implanted through the gate oxide film 3 to form n +
The figure shows that the source region 1 and the n + drain region 2 are formed.

Here, the POC 13 shown in FIG.
Has been described, but an ion implantation method may be used. However, in this case, the ion implantation is preferably performed at 50 KeV or less so that the ion implantation is performed only into the polycrystalline silicon film. Next, another example of the manufacturing process of the floating gate type memory transistor according to the third embodiment will be described. FIG. 4A shows a gate oxide film 3 on a P-type channel region of a P-type silicon substrate 9 by a thermal oxidation method, a polycrystalline silicon film as a first silicon film 4, and a second silicon film 6 with an insulating film 5 interposed therebetween. Shows a case where a polycrystalline silicon film is formed. FIG. 4B shows that after the second silicon film 6 is doped with impurities to form the control gate electrode 8, the control gate electrode 8 and the insulating film 5 are subjected to self-aligned etching. FIG. 4C shows a first silicon film using the control gate electrode 8 as a mask.
The first silicon film 4 is doped with impurities through the gate oxide film 3 by ion implantation, and the impurities are diffused from the lateral direction by a subsequent heat treatment. At the same time, the n + source region 1 and the n + drain region 2 are formed, and then the floating gate electrode 7 is formed by self-aligned etching using the control gate electrode 8 as a mask.

[0010]

As described above, the present invention is effective when the floating gate electrode is thick, but is more effective when the thickness of the floating gate electrode is reduced to 1000 ° or less. When the thickness is reduced, the step is reduced, so that it is suitable for miniaturization and the reliability is improved.
Further, as in the conventional case, when the thickness of the floating gate electrode is large, the gate electrode must be etched separately in the memory cell portion and the peripheral portion. In the self-aligned etching of the part, the peripheral part can be etched at the same time, and the process can be simplified.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views in the order of manufacturing steps of a floating gate nonvolatile semiconductor memory.

2 (a) and 2 (b) are cross-sectional views in the order of manufacturing steps in a conventional technique.

3 (a) to 3 (d) are cross-sectional views in a different manufacturing process of the floating gate nonvolatile semiconductor memory.

FIGS. 4A to 4C are cross-sectional views illustrating another manufacturing process of the floating gate nonvolatile semiconductor memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source region 2 Drain region 3 Gate oxide film 4 First silicon film 5 Insulating film 6 Second silicon film 7 Floating gate electrode 8 Control gate electrode 9 P-type silicon substrate

Claims (2)

(57) [Claims] A step of forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type; a step of forming a first silicon film on the gate insulating film; and an insulating film on the first silicon film Forming a second silicon film on the insulating film; doping an impurity in the second silicon film; etching the second silicon film and the insulating film to form a control electrode Doping the first silicon film with an impurity; etching the first silicon film to form a floating gate electrode; and forming a second conductivity type on a semiconductor surface on both sides of the floating gate electrode. Forming a source and drain region of the present invention. A step of forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type; a step of forming a first silicon film on the gate insulating film; and an insulating film on the first silicon film. Forming a second silicon film on the insulating film; doping an impurity in the second silicon film; etching the second silicon film and the insulating film to form a control electrode Doping an impurity into the first silicon film to diffuse the impurity into the first silicon film, and forming a second conductivity type source and drain region on a surface of the semiconductor substrate; A method for manufacturing a nonvolatile semiconductor memory, comprising a step of forming a floating gate electrode by etching a first silicon film.