JP3011947B2 - Carrier recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention utilizes a signal that has been subjected to polyphase modulation such as two-phase modulation or four-phase modulation, and a carrier of the signal with extremely high accuracy. The present invention relates to a carrier recovery circuit that outputs a synchronized reference signal having a frequency that is a rational multiple of the carrier frequency.

By using the carrier recovery circuit of the present invention, a reference signal equivalent to 10 MHz or 5 MHz synchronized with the carrier of the signal can be output from a polyphase phase modulated signal transmitted from a broadcasting satellite or the like, and the reference signal is measured. It can be used as a reference signal for a frequency counter or the like when measuring the frequency of a signal with high accuracy.

For example, an audio signal transmitted from a broadcasting satellite is an audio subcarrier (frequency is 63/110 times 10 MHz or 5.
MHz) is four-phase modulated.

Therefore, if the carrier recovery circuit of the present invention is used, a signal having a frequency of 110/63 or 55/63 times that of the audio subcarrier synchronized with the audio subcarrier, that is, 10 MHz
A reference signal equivalent to z or 5 MHz can be generated.

If the broadcast satellite is stably stationary and the audio sub-carrier is sufficiently accurate and four-phase modulated, 10 MHz or 5 MHz synchronized with the audio sub-carrier generated using the carrier recovery circuit of the present invention. The considerable reference signal has high stability and can be used as a highly stable reference signal for a frequency counter or the like.

Also, even if the audio subcarrier transmitted from the broadcasting satellite is not sufficiently accurate, it can be obtained at two points in the satellite broadcasting service area using the carrier recovery circuit of the present invention.
Since the reference signals corresponding to 10 MHz or 5 MHz are synchronized with each other, the frequency error of the voice subcarrier is measured at one reference point, and the frequency error is communicated to another point by means of a telephone or the like. Also at this point, frequency measurement can be performed with the same accuracy as the reference point.
As for satellite broadcasting, "Satellite receiver"
As described in Part 2 and 3 (Satellite Broadcasting Reception Technology Investigation Committee, published by The Radio Technology Association, 1983)
Here, the detailed description is omitted.

[Conventional technology]

Conventionally, for example, for reproduction of a sound subcarrier of satellite broadcasting,
As shown in FIG. 5, a Costas loop (COST) capable of simultaneously outputting demodulated data and a carrier component of a signal subjected to 4-phase phase modulation.
AS LOOP) integrated circuits were used. Then, in order to obtain a reference signal corresponding to 10 MHz or 5 MHz from the reproduced carrier obtained using the Costas loop, a conversion synthesizer 33 as shown in FIG. 4 was required.

110/63 of the carrier by the conversion synthesizer 33
A reference signal equivalent to 10 MHz or 5 MHz, which is twice or 55/63 times, is obtained.

[Problems to be solved by the invention]

In the prior art, for example, a carrier component is reproduced by a Costas loop 31 from a satellite broadcast transmission signal, and a 10 MHz or 5 MHz reference signal is obtained from the reproduced carrier by a conversion synthesizer 33. In this case,
There was such a problem.

Since the operation level range of many multipliers constituting the Costas loop 31, that is, the dynamic range is narrow,
An ALC circuit (Automatic Level Control) (not shown) was required so that the signal level for driving the multiplier did not greatly change.

However, in a normal ALC circuit, there is a problem that the phase difference between the output signal and the input signal changes instead of keeping the output signal level constant regardless of the magnitude of the input signal.

If a phase change corresponding to 0.1 degree occurs in any one of a number of multipliers constituting the Costas loop 31, the reproduced carrier wave output from the Costas loop 31 becomes 0.1.
The phase changes. Thus, for example, the audio subcarrier 5.
At the output of the conversion synthesizer 33 that inputs 10 MHz and outputs 10 MHz, a phase change of 0.1 degrees × 110/63, that is, 0.17 degrees occurs. In the prior art, when demodulating four-phase modulation, five multipliers are required, and the amount of phase change is expected to be further increased.

A low-pass filter 31b constituting the Costas loop 31,
Due to the difference in the frequency characteristics of 31h, and because the phase difference between the outputs of the 90-degree divider 31C is not exactly 90 degrees, when the signal-to-noise ratio of the input signal changes, a phase change occurs in the reproduced carrier. There was a problem unique to the Costas loop.

Regarding the above issues, please refer to “Tracking-Loop Bias Due To Costas Loop Arm Filte
r Imbalance '' JK Holmes IEEE Trans.on Communications Vol COM-30 No10 Oc
t.1982 pp2271-2273, detailed description is omitted here.

Also, if the phase detector 33b of the conversion synthesizer 33
If a phase change of 0.1 degree occurs, the output of the conversion synthesizer 33 at 10 MHz has a problem that a phase change of 0.1 degree × 110, that is, 11 degrees, occurs in the reference signal output.

The present invention solves these problems and provides a carrier recovery circuit capable of generating a reference signal having a small phase change as described above.

[Means for solving the problem]

In order to solve the above-mentioned problem, a carrier recovery circuit according to the present invention generates a first predetermined order harmonic component of a carrier by a nonlinear circuit 2 and then directly generates a reference signal synchronized with the carrier by a PLL 9. Let me.

The PLL 9 detects a phase difference between a harmonic component of the first predetermined order of the carrier and a signal that is a predetermined rational number times the frequency of the reference signal, controls the oscillation frequency of the VCO 6, and detects the carrier with extremely high precision. To obtain the synchronized reference signal.

In detecting the phase difference, a multiplier 7 that inputs the reference signal and outputs a second predetermined order harmonic component of the reference signal in order to minimize a phase change in a circuit used for the detection. And a synthesizer 8 which receives the reference signal, and multiplies the frequency of the reference signal by a predetermined rational number and outputs the same. (1) The first mixer 4 outputs the carrier signal which is the output signal of the nonlinear circuit 2 (1) mixing a harmonic component of a predetermined order of 1 with a harmonic component of a second predetermined order of the reference signal, which is an output signal of the multiplier 7, and (2) the second mixer 5 A mixing process of an output signal of the first mixer 4 and a signal having a frequency that is a predetermined rational number times the frequency of the reference signal, which is an output signal of the synthesizer 8, to obtain a first predetermined order of the carrier wave Harmonic component and the frequency of the reference signal. It is provided a two-stage step of detecting a phase difference between a predetermined rational multiple of the signal number.

[Action]

By employing the above-described means, the carrier recovery circuit according to the present invention does not use the Costas loop, and therefore does not use the ALC circuit required when using the Costas loop. In addition, there is no need to use a synthesizer for conversion, which is described in [Problems to be solved by the invention]
The problem does not occur.

Refer to Fig. 1 for the audio subcarrier of satellite broadcasting.
A case where a reference signal corresponding to 10 MHz is generated using MHz will be described in detail.

In satellite broadcasting, sound is converted to PCM (Pulse Code Modula
4) phase-modulates the 5.MHz audio sub-carrier at a bit rate of 2.048 MBPS, adds the 4-phase phase-modulated signal and the video signal, and FM-modulates the main carrier in the microwave band of about 9 GHz. Things are being sent. The BS tuner separates the received signal from the satellite into a video signal and a four-phase modulation signal after FM detection. This four-phase modulated signal is input to the carrier recovery circuit of the present invention.

The four-phase modulation signal s (t) is generally expressed as in equation (1).

a (t) and b (t) represent an I component (In-Phase) and a Q component (Quadrature-Phase) of the modulation baseband signal.

fc is a carrier frequency, and in this description, coincides with a voice subcarrier (hereinafter, simply referred to as a carrier) frequency.

fc = (63/110) x 10MHz = 5.MHz (2) The impulse response of the baseband filter on the transmitting side is represented by h.
_B (t), I component of the PCM speech signal, respectively and Q components a _n, when the b _n ∈-1,1 n∈Z, I component of the modulated baseband signal, Q component a
(T) and b (t) are Becomes Here, Z means a set of whole integers, and 1 / T means a coding rate.

The four-phase modulation signal s (t) is input to the limiter 1.

Since the output x (t) of the limiter 1 has a constant amplitude, h (t) is represented by a rectangular window function. Then Becomes

R (t) represents noise and a harmonic component of the four-phase modulated signal s (t), but is generally negligible, and will not be described below.

The output signal x (t) of the limiter 1 is input to the nonlinear circuit 2, and the output signal y (t) of the nonlinear circuit 2 is generally Becomes In the present invention, if the nonlinear circuit 2 has a perfect fourth power characteristic, that is, C ₄ = 1, C _n = 0, n ≠ 4, then y (t) = x ⁴ (t). 8) Here, to simplify the formula, Since A ² = B ² = 1, x ⁴ (t) = [Asin (2πfct) + Bcos (2πfct)] ⁴ = [sin ² (2πfct) + cos ² (2πfct) + 2ABsin (2πfct) cos ( 2Paifct)] ² = [1 + ABsin (4πfct)] ^{2 = 1 + sin 2 (4πfct} ) + 2ABsin (4πfct) ...... (11) a n, because b _n are mutually independent signals, ensemble average E of AB [AB] is Becomes zero.

Therefore, From equation (12), it can be seen that the output signal y (t) of the nonlinear circuit 2 contains the fourth harmonic component 4fc of the carrier.

The filter 3 uses this y (t) as an input signal and extracts the fourth harmonic component of the carrier.

An output terminal of the filter 3 is connected to a PLL 9 including a first mixer 4, a second mixer 5, a synthesizer 8, a multiplier 7, and a VCO 6.

The PLL 9 follows the fourth harmonic component of the carrier, and the frequency of the reference signal generated from the VCO 6 The frequency of the reference signal is 10
MHz.

 The above-described PLL 9 will be described in detail.

The first mixer 4 uses a fourth harmonic component of the carrier as a first input signal, and a second input of a signal obtained by multiplying a reference signal having a frequency fR, which is an output signal of the VCO ₆ , by a multiplier 7 by a second input. and signal frequency to generate the two components is _{f 1 = 4fc-2f R ......} (13) f 2 = 4fc + 2f R ...... (14), frequency outputs the component is f _1.

The second mixer 5 converts the output signal of the first mixer 4 into a first signal.
And the frequency f _{R of the} reference signal that is the output of VCO6.
Is multiplied by P / Q by the synthesizer 8 as a second input signal, and the frequency is f ₁₁ = f ₁ −f _R × P / Q (15) f ₁₂ = f ₁ + f _R × P / Q (16) The following two components are generated, and the oscillation frequency control voltage is generated and output from the component having a low frequency. (F ₁₁ is the frequency of the error signal, f ₁₂ is the frequency of the image component of the error signal.) When P = 16, Q = 55, the frequency f _R of the reference signal is 10MHz
become.

The output signal of the second mixer 5 is applied to the oscillation frequency control input terminal of the VCO 6.

That is, when f _R is equal to 10 MHz, The second mixer 5 has a frequency of f ₁₁ = f ₁ −f _R × P / Q = 0 Hz (19) f ₁₂ = f ₁ + f _R × P / Q = 20 MHz (20) Generate certain two components.

At this time, the error signal is DC. Therefore, a reference signal having a constant frequency f _R = 10 MHz is output to the reference signal output terminal of the VCO ₆ . If the frequency of the reference signal deviates from 10 MHz, the error signal changes, which acts on the output terminal of the second mixer 5 so that the frequency of the reference signal output from the VCO 6 is returned to 10 MHz. The oscillation frequency control voltage appears.

Therefore, when the above-described PLL 9 is in the following state, the frequency of the reference signal is always near 10 MHz, and the error from 10 MHz is small.

Although the operation has been described with reference to FIG. 1, the limiter 1 and the filter 3 in FIG.

The necessity of the limiter 1 is determined based on the state of the polyphase modulation signal input to the carrier recovery circuit according to the present invention, and the filter 3 includes an unnecessary signal in the output of the nonlinear circuit 2. This is because the necessity is determined depending on whether or not they have been used.

〔Example〕

A first embodiment of the present invention is shown in FIG. 2 and will be described in detail with reference to FIG.

This embodiment is 10 MHz synchronized with the audio subcarrier of satellite broadcasting.
Is used for the purpose of obtaining the reference signal.

The audio subcarrier (frequency 5.MHz) is input to the limiter 11 as a four-phase modulation signal. The limiter 11 is realized by using a comparator 11a and an attached capacitor and resistor. The output signal of the comparator 11a passes through a series circuit of a resistor 11c for matching and a capacitor 11b for removing DC offset, and is input to the nonlinear circuit 12. The non-linear circuit 12 can be realized by using a non-linearity such as a transistor or a diode.
This is realized by BM (Double Balanced Mixer) 12b. The RF input and Lo input of the DBM 12b are connected to the 2
Each output is connected.

From the IF output, the signal x input to the 0-degree distributor 12a
An even power component y (t) of (t) is output. I mean Is the output signal of the nonlinear circuit 12.

The output signal of the nonlinear circuit 12 is input to the filter 3.
The filter 3 is realized by a bandpass filter whose center frequency is the frequency of the fourth harmonic of the carrier, that is, 4fc = 5.MHz × 4 = 22.MHz (22).

The output of the filter 3 is a continuous wave having a frequency of 22 MHz and contains various noises. The noise is supplied to the first mixer 14, the second mixer 15, and the synthesizer 1 to be described later.
8, the multiplier 17 is eliminated by the PLL 19 composed of the VCO 6.

The output signal of the filter 3 is applied to the first input terminal 14a of the first mixer 14. In the present embodiment, the first mixer 14 is realized by a DBM 14a followed by a band-pass filter 14b having a center frequency of 2. MHz. Instead of the DBM, a transistor, a FET, a diode or a multiplier, an exclusive OR (EXO) is used.
It can also be realized by an R) type gate element or the like.

The first input terminal 14a is the RF input or Lo input of the DBM 14a, and the second input terminal 14b is the Lo input or RF input of the DBM 14a.

A second multiplier 14 is connected to the second input terminal 14b of the first mixer 14.
17 output signals are applied.

The multiplier 17 is a 2 multiplier in this embodiment. The doubler can be realized by a doubler element having a square characteristic, a full-wave rectifier, a transistor, an FET, a DBM, etc.
In the present embodiment, this is realized by a doubler element 17a, followed by a band-pass filter 17b having a center frequency of 20 MHz.

The multiplier 17 receives a reference signal, which is an output signal of the VCO 6, as an input signal, generates a second harmonic mainly by a doubler element 17a, and generates a second harmonic by a subsequent band-pass filter 17b.
Extract only the 0 MHz component.

This is applied to the second input terminal 14b of the first mixer 14. Accordingly, the first mixer 14 calculates f ₁ = 4fc−2f _R = 22.MHz−20 MHz = 2.MHz (23) f ₂ = 4fc + 2f _R = 22.MHz + 20 MHz = 42.MHz (24) Generate two components with frequency.

The output signal of the first mixer 14 is f _{1 of the} two components.
This component is applied to the first input terminal 15a of the second mixer 15. The second mixer 15 is a DB
M15a, a Butterworth-type low-pass filter 15b having a function of suppressing components other than the error signal component, and a proportional-integral filter 15c having a loop filter function for operating the PLL 19 at an optimum response speed. I have. DBM
Instead, the same components as the first mixer 14 or a phase detector can be realized. As a phase detector for that purpose, a PFD (Phase Frequency Det
The advantage is that even if the frequency of the reference signal output from the VCO 6 deviates considerably from 10 MHz, it can be returned to 10 MHz in a short time.

However, since there is a possibility that a phase change occurs due to a temperature change or the like, the DBM is used in this embodiment.

The output signal of the synthesizer 18 is applied to a second input terminal 15b of the second mixer 15.

In the present embodiment, the synthesizer 18 is a DDS (Direct
Digital Synthesizer).

That is, the VC applied to the input terminal of the synthesizer 18
The reference signal, which is the output signal of O6, is converted into a clock pulse of a logical value by the comparator 18a, and is input as a clock signal to the 55-frequency division counter 18b. The clock signal is counted at 55 periods by the 55 frequency dividing counter 18b. The output signal of the 55-frequency dividing counter 18b is address data g g∈ (0,1,2,3,..., 54), and g increases by 1 every 1 / f _R second and reaches 54. Next, it repeats to become 0. The output signal of the 55-divider counter is applied to an address input terminal of a ROM (Read Only Memory) 18c. A numerical table d (g) is stored in the ROM 18c. If the output of the ROM 18c is 8 bits, the numerical table is, for example, Generated by

Here, "round" is a function meaning "4 pick-up" and "5 pick-up". ROM18
The output signal d (g) of c is input to the latch 18d, and is simultaneously output from the latch 18d at the rising (or falling) of the clock symbol, and the DAC (Digital to Analog Co.) is output.
vertor) is applied to the input terminal of 18e.

The output signal of DAC18e is Becomes Here, _VQ means the quantization level, V _O means the amplitude of the output voltage, and V _OS means the offset voltage.

The output signal of the DAC 18e is input to a band-pass filter 18f having a center frequency of 2.MHz, where the quantization noise, harmonic distortion, etc. are suppressed, and the second input of the second mixer 15 is output as the output signal of the synthesizer 18. Applied to terminal 15b.

The output signal of the synthesizer 18 is such that the address data g is 1 /
because it increases by 1 every f _R seconds Is represented by

_VA is the amplitude of the output signal of the synthesizer 18, and τ is the delay time of the synthesizer 18 mainly caused by the delay time of the filter 18f.

Therefore, the frequency of the output signal of the synthesizer 18, the equation (27), the 2.MHz When f _R is assumed to be 10 MHz.

The error signal generated by the DBM 15a and the 2 × 2.MHz frequency component, which is an image component of the error signal, have components other than the error signal suppressed by the subsequent Butterworth type low-pass filter 15b. V with proportional-integral filter 15c
Generates oscillation frequency control voltage to be applied to CO6.

If the constant of the proportional-integral filter 15c is appropriately selected,
The oscillation frequency control voltage applied to the VCO 6 can be generated from the error signal so that the LL 19 can always follow the fourth harmonic component of the carrier, which is the output signal of the filter 3.

For example, a lag-lead filter as shown in FIG. 6 can be used instead of the proportional-integral filter.

VCO6 is a VCXO (Voltage Controlled) with an oscillation frequency of 10 MHz.
Crystal Oscillator). The variable range of the oscillation frequency is about (10 MHz-0.1 KHz) to (10 MHz + 0.1 KHz).

The VCO 6 can be realized by an atomic standard whose oscillation frequency can be changed, for example, a rubidium vapor oscillator, a hydrogen maser oscillator, or the like, other than the VCXO of the present embodiment. Also,
In this embodiment, the frequency of the reference signal is 10 MHz.
Oscillation frequencies other than the above can be realized by appropriately selecting the multiple of the multiplier and the rational number P / Q of the synthesizer.

 FIG. 3 shows a second embodiment of the present invention.

The limiter 21 is realized by a diode limiter in which two diodes are connected in parallel in opposite directions.

The nonlinear circuit 22 is realized by an absolute value circuit that outputs an absolute value of an input signal.

In this embodiment, the synthesizer 28 includes a VCXO 28c whose frequency is variable around 160 MHz, a 16 frequency divider 28d, and a PF
PLL30 composed of D28a and loop filter 28b
And a 55-frequency divider 28e and a band-pass filter 28f having a center frequency of 2.MHz.

To describe the operation of the synthesizer 28, the 160 MHz signal which is the output signal of the VCXO 28c is
Divide by 16 at 8d to obtain a 10MHz signal.

This 10 MHz signal and the reference signal applied to the output terminal of the synthesizer 28 are frequency-detected and phase-detected by the PFD 28a, and the oscillation signal applied to the VCXO 28c by the loop filter 28b from the error signal appearing at the output of the PFD 28a Generate a control voltage.

As a result, the PLL 30 has a frequency 16 times that of the reference signal applied to the input terminal of the synthesizer 28, that is, 160M.
It operates so that the Hz signal is output stably from the VCXO28c.

When the output signal of the VCXO 28c is divided by 55 by the 55 frequency divider 28e, 2.MHz is output from the 55 frequency divider 28e and input to the band pass filter 28f, and a sine wave signal in which unnecessary components are suppressed is output. Is done. This is the output signal of the synthesizer 28.

The carrier recovery circuit having the same function as that of the first embodiment can be realized by the synthesizer having the above configuration.

If the carrier recovery circuit of the present invention is used to generate a 10 MHz reference signal synchronized with, for example, an audio sub-carrier of a four-phase modulated signal for satellite broadcast audio, the reference signal can be synchronized over the entire service area of the satellite broadcast. Thus, highly accurate frequency measurement can be performed in the entire service area.

Or, conversely, it is generated by the carrier recovery circuit of the present invention.
By comparing a 10MHz or 5MHz reference signal with a 10MHz or 5MHz signal generated by a high precision atomic standard oscillator such as a cesium beam oscillator or rubidium vapor oscillator using a phase comparator, vector voltmeter, etc. The change in distance between points can be accurately measured.

That is, the stability of the reference signal generated by the carrier recovery circuit of the present invention is about .sigma.y (.tau. = 100 seconds) = 2.times.10.sup.- ^{12 in the} Allan variance in the first embodiment.

Since the variation of the error when the time is measured for τ seconds is τσy (τ) seconds, when τ = 100 seconds, it becomes 200 psec, which is equivalent to 6 cm when converted into the distance Cτσy (τ) of light travel.

Therefore, in principle, a change in the distance between the broadcasting satellite and the receiving point for about 100 seconds can be measured up to about 6 cm.

The first embodiment and the second embodiment each include the limiter 1 and the filter 3.

Even if the amplitude is limited by the limiter 1 in a signal having a good S / N such as a satellite broadcast, the phase is not deviated, so that it is effective to keep the amplitude constant for later signal processing. . In the case of a signal having a poor S / N, the presence of the limiter 1 may be rather a drawback.

The function of the filter 3 is to eliminate unnecessary signals from the signals that have passed through the nonlinear circuit 2.

Returning to the essence of the function as described above, in the principle diagram of FIG. 1, the limiter 1, the nonlinear circuit 2, and the filter 3 receive the polyphase modulation signal and extract a harmonic signal of a predetermined order. Therefore, the main body can be regarded as the nonlinear circuit 2, and the limiter 1 and the filter 3 are not essential.

〔The invention's effect〕

The carrier recovery circuit according to the present invention, as described above,
Do not use Costas Loop 31. Therefore, the ALC circuit necessary for stably operating the Costas loop 31 is not used. Further, the conversion synthesizer 33 for converting a signal having the frequency of the reproduced carrier into a reference signal is not used.

Instead, a reference signal is output from the VCO 6 so that the phase of the signal generated from the reference signal matches the phase of a predetermined-order harmonic component of the carrier generated by the nonlinear circuit 2.
PLL9 was controlled. As a result, the disadvantages of the ALC circuit that the phase between the input and the output changes, the problem of the phase change of many multipliers forming the Costas loop 31, the two low-pass filters forming the Costas loop 31
The phase change problem caused by the imbalance between 31b, 31h and the 90-degree divider 31c, and the phase change problem occurring in the conversion synthesizer 33 are all completely solved, and a carrier recovery circuit with little phase change is provided. be able to.

In the carrier recovery circuit according to the present invention, for example, even if the first mixer 4 or the second mixer 5 has a phase change of 0.1 degree, the reference signal has only a phase change of 0.1 degree × 10 MHz / 22.MHz = 0.043 degree. Does not occur.

[Brief description of the drawings]

1 is a block diagram showing the present invention, FIG. 2 is a block diagram showing a first embodiment, FIG. 3 is a block diagram showing a second embodiment,
FIG. 4 is a block diagram showing a prior art, FIG. 5 is a block diagram showing a Costas loop, and FIG. 6 is a circuit diagram showing a lag-lead type filter. 1,11,21 …… Limiter, 2,12,22 …… Non-linear circuit, 3 ……
Filters, 4,14 First mixer, 5,15 Second mixer, 6 VCO, 7,17 Multiplier, 8,18,28 Synthesizer, 9,19,29 …… PLL.

Claims (3)

(57) [Claims] A nonlinear circuit for receiving a polyphase-modulated signal and outputting a harmonic component of a first predetermined order of a carrier of the polyphase-modulated signal; A PLL for receiving an output signal as an input signal and outputting a reference signal synchronized with the carrier, wherein the PLL receives the reference signal and outputs a second signal of the reference signal. A multiplier (7) for outputting a harmonic component of a predetermined order; a synthesizer (8) for receiving the reference signal and multiplying the frequency of the reference signal by a predetermined rational number and outputting the same; and an output signal of the nonlinear circuit A first mixer (4) that outputs a necessary component of a product of both input signals and an output signal of the multiplier, an output signal of the first mixer, and a synthesizer. Output signal and the input signal, the product of both input signals A second mixer (5) for generating and outputting an oscillation frequency control voltage from the error signal; and a VCO (6) for receiving the output signal of the second mixer as an input signal and outputting the reference signal. Carrier recovery circuit. 2. A limiter (1) for receiving a polyphase-modulated signal and outputting the polyphase-modulated signal with a constant amplitude, and an output signal of the limiter as an input signal. A nonlinear circuit (2) for outputting a harmonic component of a first predetermined order of a carrier of a phase-phase modulated signal, and a PLL for receiving an output signal of the nonlinear circuit as an input signal and outputting a reference signal synchronized with the carrier (9) a carrier recovery circuit, wherein the PLL receives the reference signal, and outputs a harmonic component of a second predetermined order of the reference signal. A synthesizer (8) for receiving a reference signal, multiplying the frequency of the reference signal by a predetermined rational number, and outputting the signal; an output signal of the nonlinear circuit and an output signal of the multiplier; First mixer that outputs a required component of the product of 4) and a second mixer that receives the output signal of the first mixer and the output signal of the synthesizer as input signals, and generates and outputs an oscillation frequency control voltage from an error signal in a product of both input signals. (5) A carrier recovery circuit comprising: a VCO (6) that receives an output signal of the second mixer as an input signal and outputs the reference signal. 3. A limiter (1) for receiving a polyphase-modulated signal and outputting the polyphase-modulated signal with a constant amplitude, and an output signal of the limiter as an input signal. A nonlinear circuit (2) for outputting a harmonic component of a first predetermined order of a carrier wave of a phase-phase modulated signal; an output signal of the nonlinear circuit as an input signal; A filter for extracting a harmonic component of a first predetermined order, and a PLL for receiving an output signal of the filter as an input signal and outputting a reference signal synchronized with the carrier wave
(9) a carrier multiplier circuit, wherein the PLL receives the reference signal and outputs a harmonic component of a second predetermined order of the reference signal. A synthesizer (8) for receiving a reference signal, multiplying the frequency of the reference signal by a predetermined rational number, and outputting the input signal; an output signal of the filter and an output signal of the multiplier; A first mixer (4) for outputting a necessary component of the product, an output signal of the first mixer, and an output signal of the synthesizer as input signals, and an error signal of a product of both input signals A second mixer (5) for generating and outputting an oscillation frequency control voltage from a VCO, and a VCO (6) for receiving the output signal of the second mixer as an input signal and outputting the reference signal circuit.