JP3008567B2 - Chip type varistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip-type varistor functioning as a voltage non-linear resistor. In addition, the present invention relates to a structure in which diffusion to internal electrodes is suppressed to prevent deterioration of electrical characteristics.

[0002]

2. Description of the Related Art In recent years, in the field of electronic devices used for communication devices and the like, miniaturization and integration are rapidly progressing. Also,
Reduction in withstand voltage by increasing the density of ICs is required, and accordingly, protection elements and circuit designs are required to prevent breakage and malfunction of IC circuits due to intrusion of high-voltage noise. . A varistor having a non-linear voltage characteristic is employed as such a protection element. In order to apply this varistor to an IC circuit, conditions such as low suppression voltage, small capacitance, and small size are required. However, in the above varistor, there is a problem that the capacitance increases because the varistor voltage must be reduced in order to lower the suppression voltage. In addition, the capacitance can be reduced by reducing the electrode area, but this has a problem that the surge withstand capability is reduced. Conventionally, a multilayer chip varistor has been proposed as one that can cope with miniaturization while reducing the suppression voltage and the capacitance (for example, Japanese Patent Publication No. 58-58).
-23921). This laminated varistor is formed by alternately laminating semiconductor ceramic layers and internal electrodes and integrally sintering them, exposing one end surface of the internal electrode on both end surfaces of the sintered body, and exposing the internal electrode on both end surfaces. An external electrode connected to one end face is formed. By the way, although the above chip varistor is useful as a noise absorbing element,
If the size of the varistor element is reduced, there is a problem that a leakage current due to a surface current or a surface discharge easily occurs. In addition, since Ag is used for the external electrodes, there is a problem that solder erosion is likely to occur when surface mounting is performed by soldering. In order to avoid such leakage current and solder erosion, it is effective to coat a glass film on the outer surface of the sintered body excluding the external electrodes to make the surface insulating. As a method for coating the glass film, a method has conventionally been adopted in which the glass is baked at a temperature of 400 to 900 ° C. to diffuse the glass to the surface of the sintered body. By forming this glass film, the leakage current can be suppressed, and the surface of the external electrode can be covered with a plating film formed by electrolytic plating, thereby preventing solder erosion. Here, when the external electrode is coated with a plating film, since the sintered body is a semiconductor, if the surface of the sintered body is not surely insulated, plating grows over the entire surface and short-circuits. Or the effect of suppressing the leakage current may be reduced. Accordingly, the glass film needs to have a certain thickness, and it is necessary to make the thickness uniform.
Therefore, the baking temperature of the glass is set high to increase the surface diffusion.

[0003]

However, in the above-mentioned conventional chip varistor, when the baking temperature of the glass is increased, the grain boundary diffusion of the glass may be activated and the glass may reach the internal electrode, and as a result, the varistor voltage may be reduced. In addition, there is a problem that the suppression voltage rises and adversely affects the varistor characteristics. Here, it is possible to avoid diffusion to the internal electrodes while making the thickness of the glass film uniform, by delicately controlling the amount of glass and the baking temperature. However, this control is very difficult and at present difficult. The present invention has been made in view of the above conventional situation, and when forming a glass film on the surface of a sintered body, it is possible to make the film thickness uniform while eliminating the need for delicate control of the baking temperature, and to the internal electrode It is an object of the present invention to provide a chip-type varistor that can suppress the diffusion of the varistor and prevent the varistor characteristics from being adversely affected.

[0004]

SUMMARY OF THE INVENTION Accordingly, a first aspect of the present invention is to embed a plurality of internal electrodes in a sintered body and connect the internal electrodes to external electrodes formed on both end surfaces of the sintered body. In addition, in a chip type varistor in which a glass film is formed on an outer surface of the sintered body, a free electrode that is not connected to the external electrode is disposed between a surface portion of the sintered body and the internal electrode. It is characterized by: The invention of claim 2 is characterized in that the free electrode is larger than the area of the characteristic portion in the internal electrode and covers the characteristic portion.
It is characterized by being made of d alloy or Pt.

[0005]

According to the chip-type varistor according to the first aspect of the present invention, since the free electrode is disposed between the surface of the sintered body and the internal electrode, the free electrode suppresses diffusion into the glass. Therefore, even if the baking temperature is set high, diffusion to the internal electrodes can be reduced, and deterioration of the varistor characteristics can be avoided. As a result, a thick and uniform glass film can be formed without the need for delicate control of the baking temperature, and the insulating property can be improved. According to the second aspect of the present invention, since the free electrode is made larger than the area of the characteristic portion of the internal electrode, the diffusion of glass to the internal electrode can be suppressed more reliably. Further, in the third aspect of the present invention, since the silver / palladium alloy or platinum is employed for the free electrode, the effect of suppressing the diffusion of glass can be improved.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to 4 are views for explaining a chip type varistor according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a chip-type varistor of the present embodiment, which is a pair of internal electrodes 3 and 3 made of an Ag-Pd alloy inside a rectangular parallelepiped sintered body 2 made of semiconductor ceramic containing ZnO as a main component. And the left and right end faces 2 of the sintered body 2
External electrodes 4 made of Ag are formed on a and 2b. One end face 3a of each internal electrode 3 is
Are exposed to the left and right end faces 2a and 2b alternately and connected to the external electrode 4, and the other end faces are sealed in the sintered body 2. The outer surface of the external electrode 4 is coated with a Ni plating film 8 by electrolytic plating.

The portion of the ceramic layer 5a of the sintered body 2 sandwiched between the two internal electrodes 3 is a characteristic portion A exhibiting a voltage non-linear characteristic. It is an opposing surface. The portions of the sintered body 2 other than the ceramic layer 5a are ceramic layers 5b and 5c as dummy.

Further, a glass film 6 is formed on the outer surface of the sintered body 2, and the glass film 6 diffuses into the surface of the sintered body 2 by baking lead borosilicate glass powder at a high temperature. It is formed by the following.

In the ceramic layers 5b and 5c between the internal electrode 3 and the surface of the sintered body 2, a free electrode 7 made of an Ag-Pd alloy not connected to the external electrode 4 is provided. This free electrode 7 is sealed in the sintered body 2. The free electrode 7 is set to be larger than the area of the characteristic portion A of the internal electrode 3 and covers the characteristic portion A. Diffusion into the glass layer 7 is suppressed by the free electrode 7.

Next, a method of manufacturing the chip type varistor 1 of the present embodiment will be described. First, as a ceramic raw material, ZnO, Bi ₂ O ₃ , CoCO ₃ ,
98 mol% and 0.5 mol of MnO ₂ and Sb ₂ O ₃ respectively
%, 0.5 mol%, 0.5 mol%, 0.5 mol%, and pure water is added thereto and mixed with a ball mill for 24 hours to form a slurry. Next, the slurry is filtered, dried and granulated, and then calcined at a temperature of 800 ° C. for 2 hours. Thereafter, the calcined product is coarsely pulverized by a pulverizer, and pure water is added thereto, finely pulverized by a vol mill, filtered and dried, and then dispersed in a solvent together with an organic binder to form a slurry. A green sheet having a thickness of 50 μm is formed from the slurry by a doctor blade method, and the green sheet is punched into a predetermined size to form a number of ceramic sheets. As a result, a ceramic layer 5a exhibiting voltage non-linear characteristics and ceramic layers 5b and 5c as dummy are formed.

Next, a conductive paste made of an Ag-Pd alloy (7: 3 ratio) is prepared, and the paste is screen-printed on the upper surfaces of the ceramic layers 5a and 5c to form the internal electrodes 3. In this case, only one end face 3a of the internal electrode 3 is located at the outer edge of the ceramic layers 5a and 5c, and the other end face is located inside the ceramic layers 5a and 5c. In addition, a conductive paste is also printed on the upper surfaces of the other ceramic layers 5b and 5c to form free electrodes 7. The free electrode 7 is formed such that all end faces thereof are located inside the peripheral edges of the ceramic layers 5b and 5c and are larger than the area of the characteristic portion A of the internal electrode 3.

Next, as shown in FIG.
Are overlapped so as to face each other with the ceramic layer 5a interposed therebetween, and the one end faces 3a of the internal electrodes 3 are alternately positioned left and right, and the upper and lower surfaces of the ceramic layers 5b, 5c are superposed. Further, the ceramic layers 5b and 5c on which the free electrode 7 is formed are overlapped on the upper and lower surfaces thereof, and two ceramic layers 5b and 5c on which nothing is printed are overlapped. Next, a pressure of ² t / cm ² is applied in the laminating direction to press-bond, thereby forming a laminated body. Thereafter, the laminate is cut into a predetermined size, heated at 500 ° C. for 2 hours to eliminate the binder, and then heated to 950 ° C. and fired for 2 hours to obtain a sintered body 2. .

The sintered body 2 thus obtained is housed in an alumina porcelain pot, and a 1% by weight lead borosilicate glass powder of the total weight of the sintered body is added into the pot. And while rotating the porcelain pot, 700
Heat to ~ 900 ° C. Then, the glass powder is converted into a sintered body 2
And the glass film 6 is thereby formed. In this case, the diffusion of the glass powder into the interior is prevented by the free electrode 8, the penetration into the internal electrode 3 is suppressed, and the glass film 6 having a uniform thickness is formed on the surface of the sintered body 2. Is done.

Next, an Ag paste is applied to the left and right end surfaces 2a and 2b of the sintered body 2 where one end surface 3a of the internal electrode 3 is exposed, and then heated at 800 ° C. for 10 minutes to form an external electrode 4 To form Thereafter, the sintered body 2 is subjected to electrolytic plating, and a Ni plating film 8 is formed on the outer surface of the external electrode 4. In this case, since the portion of the sintered body 2 other than the external electrodes 4 is covered with the glass film 6, the plating does not adhere. Thereby, the chip type varistor 1 of the present embodiment is manufactured.

As described above, according to this embodiment, the free electrode 7 is provided between the surface of the sintered body 2 and the internal electrode 3, and the free electrode 7 covers the characteristic portion A of the internal electrode 3. So
The diffusion of the glass can be suppressed by the free electrode 7, and the diffusion to the internal electrode 3 can be reduced to avoid an increase in the limiting voltage and the varistor voltage. Further, since the baking temperature can be increased, the tension of the molten glass is reduced, the wettability to the element can be improved, and a thick and uniform glass film 6 can be formed. The leakage current can be reduced without impairing the voltage suppression effect, and solder erosion during soldering can be prevented. In the above-described embodiment, the structure in which the pair of internal electrodes 3 are embedded in the sintered body 2 has been described as an example. However, the present invention is not limited to this, and has a structure in which many internal electrodes are embedded. Also applicable to

[0016]

[Table 1]

Table 1 shows the results of tests performed to confirm the effects of the chip varistor of this embodiment. In this test, a number of chip-type varistors were prepared by the manufacturing method of the above embodiment, and the varistor voltage, nonlinear coefficient, capacitance, electrostatic loss, The limiting voltage ratio, the rate of change in the soldering process, the varistor voltage after plating, and the rate of change in surge were measured. In addition, as shown in FIG.
With respect to the characteristic area t1 × t2 of the internal electrode (see FIG. 5C), the area of the free electrode is defined as t1 + Δt, t2 + Δt (0
(0.4 mm) (see FIG. 5A), and the area of the free electrode is t1-Δt, t2-Δt.
(0.1 to 0.2 mm) was performed when the size was reduced (see FIG. 5B). Here, the rate of change in the soldering process was determined using a pine resin for each sample after forming the external electrodes.
The sample was immersed in a 4 × 6 solder bath at 860 ° C. for 5 seconds, washed with trichloroethane for 60 seconds, and left for 1 hour for measurement. The limiting voltage ratio is the ratio of the output voltage / varistor voltage when a triangular current wave of 8 × 20 μsec is applied, and the surge change rate is the varistor voltage / applied when the triangular current wave is applied and left for 1 hour. This is the rate of change of the front varistor voltage. In addition,
For comparison, the same measurement was performed on a conventional chip varistor without a free electrode. As is clear from Table 1, conventional samples without free electrodes (Nos. 1 to 6)
So, if the glass baking temperature is as low as 700-800 ° C,
Although the varistor voltage and the nonlinear coefficient are satisfactory, the dielectric loss and the rate of change in the soldering process are low, and the plating process adheres to the entire surface of the sintered body and causes a short circuit. It has become. When the baking temperature is as high as 850 ° C. or higher, the varistor voltage and the nonlinear coefficient are deteriorated even though the glass film is uniform, and the glass is diffused to the internal electrodes. on the other hand,
When the area of the free electrode is smaller than the characteristic part of the internal electrode (Sample Nos. 7, 8, 13, and 14), the varistor voltage and the specific linear coefficient are determined because the glass goes around the free electrode and diffuses inside. The effect is slightly small in the characteristics such as.
On the other hand, when the area of the free electrode is larger than that of the characteristic portion (Sample Nos. 9 to 12 and 15 to 20), the characteristics of the varistor voltage, the nonlinear coefficient, the dielectric loss, and the limiting voltage ratio are all impaired. Satisfactory characteristics are obtained in all of the change rate of the soldering process, the varistor voltage after plating, and the change rate of the surge.

[0018]

[Table 2]

[0019]

[Table 3]

Tables 2 and 3 show the conventional samples (Nos. 2 to 6) without the free electrodes and the samples of the present example (Nos. 11 and 17) with the free electrodes used in the above test. )
Are selected, the cross-section of each sample is polished, and the results of investigating the diffusion distance of the glass with an X-ray microanalyzer (energy dispersive type) are shown. As shown in FIG. 2, the diffusion distance of the sintered body 2 in the stacking direction x-axis and the diffusion distance in the direction perpendicular to the stacking direction y-axis were measured. In each sample, the distance from the surface of the sintered body 2 to the free electrode 7 was 100 μm, and the distance from the free electrode to the internal electrode was 100 μm.
μm, and the distance from the side end surface of the sintered body to the side end surface of the internal electrode was 400 μm. As is clear from each table, in the conventional sample having no free electrode, the glass reaches the characteristic portion of the internal electrode when the baking temperature required for insulation is set to 850 ° C. In contrast, in the sample of this example, even when the baking temperature was raised to 900 ° C., the glass did not reach the internal electrodes, and it can be seen that the free electrode suppressed diffusion into the glass.

[0021]

As described above, according to the chip-type varistor according to the present invention, the free electrode which is not connected to the external electrode is disposed between the surface portion of the sintered body and the internal electrode. When a glass film is formed on the surface, there is an effect that the film thickness can be made uniform without requiring delicate control of the baking temperature, and diffusion to the internal electrode can be suppressed to prevent an adverse effect on the varistor characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view taken along the line II of FIG. 3 for explaining a chip type varistor according to one embodiment of the present invention.

FIG. 2 is a sectional view of the chip type varistor according to the embodiment shown in FIG.
It is a line sectional view.

FIG. 3 is a perspective view of the chip type varistor of the embodiment.

FIG. 4 is an exploded perspective view of the chip varistor of the embodiment.

FIG. 5 is a plan view of a free electrode and an internal electrode for explaining a test method performed for confirming the effect of the embodiment.

[Explanation of symbols]

 Reference Signs List 1 chip type varistor 2 sintered body 2a, 2b left and right end faces of sintered body 3 internal electrode 3a one end face of internal electrode 4 external electrode 6 glass film 7 free electrode A characteristic part

Continuation of front page (72) Inventor Yasunobu Yoneda 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Murata Manufacturing Co., Ltd. (56) References JP-A-2-302003 (JP, A) JP-A-2-14501 (JP, A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01C ^7/ 02-7/22

Claims (3)

(57) [Claims] A plurality of internal electrodes are buried inside a ceramic sintered body, one end surface of the internal electrode is connected to an external electrode formed on an end surface of the sintered body, and a plurality of internal electrodes are formed outside the sintered body. A chip-type varistor having a surface coated with a glass film, wherein a free electrode not connected to the external electrode is disposed between a surface portion of the sintered body and an internal electrode. 2. The method according to claim 1, wherein the free electrode comprises:
A chip-type varistor characterized in that it is larger than an area of a characteristic portion exhibiting a voltage ratio linear characteristic in an internal electrode and covers the characteristic portion. 3. The chip-type varistor according to claim 1, wherein the free electrode is made of a silver-palladium alloy or platinum.