JP3000360U - Reference signal generation circuit for communication equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to reduce the mounting area on the board by using only one reference frequency oscillator for communication equipment, and prevent troubles due to complicated spurious caused by interference between crystal oscillators. To do. In a communication device reference signal generation circuit for generating a plurality of various reference signals by a reference frequency generation oscillator, only one oscillator is provided, and each of the various reference signals is generated by a single oscillator. It is a communication device reference signal generation circuit including a reference signal generation means for generating a reference frequency signal phase.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a reference signal generation circuit for generating a plurality of signals of a predetermined required frequency from a signal of a frequency output from a single reference oscillator suitable for use in a small communication device such as a pager. It is a thing.

[0002]

[Prior art]

 In a pager using a conventional POCSAG code, a PLL (phase locked loop) circuit of the receiver has a low speed clock for CPU clock of 32.768 KHz, a high speed clock of 2 MHz band or 600 Hz (1200 bps). ) And a reference clock of different frequencies, such as 256 Hz (512 bps). Therefore, a plurality of reference oscillators such as crystals are required to generate the reference clock of each frequency. FIG. 4 is a block diagram showing the configuration of a reference signal generation circuit used in this pager to generate a plurality of reference clock signals having different frequencies. The reference signal generation circuit 100 includes a plurality of oscillators such as a first oscillator 1, a second oscillator 2, and a third oscillator 3. Reference numeral 1a is a crystal oscillator used for the oscillator 1, and 32. It is a crystal oscillator for generating a low-speed clock of 768 KHz. Reference numeral 2a is a crystal oscillator used for the oscillator 2, and is a crystal oscillator for a CPU high-speed clock in the 2 MHz band. Reference numeral 3a is a crystal oscillator for a 600 Hz clock. Reference numeral 4 is a low-speed clock output terminal of 32.768 KHz for CPU timing output from the first oscillator 1, and 7 is 32.768 KH. z is divided by a frequency divider 8 at a 256 Hz output terminal, 5 is a 2 MHz band CPU high-speed clock output terminal, and 6 is an output terminal for outputting a 600 Hz clock signal. The clock signals output from the low-speed clock output terminal 4, the CPU high-speed clock output terminal 5, and the output terminals 6 and 7 are supplied to the PLL circuit block operating with the clock signals of the respective frequencies.

[0003]

Since the conventional reference signal generation circuit is configured as described above, in order to generate clock signals of different frequencies, water having different natural oscillation frequencies are generated. It is necessary to provide an oscillator with a crystal oscillator independently, which requires a mounting area on the board, and interference between each crystal oscillator causes complicated spurious signals, which causes reception failure. There was a problem.

The present invention has been made to solve the above-mentioned problems, and it is possible to reduce the mounting area on a substrate by using a single oscillator and to reduce the interference between crystal oscillators. It is an object of the present invention to provide a reference signal generation circuit capable of preventing a failure due to a complicated spurious generation caused by the above.

Another object of the present invention is to provide a reference signal generation circuit that can further reduce power consumption.

[0006]

[Means for Solving the Problems]

 A reference signal generating circuit for communication equipment according to the present invention is a reference signal generating circuit for communication equipment, which generates a plurality of various reference signals by an oscillator for generating a reference frequency. In the reference signal generating circuit for communication equipment, only one oscillator is provided. Each signal is provided with a reference signal generating means for generating it based on the reference frequency signal phase by the single oscillator.

Further, a plurality of PLL (phase locked loop) circuits are provided, and each of the PLL circuits outputs a voltage-controlled oscillator that outputs a target frequency signal and a signal obtained by dividing the signal of the voltage-controlled oscillator by a frequency divider. And a control voltage applied to the control voltage of the voltage controlled oscillator by converting the pulse signal corresponding to the phase difference between the phase comparator for comparing the phase with the reference frequency signal by the oscillator to a DC voltage. It is characterized in that it is composed of a generator circuit.

Further, when each of the PLL circuits that generate a plurality of various target frequencies operates, if there is a frequency that is not required at the current time among the various frequencies, the corresponding PLL circuit It is characterized in that it is provided with a power supply control means for shutting off the power supply only when it is not needed.

Further, the frequency divider in the PLL circuit is a variable frequency divider whose frequency division ratio is variable by a control signal.

Further, the control signal for controlling the frequency division ratio of the variable frequency dividing circuit is read from the storage device of the data table in which the target output frequency data and frequency division ratio data are stored in association with each other. It is characterized in that it has a control means.

[0011]

[Action]

 The reference signal generating circuit for communication equipment according to the present invention compares the phase of a signal of a predetermined frequency output from a reference oscillator with a single oscillator and the divided outputs of a plurality of voltage controlled oscillators. Based on the phase comparison results, the output signal frequencies of the plurality of voltage controlled oscillators are PLL-controlled to the set frequency values respectively, and the signals of the predetermined frequency output from the single reference oscillator are Since a plurality of signals of different reference frequencies for communication equipment are generated, it is sufficient to provide one oscillator, for example, a reference oscillator with a single crystal oscillator, and reduce the mounting area on the board. In addition, it is possible to avoid the occurrence of troubles due to complicated spurious caused by the interference between the reference oscillators by the multiple oscillators.

The reference signal generation circuit for communication equipment according to the present invention is not required at the current time among a plurality of PLL circuits in which the target output signal frequency is PLL-controlled to the set frequency value. By shutting off the power supply to the PLL circuit including the voltage control oscillator, the power consumption is controlled to the required time.

Further, the reference signal generating circuit for communication equipment according to the present invention is a frequency division circuit read by a control circuit such as a microcomputer from a data table stored in a storage device in which output frequency data and frequency division ratio data are associated with each other. Since the PLL control is performed by the control signal generated based on the ratio data, it suffices to provide one reference oscillator with a single oscillator, which can reduce the mounting area on the substrate, It is possible to avoid the occurrence of troubles due to the complicated spurious caused by the interference between the reference oscillators by the crystal oscillator.

[0014]

【Example】

Hereinafter, a first embodiment of a reference signal generating circuit for communication equipment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the reference signal generation circuit of this embodiment. In the figure, 11 is a reference oscillator that generates and outputs a low-speed clock signal for CPU clocking of a reference frequency Fref (for example, 32.768 KHz), and 11a has a natural vibration frequency of the reference frequency Fref connected to the reference oscillator 11. Crystal oscillator, 12 is a first frequency dividing circuit set to a frequency division ratio of 1 / a (for example, 1/2 ⁷ ), 13 is a clock signal having an oscillation frequency F1 (for example, 19.2 KHz) The first voltage-controlled oscillation oscillator (hereinafter referred to as VCO), 14 is a second frequency dividing circuit set to a frequency division ratio of 1 / b (for example, 1/75), and 15 is a first frequency dividing circuit. The phase comparison circuit compares the phase between the frequency-divided output of the frequency-dividing circuit 12 and the frequency-divided output of the second frequency-dividing circuit 14, and outputs a pulse signal having a pulse width corresponding to the phase difference. Reference numeral 16 is a control voltage generation circuit that integrates the pulse signal output from the phase comparison circuit 15 and generates a DC voltage signal.

Reference numeral 17 is a second VCO that generates and outputs a high-speed clock signal with an oscillation frequency F2 (for example, 2 MHz band), and 18 is set to a division ratio 1 / c (for example, 1/7000 to 1/8000). The third frequency divider circuit 19 compares the phase between the frequency-divided output of the first frequency-divider circuit 12 and the frequency-divided output of the third frequency-divider circuit 18, and determines the pulse width corresponding to the phase difference. It is a phase comparison circuit that outputs a pulse signal. Reference numeral 20 is a control voltage generation circuit that integrates the pulse signal output from the phase comparison circuit 19 to generate a DC voltage signal.

Reference numeral 21 is a first power supply block, which is a fourth VCO 13, a second frequency dividing circuit 14, a phase comparison circuit 15, and a fourth frequency dividing ratio 1 / d (for example, 1/2 ⁵ ). It is a power supply block of the frequency divider circuit 23, and the power supply to the first VCO 13, the second frequency divider circuit 14, the phase comparison circuit 15, and the fourth frequency divider circuit 23 is the second power source supply described below. Independent of block. Reference numeral 22 is a second power supply block, which is a power supply block for the second VCO 17, the third frequency divider circuit 18, and the phase comparison circuit 19. The second VCO 17 and the third frequency divider circuit 18 are used for phase comparison. Electric power is supplied to the circuit 19 independently of the first power supply block.

Reference numeral 24 is a 256 Hz (512 bps) clock signal output terminal, 25 is a 600 Hz (F1 / d, 1200 bps) clock signal output terminal, and 26 is a Fre f (32.768 KHz) low-speed clock signal for CPU clocking. , And 27 is an output terminal for a high-speed clock signal having an oscillation frequency F2. Reference numeral 28 denotes a power supply control means, which is a circuit for independently supplying power from the power supply 29 to the first power supply block 21 and the second power supply block 22.

Next, the operation will be described. In this communication device reference signal generation circuit, the CPU clocking low-speed clock signal of the reference frequency Fref32.768 KHz generated and output by the reference oscillator 11 is output to the output terminal 26 as the CPU clocking low-speed clock signal. In the first frequency dividing circuit 12, the frequency is divided into Fref / a and supplied to the phase comparison circuit 15, and the signal 256 Hz is output to the terminal 24. On the other hand, the clock signal of frequency F1 output from the first VCO 13 is divided into F1 / b and supplied to the phase comparison circuit 15. The phase comparison circuit 15 performs phase comparison between the clock signal divided into Fref / a and the clock signal divided into F1 / b, and a pulse signal corresponding to the phase difference is outputted to the control voltage generation circuit 16 Is converted into a DC voltage signal by the first VCO 13 and supplied to the frequency control terminal of the first VCO 13. The first VCO 13 outputs the signal frequency to the first frequency dividing circuit 12 and the second frequency dividing circuit 15 in the phase comparison circuit 15. PLL control is performed so that the phase difference between the clock signals output from the circuit 14 becomes zero. Therefore, the frequency F1 of the clock signal output from the first VCO 13 has the same phase as the reference frequency Frex, and is further divided into 1 / d in the fourth frequency dividing circuit 23 to be output as a clock signal with a frequency of 600 Hz (1200 bps). Output to the terminal 25. Similarly, the frequency F2 of the clock signal output from the second VCO 17 is also PLL controlled, and is output to the output terminal 27 as a high-speed clock signal in the 2 MHz band in which the phases are matched.

In many cases, the pager does not need the above four frequencies at the same time. In that case, when the high-speed clock signal in the 2 MHz band is unnecessary, the power supply control means 28 causes the second power supply block 22 to operate. As a result, the power supply 29 supplies the first VCO 13 of the first power supply block 21, the second frequency division circuit 14, the phase comparison circuit 15, and the fourth frequency division ratio 1 / d. Power is supplied to the frequency dividing circuit 23 (however, power is always supplied to the components other than the first power supply block 21 and the second power supply block 22), and power consumption by unnecessary circuits is suppressed.

Further, since only one crystal oscillator 11a is used for the reference oscillator 11, the space on the substrate can be effectively used, and moreover, when a plurality of crystal oscillators having different natural oscillation frequencies are used. In addition, no complicated spurious is generated, and it can be used not only for pager but also for communication equipment to avoid occurrence of reception failure.

Next, a second embodiment of the high-speed clock signal generation of the communication device reference signal generation circuit of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the communication device reference signal generation circuit of this embodiment. In the figure, 31 is a reference oscillator that generates and outputs a low-speed clock signal for CPU clocking of a reference frequency Fref (for example, 32.768 KHz), 31a is a specific vibration frequency of the reference frequency Fref connected to the reference oscillator 31. The crystal oscillator 32, a microcomputer (CPU) 32, and an output frequency / division ratio correspondence table 33 in which output frequency data and division ratio data are stored in association with each other as shown in FIG. The storage device 34 is a programmable variable frequency divider circuit whose frequency division ratio can be varied by a control signal, and 35 is a frequency division output from the variable frequency divider circuit 34 and a reference oscillator 31. A phase comparison circuit that detects the phase difference from the CPU clocking low-speed clock signal and outputs a pulse signal having a pulse width corresponding to the detected phase difference, 36 Control voltage generating circuit for converting a pulse signal outputted from the phase comparator 35 into a DC voltage signal, 37 is a VCO which is more output signal frequency into a DC voltage signal is controlled. 38 is an output terminal to which the output signal from the VCO 37 is supplied.

Next, the operation will be described. In the high-speed clock signal generation circuit of the communication device reference signal generation circuit, when the output signal frequency to be taken out from the output terminal 38 is set, the CPU 32 responds to the output frequency / division ratio based on the set output frequency. The corresponding frequency division ratio data is read out by referring to the table storage device 33. Then, a control signal is generated based on the read frequency division ratio data and output to the variable frequency dividing circuit 34. The variable frequency dividing circuit 34 sets the frequency dividing ratio based on the control signal sent from the CPU 32. Therefore, when the frequency division ratio set in the variable frequency dividing circuit 34 is 1 / m, the signal frequency extracted from the output terminal 38 is m · Fref, which is equal to the frequency division ratio set in the variable frequency dividing circuit 34. It is possible to take out the corresponding signal frequency from the output terminal 38.

Further, since only one crystal oscillator 31a is used for the reference oscillator 31, it is possible to effectively use the space on the base plate, and moreover, when a plurality of crystal oscillators having different natural oscillation frequencies are used. It does not cause complicated spurious noise and can prevent reception failures even when used in communication equipment.

In this embodiment, the frequency division ratio is read from the output frequency / frequency division ratio correspondence table storage device 33 based on the output frequency. However, the output frequency is read based on the frequency division ratio. A control signal corresponding to the output frequency read and output may be output to the variable frequency dividing circuit 34, or may be configured by a logical circuit without using a microcomputer.

[0025]

[Effect of device]

 As described above, according to the present invention, a plurality of various reference signals required by communication equipment are generated based on a single crystal oscillator for generating a reference frequency, so that the mounting area on the board is reduced. In addition, it is possible to prevent the trouble due to the complicated spurious caused by the interference between the crystal oscillators. Further, since the various reference signals are composed of a plurality of PLL circuits based on a single oscillator, the power supply of the PLL circuits is temporarily stopped during the time period when the reference signals generated by the respective reference signals are unnecessary. Since it can be set, there is an effect that power consumption can be controlled. Further, if the PLL frequency divider is a variable PLL frequency divider, it is effective to change or adjust the reference signal generation frequency efficiently.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a reference signal generating circuit for a communication device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a high-speed clock generation configuration of a communication device reference signal generation circuit according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a configuration of an output frequency / frequency division ratio correspondence table in high-speed clock generation of the communication device reference signal generation circuit according to the second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a conventional communication device reference signal generation circuit.

[Explanation of symbols]

11 Reference Oscillator 13 First VCO 17 Second VCO 28 Power Supply Control Means 32 CPU (Microcomputer) 33 Output Frequency / Division Ratio Correspondence Table (Data Table) 34 Variable Divider Circuit 37 VCO

Claims (5)

[Scope of utility model registration request] 1. A reference signal generation circuit for communication equipment, which generates a plurality of various reference signals by a reference frequency generation oscillator, wherein only one oscillator is provided, and each of the various reference signals is a single oscillation. A reference signal generation circuit for communication equipment, comprising a reference signal generation means for generating a reference frequency signal phase by a child. 2. The communication device reference signal generation circuit according to claim 1, further comprising a plurality of PLL (phase-locked loop) circuits, each of the PLL circuits including a voltage-controlled oscillator that outputs a target frequency signal and the voltage. A phase comparator for comparing the phase of a signal obtained by dividing the signal of the controlled oscillator with a frequency divider and the reference frequency signal by the oscillator, and a pulse voltage corresponding to the phase difference of the phase comparator for DC voltage conversion A reference signal generation circuit for a communication device, comprising a control voltage generation circuit for applying a control voltage of a voltage controlled oscillator. 3. The communication device reference signal generation circuit according to claim 1, wherein when each of the PLL circuits that generate a plurality of various target frequencies operates, the current time among the various frequencies is set. A reference signal generation circuit for communication equipment, comprising a power supply control means for shutting off power supply to the PLL circuit corresponding to the unnecessary frequency for a time not required. 4. The reference signal generation circuit for communication equipment according to claim 1, wherein the frequency divider in the PLL circuit is a variable frequency divider whose frequency division ratio is variable by a control signal. A reference signal generation circuit for a communication device, characterized in that 5. The communication device reference signal generation circuit according to claim 4, wherein the output frequency data and the division ratio data targeted by the control signal for controlling the division ratio of the variable frequency division circuit correspond to each other. A reference signal generation circuit for communication equipment, comprising a control means read out from a storage device of a data table stored therein.