JP3088032B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor and a field-effect transistor, and more particularly to a semiconductor device having a bipolar transistor and a field-effect transistor formed on an insulating substrate.

[0002]

2. Description of the Related Art The formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and is used to fabricate a normal Si integrated circuit.
Much research has been done because devices utilizing SOI technology have many advantages that cannot be achieved with i-substrates. That is, by using the SOI technology, 1. Easy dielectric separation and high integration. 2. Excellent radiation resistance. Stray capacitance is reduced, enabling higher speed,
4. 4. Well step can be omitted. 5. Latch-up can be prevented. Advantages such as the possibility of a fully depleted field-effect transistor by thinning can be obtained.

[0003] In order to realize many of the above advantages in device characteristics, researches have been made on a method of forming an SOI structure for several decades. The contents are summarized in, for example, the following documents. Special Issue: "
Single-crystal silicon onnon-single-crystal insula
tors "; edited by GWCullen, Journal of CrystalGro
wth, volume 63, no 3, pp 429-590 (1983).

In the past, on a single crystal sapphire substrate,
SOS (silicon on sapphire), which is formed by heteroepitaxy of Si by CVD (chemical vapor deposition), is known, and although it has achieved some success as the most mature SOI technology, the Si layer and the underlying sapphire A large amount of crystal defects due to the lattice mismatch at the substrate interface, the incorporation of aluminum from the sapphire substrate into the Si layer, and above all, the delay in increasing the cost and the area of the substrate has hindered the spread of its applications. I have. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt can be broadly divided into the following two: After the surface of the Si single crystal substrate is oxidized, a window is opened to partially expose the Si substrate, and the portion is laterally epitaxially grown as a seed to form a Si single crystal layer on SiO ₂ (in this case, see FIG. 4). Involves the deposition of a Si layer on SiO _2. ); The Si single crystal substrate itself is used as an active layer, and SiO ₂ is formed thereunder (this method does not involve the deposition of a Si layer).

Various semiconductor elements and integrated circuits containing them have been fabricated on a silicon layer on an insulator formed by these methods.

[0006]

As means for realizing the above item 1, a method of directly growing a single crystal layer Si in a lateral direction by CVD, a method of depositing amorphous Si,
A method in which solid phase lateral epitaxial growth is performed by heat treatment, an electron beam or a laser is applied to an amorphous or polycrystalline Si layer.
A method of converging and irradiating an energy beam such as light to grow a single crystal layer on SiO ₂ by melting and recrystallization, and a method of scanning a melting region in a band shape by a rod-shaped heater (Zone melting) recrystallization) is known.
Each of these methods has its advantages and disadvantages, but it leaves significant problems in its controllability, productivity, uniformity, and quality.
Nothing has been commercialized yet. For example,
In the CVD method, sacrificial oxidation is required to make the thin film flat, and the solid phase growth method has poor crystallinity. Also, in the beam annealing method, the processing time by the convergent beam scanning and the beam
There is a problem in the controllability such as the degree of overlap of the system and the focus adjustment.
Of these, the Zone Melting Recrystallization method is the most mature, and relatively large-scale integrated circuits have been prototyped. However, many crystal defects such as sub-grain boundaries still remain, and minority carrier devices You haven't made it.

The following two methods, which do not use a Si substrate as a seed for epitaxial growth, are the following two methods: An oxide film is formed on a Si single crystal substrate having a V-shaped groove anisotropically etched on its surface, and a polycrystalline Si layer is deposited on the oxide film as thick as the Si substrate, and then polished from the back surface of the Si substrate. Thereby, a dielectrically separated Si single crystal region surrounded by V grooves is formed on the thick polycrystalline Si layer. In this method, the crystallinity is good, but the process of depositing polycrystalline Si several hundred microns thick, and the process of polishing a single-crystal Si substrate from the back surface to leave only the separated Si active layer are controlled. There is a problem in terms of productivity and productivity; SIMOX (SIMO
X: Separation by ion implanted oxygen) is a method of forming an SiO ₂ layer by implanting oxygen ions into a Si single crystal substrate, and is the most mature method at present because of its good compatibility with the Si process. However, S
In order to form an iO ₂ layer, oxygen ions should be 10 ¹⁸ ion
It is necessary to implant s / cm ² or more, but the implantation time is long, the productivity is not high, and the wafer cost is high. In addition, many crystal defects remain, and are not industrially of sufficient quality to produce minority carrier devices; A method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method uses P-type S
Proton ion implantation of an N-type Si layer on the surface of the i-single crystal substrate (Imai et al., J. Crystal Growth, vol 63, 547 (1983)),
Alternatively, an island is formed by epitaxial growth and patterning, and only the P-type Si substrate is made porous by anodizing in an HF solution so as to surround the Si island from the surface. Is a method of separating the dielectric material from a dielectric. In this method, the separated Si region is determined before the device process, and there is a problem that the degree of freedom in device design may be limited. The features of have not been fully demonstrated.

According to the present invention, there is provided an integrated circuit including a bipolar transistor and a field-effect transistor in a high-quality single-crystal semiconductor layer on an insulating substrate capable of solving the above-mentioned problems and meeting the above-mentioned requirements. It is intended to provide a circuit.

Another object of the present invention is to provide a semiconductor integrated circuit realizing the advantages of the SOI device.

Another object of the present invention is to provide a high-quality integrated circuit on an insulating substrate which can be used as a substitute for expensive SOS or SIMOX even when manufacturing a large-scale integrated circuit having an SOI structure. Also aim.

[0011]

According to the present invention, there is provided a semiconductor device having a bipolar transistor and a field effect transistor, wherein the bipolar transistor and the field effect transistor are formed on an insulating base; The single crystal layer forming the active region of the bipolar transistor and the field effect transistor includes a porous single crystal semiconductor layer and a non-porous single crystal semiconductor layer.
The first base having the structure described above and the second base are interposed via an insulating layer.
Multilayer structure in which the non-porous single crystal semiconductor layer is located inside
After bonding so that the body is obtained , the multilayer structure
A single crystal layer obtained by removing the porous single crystal semiconductor layer .

In the present invention, the insulating layer may be
Insulation formed on the surface of two substrates, for example, a silicon substrate
A material layer can be used. This insulator layer includes a deposited silicon oxide layer, nitride layer, oxynitride layer, tantalum oxide layer, and the like, in addition to the silicon oxide layer formed by surface oxidation.

[0013] The present invention provides an excellent economical property, a uniform flatness over a large area, and extremely excellent crystallinity on an insulating substrate having an insulating layer such as silicon oxide on the surface.
Since an element is formed including a Si single crystal layer having extremely few defects, a bipolar transistor having a reduced capacitance between a substrate and a collector, and an insulated gate field effect transistor having a reduced floating capacitance of a source and a drain are required. Can be manufactured, high speed operation is possible, there is no latch-up phenomenon,
It is possible to provide a circuit having excellent radiation resistance without soft errors due to α rays.

Here, in order to facilitate understanding of the present invention, a general technical description regarding porous silicon and its removal by chemical etching will be described.

[0015] Porous Si is described in 1956 by Uhlir et al.
Was discovered during the research process of electropolishing of semiconductors (A.
Uhlir, Bell Syst. Tech. J., vol 35, p.333 (1956)). In addition, Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in an HF solution requires holes, and the reaction is as follows (T .
Unagami: J. Electrochem. Soc., Vol. 127, p. 476 (198
0)): Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + ( ^{4-λ) e + → SiF} 4 + 4H + + λe- SiF 4 + 2HF → H 2 SiF 6 where, e ⁺ and, e ^- respectively represent a positive hole and an electron. Further, n and λ are the number of holes required for dissolving one atom of silicon, respectively, and it is assumed that porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type silicon having holes is easily made porous. The selectivity in this porosity has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Yasno, Onaka, Kajiwara; IEICE Technical Report, vol 79, SSD 79-9549 (1979)) , And K. Imai; S
olid-State Electronics vol 24,159 (1981)). P-type silicon having holes as described above is easily made porous,
P-type silicon can be selectively made porous.

On the other hand, reports have been made that high-concentration N-type silicon also becomes porous (RP Holmstorm, IJYChi Appl. Phys. Let.)
t. Vol. 42, 386 (1983)).
It is important to select a substrate that can realize porosity.

Further, since the porous layer has a large amount of voids formed therein, the density is reduced to less than half of the original silicon. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the ordinary etching rate of the single crystal layer.

Next, the removal of the porous layer Si by chemical etching will be discussed. In general, P = (2.33-A) /2.33 (1) is called Porosity, and this value can be changed during anodization, and can be expressed as follows: P = (m ₁ −m ₂ ) / (m ₁ −m ₃ ) (2) or P = (m ₁ −m ₂ ) / ρAt (3) where, m ₁ : total weight before anodization m ₂ : after anodization Total weight m ₃ : Total weight after removing porous Si ρ: Density of single crystal Si A: Porous area t: Thickness of porous Si When the area of a region to be porous cannot be accurately calculated There are many. In this case, equation (2) is effective, but in order to measure m ₃ , the porous Si must be etched.

Further, in the above-described epitaxial growth on the porous Si, since the porous Si has a structural property, it is possible to alleviate the strain generated during the heteroepitaxial growth and suppress the generation of defects. . However, also in this case, it is clear that the Porosity of the porous Si is a very important parameter. Therefore, the above measurement of Porosity is also essential in this case.

In the present invention, selective etching is performed using an etching solution having little etching effect on crystalline Si and having an excellent etching effect on porous Si.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Nevertheless, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, 1000 ° C
Above, rearrangement of the internal holes occurs, and the characteristics of the accelerated etching are impaired. For this reason, the Si layer is epitaxially grown by the molecular beam epitaxial growth method or the plasma C method.
CVD method such as VD, low pressure CVD, photo CVD, bias
Low temperature growth such as sputtering or liquid phase growth is preferred.

Hereinafter, embodiments of the semiconductor device of the present invention will be described in detail with reference to the drawings together with a method of manufacturing the same.

[0024]

Embodiment 1 FIG. 1 is a partial sectional view showing an example of the configuration of a semiconductor device according to the present invention. In FIG. 1, 2 is Si
Reference numeral 4 denotes a substrate, and reference numeral 4 denotes an insulating layer formed of a Si oxide film formed on the surface. Three island-shaped single crystal layers 6, 8, and 10 are formed on the insulator layer.

The conductivity type in the island-like single crystal layer 6 is formed in an appropriate pattern as shown in the figure. Further, on the island-like single crystal layer 6, a Si oxide film 12, an insulating layer 14, a base electrode 16, an emitter An electrode 18 and a collector electrode 20 are formed, and N
A PN-type bipolar transistor BT is configured.
Although the bipolar transistor is a planar type in FIG. 1, it may be a lateral type or the like.

The conductivity type in the island-shaped single crystal layer 8 is formed in an appropriate pattern to form a source region S and a drain region D. Further, on the island-shaped single crystal layer 8, a gate oxide film 22, a gate 24, an insulating Layer 14, source electrode 26, drain electrode 2
8 and the gate electrode 30 are formed to form an N-channel field effect transistor NFET.

The conductivity type in the island-shaped single crystal layer 10 is formed in an appropriate pattern to form a source region S and a drain region D. Further, on the island-shaped single crystal layer 10, a gate oxide film 32,
The gate 34, the insulating layer 14, the source electrode 36, the drain electrode 38, and the gate electrode 40 are formed to configure a P-channel field effect transistor PFET.

A first embodiment of the fabrication of the semiconductor device of this configuration example will be described with reference to FIGS.

Here, a method is used in which a P-type substrate or a high-concentration N-type substrate is entirely made porous, and then a single crystal layer is epitaxially grown. FIG. 2 (a) to (c)
Are process drawings for explaining the method of manufacturing a semiconductor substrate according to the present invention, and are shown as schematic cross-sectional views in each process. In FIGS. 2A to 2C, the Si single crystal group
The porous portion of the plate 52 is the porous single crystal semiconductor of the present invention.
And the thin-film single-crystal Si layer 54 is the non-porous thin film of the present invention.
Single crystal semiconductor layers, which serve as the first substrate of the present invention.
And the other Si substrate 58 is the second substrate of the present invention.
And an oxide layer 56 and an insulator layer (silicon oxide layer)
Reference numeral 60 denotes the insulating layer of the present invention, and FIG.
The layer structure is shown.

As shown in FIG. 2A, first, a P-type (or high-concentration N-type) Si single-crystal substrate 52 is prepared, and all of the substrate is made porous. Epitaxial growth is performed on the porous substrate surface to form a thin-film single-crystal Si layer 54. The P-type Si substrate is made porous by an anodizing method using an HF solution. The porous Si layer, the monocrystalline Si as compared with the density of 2.33 g / cm ^3, the density of 1.1~0.6g / cm ³ by changing the density of HF solution concentration to 50 to 20% Range.

As shown in FIG. 2B, the surface of the single crystal Si layer 54 on the porous Si
Is formed, the other Si substrate 58 is prepared, an insulator layer (silicon oxide layer) 60 is formed on the surface thereof, and then the surface of the oxide layer 56 of the single crystal Si layer 54 on the porous Si substrate is formed. The other Si substrate 58 is bonded to the surface of the insulator layer 60. The oxide layer 56 plays an important role in the characteristics of the device to be manufactured. That is, the interface level generated from the base interface of the Si active layer can be lower at the interface of the oxide film than in the case where the bonding is directly performed without the oxide layer 56, and the characteristics of the obtained electronic device are remarkable. improves. Thereafter, only the porous Si is subjected to the electroless wet chemical etching by immersing the whole in an etching solution, and the Si substrate 5 is etched.
The thin nonporous single-crystal silicon layer 54 is formed on the insulator layer 60 of FIG.

FIG. 2C shows a semiconductor substrate obtained by the present invention. That is, a single-crystal Si layer 54 having crystallinity equivalent to that of a silicon wafer is flattened and uniformly thinned on an insulating substrate (Si substrate 58 with an insulator layer 60), and the entire wafer is covered. Area.

The semiconductor substrate thus obtained can be suitably used from the viewpoint of producing an insulated electronic device.

A selective etching method for electroless wet chemical etching of only porous Si will be described below.

An etching solution having no etching effect on crystalline Si and capable of selectively etching only porous Si includes hydrofluoric acid, buffered hydrofluoric acid, hydrofluoric acid to which hydrogen peroxide solution is added, or buffered hydrofluoric acid. A mixed solution of an acid, a mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which an alcohol is added, and a mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which an aqueous solution of hydrogen peroxide and an alcohol are added are suitably used.

FIGS. 3 to 10 are characteristic diagrams showing the etching time dependence of the thickness of the etched porous Si and single-crystal Si when the porous Si and single-crystal Si are infiltrated with the above-mentioned various etching solutions. . The etchants are:
3 is a mixture of 49% hydrofluoric acid and hydrogen peroxide solution (1: 5), FIG. 5 is a mixture of 49% hydrofluoric acid and alcohol (10: 1), FIG. 6 is a mixture (10: 6: 50) of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution,
7 shows buffered hydrofluoric acid, FIG. 8 shows a mixed solution of buffered hydrofluoric acid and hydrogen peroxide solution (1: 5), FIG. 9 shows a mixed solution of buffered hydrofluoric acid and alcohol (10: 1), FIG.
Is a mixed solution (10: 6: 50) of buffered hydrofluoric acid, alcohol and aqueous hydrogen peroxide. In addition, what added alcohol was infiltrated without stirring, and what added no alcohol was infiltrated with stirring.

The porous Si is prepared by anodizing non-porous single-crystal Si, and the conditions are as follows. The starting material of porous Si formed by anodization is single-crystal Si.
However, the present invention is not limited to this, and it is also possible to use Si having another crystal structure: applied voltage: 2.6 (V) current density: 30 (mA · cm ⁻² ) anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) The porous Si prepared under the above conditions is subjected to the above various etchings at room temperature. Infiltrated into the liquid.

When the decrease in the thickness of the porous Si was measured for those infiltrated with 49% hydrofluoric acid (open circles in FIG. 3) with stirring, the porous Si was rapidly etched.
90 μm in about 40 minutes, and 20 minutes after 80 minutes
Even 5 μm was etched uniformly with a high degree of surface properties.

The thickness of the porous Si was measured for a sample in which a mixture of 49% hydrofluoric acid and aqueous hydrogen peroxide (1: 5) (open circles in FIG. 4) was infiltrated with stirring. The porous Si is rapidly etched to 112 μm in about 40 minutes and 256 μm after 80 minutes.
Etching was uniform with high surface properties.

A mixture of 49% hydrofluoric acid and alcohol (1
0: 1) (open circles in FIG. 5) without infiltration, when the decrease in the thickness of the porous Si was measured, the porous Si was rapidly etched, and 85 μm in about 40 minutes. 195 μm after 80 minutes
Also had a high degree of surface properties and was uniformly etched.

The thickness of the porous Si that was infiltrated without stirring into a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and aqueous hydrogen peroxide (open circles in FIG. 6) As a result, the porous Si was rapidly etched, having a high surface property of 107 μm in about 40 minutes and 244 μm after 80 minutes, and was uniformly etched.

When a decrease in the thickness of the porous Si was measured for a sample infiltrated with buffered hydrofluoric acid (open circles in FIG. 7) while stirring, the porous Si was rapidly etched, and was reduced to 70 μm in about 40 minutes. After 120 minutes, the surface was uniformly etched with a high surface property of 118 μm.

When a mixture of buffered hydrofluoric acid and aqueous hydrogen peroxide (1: 5) (open circles in FIG. 8) was infiltrated with stirring, the decrease in the thickness of the porous Si was measured. The quality Si is rapidly etched to 88 μm in about 40 minutes, and 147 μm after 120 minutes.
Etching was uniform with high surface properties.

When a mixture of buffered hydrofluoric acid and alcohol (10: 1) (open circles in FIG. 9) was infiltrated without stirring, the decrease in the thickness of the porous Si was measured. Porous Si is rapidly etched and 40
Minutes, 67 μm, and after 120 minutes, 112 μm.
μm also had a high degree of surface properties and was uniformly etched.

The thickness of the porous Si that was infiltrated without stirring into a mixed solution (10: 6: 50) of buffered hydrofluoric acid, alcohol and aqueous hydrogen peroxide (open circles in FIG. 10) As a result, the porous Si was rapidly etched to 83 μm in about 40 minutes,
After 0 minutes, 140 μm was uniformly etched with a high degree of surface properties.

Although the solution concentration of the hydrogen peroxide solution is 30% here, it is set at a concentration that does not impair the effect of adding the following hydrogen peroxide solution and that is practically acceptable in the manufacturing process and the like. You. As buffered hydrofluoric acid, ammonium fluoride (NH ₄ F) 36.2%, hydrogen fluoride (HF) 4.
A 46% aqueous solution is used.

As the alcohol used for the etching solution, besides ethyl alcohol, alcohol such as isopropyl alcohol which can be practically used in the production process and the like, and which can provide the following alcohol addition effect can be used.

The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid and aqueous hydrogen peroxide.
By adding the hydrogen peroxide solution, the oxidation of silicon can be accelerated, and the reaction rate can be increased as compared with the case without addition. By further changing the ratio of the hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, air bubbles of a reaction product gas by etching can be instantaneously removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently removed.
Can be etched.

The conditions of the solution concentration and the temperature are set within a range in which the effects of hydrofluoric acid, buffered hydrofluoric acid, the above-mentioned hydrogen peroxide solution or the above-mentioned alcohol are exerted, and the etching rate is practically acceptable in the manufacturing process and the like. Here, as an example, the case of the above-mentioned solution concentration and room temperature is taken up,
The present invention is not limited to such conditions.

When using hydrofluoric acid, the HF concentration in the etching solution is preferably set in the range of 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80%.

[0051] When using a buffered hydrofluoric acid, in the etching solution, HF concentration is preferably 1 to 95%, more preferably 1-85%, more preferably set in a range of 1 to 70% NH ₄ F concentration Is preferably 1 to 95
%, More preferably 5 to 90%, still more preferably 5 to 90%.
It is set in the range of 80%.

In the etching solution, the concentration of H ₂ O ₂ is preferably 1 to 95%, more preferably 5 to 90%, and still more preferably 10 to 80%, and is set within a range in which the above-described hydrogen peroxide solution is exhibited. Is done.

In the etching solution, the alcohol concentration is preferably not more than 80%, more preferably not more than 60%, and still more preferably not more than 40%, and is set within a range in which the effect of the alcohol is exerted.

The temperature is set in the range of preferably 0 to 100 ° C., more preferably 5 to 80 ° C., and still more preferably 5 to 60 ° C.

On the other hand, non-porous Si having a thickness of 500 μm was infiltrated into the above various etching solutions at room temperature. Later
The decrease in the thickness of the non-porous Si was measured (FIGS. 3 to 10).
Black circle). Non-porous Si, even after 120 minutes,
Only less than 100 Å was etched.

Porous Si and Non-porous Si after Etching
Was washed with water, and the surface thereof was trace-analyzed by a secondary ion mass spectrometer. No impurities were detected.

The single crystal layer on the surface of the semiconductor substrate obtained in the step of FIG. 2 is separated into islands by a partial oxidation method or etching to form island single crystal layers 6, 8, and 10 in FIG. I do. Incidentally, the insulator layer 4 of FIG.
It is composed of i-layers 56 and 60.

NPN type bipolar transistor B of FIG.
The step of forming T will be described with reference to FIG.

First, as shown in FIG. 11A, N-type impurity ions are implanted into the island-shaped single crystal layer 6 to form a collector region. Next, the oxide film 1 is formed on the surface of the island-shaped single crystal layer 6 by dry oxidation or wet oxidation by pyrogenesis.
2 is formed, and the oxide film is partially removed using photolithography or the like. P-type impurities are diffused from the window thus formed by ion implantation, thermal diffusion or the like to form a base region. Next, an N-type impurity is heavily doped into the emitter region and the collector contact region using a mask pattern formed of a photoresist.

Subsequently, as shown in FIG. 11B, an insulating layer 14 is deposited by using a CVD method, a bias sputtering method or the like. Further, after a contact hole is formed by photolithography and etching, the respective electrodes 16 and 16 of a base region, an emitter region, and a collector contact region are formed.
By forming 18, 18 from Al, Al-Si, W, Mo, W silicide, Ti, Ti silicide, etc., a bipolar transistor can be obtained.

Incidentally, a PNP type bipolar transistor is also
It can be formed in a similar manner by changing the conductivity type of the impurity.

The N-channel field effect transistor N shown in FIG.
A process for forming the FET and the P-channel field effect transistor PFET will be described with reference to FIG.

First, as shown in FIG. 12A, a P-type impurity ion is implanted into the island-shaped single crystal layer 8 and an N-type impurity ion is implanted into the island-shaped single crystal layer 10 independently. Next, gate insulating films 22 and 32 are formed on each of the island-shaped single crystal layers, and gates 24 and 34 of polycrystalline silicon are formed by patterning. Using the polycrystalline silicon gate as a mask, a source region S and a drain region D are formed by ion-implanting impurities in a self-aligned manner. At this time, N-type impurity ions are implanted into the NFET to form the source region S and the drain region D, and P-type impurity ions are implanted into the source region S and the drain region D.

Subsequently, as shown in FIG. 12B, after the insulating layer 14 is formed and the contact holes are formed, the source electrodes 26 and 36, the drain electrodes 28 and 38, and the gate electrodes 30 and 40 are formed. Thereby, an N-channel field-effect transistor and a P-channel field-effect transistor can be obtained.

By using the bipolar transistor and the field effect transistor formed as described above and connecting these electrodes to a circuit configuration as shown in FIG. 13 by, for example, a thin film metal wiring, an integrated circuit is manufactured. can do.

[0066]

Second Embodiment A second embodiment of the fabrication of the semiconductor device having the configuration example shown in FIG. 1 will be described with reference to FIG.

Here, a method will be described in which an N-type layer is formed before the formation of the porous body, and thereafter, only the P-type substrate or the high-concentration N-type substrate is selectively made porous by anodizing. FIGS. 14A to 14D are process diagrams for explaining a method of manufacturing a semiconductor substrate according to the present invention, and are shown as schematic cross-sectional views in each process. FIG.
In (a) to (d), the porous Si substrate 73 is the present invention.
And a single-crystal Si layer 74
The non-porous single crystal semiconductor layers of the invention
And the other Si substrate 76 is
The second substrate of the present invention comprises an insulator layer (silicon oxide layer)
Reference numeral 78 denotes the insulating layer of the present invention, and FIG.
A multilayer structure is shown.

As shown in FIG. 14A, a low impurity concentration layer 74 is formed on the surface of a high-concentration N-type Si single crystal substrate 72 by epitaxial growth using various thin film growth methods.
Alternatively, protons are ion-implanted into the surface of the P-type Si single-crystal substrate 72 to form the N-type single-crystal layer 74.

Next, as shown in FIG.
i single crystal substrate (or high concentration N-type Si single crystal substrate) 72
Is transformed into a porous Si substrate 73 from the rear surface by an anodizing method using an HF solution. The density of this porous Si layer is higher than that of single-crystal Si at 2.33 g / cm ^3.
By changing the F solution concentration to 50 to 20%, the density 1.
It can be changed in the range of 1 to 0.6 g / cm ³ .

As shown in FIG. 14C, the other S
After preparing an i-substrate 76 and forming an insulator layer (silicon oxide layer) 78 on the surface thereof, the surface of the single crystal Si layer 74 on the porous Si substrate and the insulator layer of the other Si substrate 76 are formed. Attach to the surface of 78. Thereafter, only the porous Si is subjected to electroless wet chemical etching by immersing the entirety in an etching solution, and the thin nonporous single-crystal silicon layer 74 is left on the insulator layer 78 of the Si substrate 76 to be formed. .

FIG. 14D shows a semiconductor substrate obtained by the present invention. That is, a single-crystal Si layer 74 having crystallinity equivalent to that of a silicon wafer is flattened and uniformly thinned on an insulating substrate (the Si substrate 76 with the insulating layer 78), and the entire wafer is covered. Area.

Using the semiconductor substrate thus obtained, the semiconductor device of FIG. 1 can be manufactured in the same manner as in the first embodiment. The insulator layer 4 of FIG.
This corresponds to the Si oxide layer 78 shown in FIG.

[0073]

The present invention will be described below with reference to specific examples.

Example 1 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in an HF solution. The conditions of the anodization were as follows: applied voltage: 2.6 (V) current density: 30 (mA · cm ⁻² ) anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%).

The MBE was placed on the P-type (100) porous Si substrate.
An Si epitaxial layer was grown at a low temperature of 0.5 μm by a molecular beam epitaxy (Molecular Beam Epitaxy) method. The deposition conditions are as follows: Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr Growth rate: 0.1 nm / sec.

Next, the surface of the epitaxial layer is
An oxide layer having a thickness of 00 mm is formed, and the oxidized surface is
The other Si substrate on which an oxide layer having a thickness of 000 mm was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

After that, the bonded substrates were mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ .

As a result of observation of the cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

The NPN type bipolar transistor, the N-channel field effect transistor and the P-type
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 2 A P-type (100) single-crystal Si substrate having a thickness of 200 μm was anodized in an HF solution. The conditions of the anodization were as follows: applied voltage: 2.6 (V) current density: 30 (mA · cm ⁻² ) anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%).

On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by a plasma CVD method. The deposition conditions are as follows: Gas: SiH ₄ RF power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 2.5 nm / sec.

Next, 10 .ANG.
An oxide layer having a thickness of 00 mm is formed, and the oxidized surface is
The other Si substrate on which an oxide layer having a thickness of 000 mm was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ .

As a result of observation of the cross section with a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

An NPN type bipolar transistor, an N-channel field effect transistor and a P-type
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 3 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in an HF solution. The conditions of the anodization were as follows: applied voltage: 2.6 (V) current density: 30 (mA · cm ⁻² ) anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%).

A 0.5 μm low-temperature Si epitaxial layer was grown on the P-type (100) porous Si substrate by bias sputtering. The deposition conditions are as follows: RF frequency: 100 MHz High frequency power: 600 W Temperature: 300 ° C. Ar gas pressure: 8 × 10 ^-3 Torr Growth time: 60 minutes Target DC bias: -200 V Substrate DC Bias: +5 V.

Next, the surface of the epitaxial layer is
An oxide layer having a thickness of 00 mm is formed, and the oxidized surface is
The other Si substrate on which an oxide layer having a thickness of 000 mm was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Then, the bonded substrates were mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a film thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ .

As a result of the cross-sectional observation with a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

The NPN type bipolar transistor, the N-channel field effect transistor and the P-type
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 4 An N-type (100) single-crystal Si substrate having a thickness of 200 μm was anodized in an HF solution. The conditions of the anodization were as follows: applied voltage: 2.6 (V) current density: 30 (mA · cm ⁻² ) anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%).

A Si epitaxial layer was grown on the N-type (100) porous Si substrate at a low temperature of 5 μm by a liquid phase growth method. The growth conditions are as follows: solvent: Sn growth temperature: 900 ° C. growth atmosphere: H ₂ growth time: 50 minutes.

Next, 10 .ANG.
An oxide layer having a thickness of 00 mm is formed, and the oxidized surface is
The other Si substrate on which an oxide layer having a thickness of 000 mm was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a film thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 5 μm was formed on SiO ₂ .

As a result of observing the cross section with a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

The NPN type bipolar transistor, the N channel field effect transistor and the P
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 5 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in an HF solution. The conditions of the anodization were as follows: applied voltage: 2.6 (V) current density: 30 (mA · cm ⁻² ) anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%).

The P-type (100) porous Si substrate was subjected to reduced pressure CV
By the method D, a Si epitaxial layer was grown at a low temperature of 1.0 μm. The deposition conditions are as follows: Source gas: SiH ₄ Carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 3.3 nm / sec.

Next, 10 .ANG.
An oxide layer having a thickness of 00 mm is formed, and the oxidized surface is
The other Si substrate on which an oxide layer having a thickness of 000 mm was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a film thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 1.0 μm was formed on SiO ₂ .

When SiH ₂ Cl ₂ was used as the source gas, it was necessary to raise the growth temperature by several tens of degrees, but the accelerated etching characteristic peculiar to the porous substrate was maintained.

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

The NPN type bipolar transistor, the N-channel field effect transistor and the P-type
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 6 A Si epitaxial layer was grown to 1 μm on a P-type (100) Si substrate having a thickness of 200 μm by CVD. The deposition conditions were as follows: Reactant gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 liter / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min.

This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / mi.
n. P-type (100) Si with a thickness of 200 microns
The entire substrate was made porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, 10 .ANG.
An oxide layer having a thickness of 00 mm is formed, and the oxidized surface is
The other Si substrate on which an oxide layer having a thickness of 000 mm was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a film thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 1 μm was formed on SiO ₂ .

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

An NPN bipolar transistor, an N-channel field effect transistor and a P-type
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 7 A 5 μm Si epitaxial layer was grown on a P-type (100) Si substrate having a thickness of 200 μm by CVD. The deposition conditions were as follows: Reactant gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 liter / min. Temperature: 1080 ° C. Pressure: 760 Torr Time: 1 min.

This Si substrate was anodized in an HF solution. The conditions of the anodization were as follows: applied voltage: 2.6 (V) current density: 30 (mA · cm ⁻² ) anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%).

As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, 10 .ANG.
An oxide layer having a thickness of 00 mm is formed, and the oxidized surface is
The other Si substrate on which an oxide layer having a thickness of 000 mm was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a film thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 5 μm was formed on SiO ₂ .

As a result of observation of a cross section by a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

The NPN bipolar transistor, the N-channel field effect transistor and the P-channel
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 8 An N-type Si layer having a thickness of 1 μm was formed on the surface of a P-type (100) Si substrate having a thickness of 200 μm by ion implantation of protons. The H ⁺ injection volume was 5 ^× 10 ¹⁵ (ions / cm ² ).

The substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / mi.
n. P-type (100) Si with a thickness of 200 microns
The entire substrate was made porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the N-type Si layer did not change.

Next, the surface of the N-type Si layer is 1000 °
A thick oxide layer is formed, and on the oxidized surface, 5000
(4) The other Si substrate on which the thick oxide layer was formed was overlaid and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Thereafter, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of about 200 μm was removed, and a single-crystal Si layer having a thickness of 1 μm was formed on SiO ₂ .

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

An NPN-type bipolar transistor, an N-channel field-effect transistor and a P-type
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

Example 9 A P-type (100) single crystal Si substrate having a thickness of 500 μm was anodized in a 50% HF solution. The current density at this time is 10 mA / c
It was m ^2. In 10 minutes, a porous layer having a thickness of 20 microns was formed on the surface. On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by a low pressure CVD method. The deposition conditions are as follows: Reaction gas flow rate: SiH ₂ Cl ₂ 0.6 l / min. H ₂ 100 l / min. Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min.

Next, the surface of this epitaxial layer was
nm. 0.8 μm on the surface of the thermal oxide film
The other Si substrate on which the m-thick oxide layer was formed was overlaid and heated at 900 ° C. for 1.5 hours in an oxygen atmosphere, whereby the two substrates were firmly joined.

Next, polishing was performed on the back surface of the Si substrate by polishing.
By removing 90 μm, the porous layer was exposed.

Thereafter, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 1
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 15 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

The NPN bipolar transistor, the N-channel field effect transistor and the P-type
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

(Example 10) A 1-micron Si epitaxial layer was grown on a P-type (100) Si substrate having a thickness of 200 microns by CVD. The deposition conditions were as follows: Reactant gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 liter / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min.

The substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm /
min, P-type (100) with a thickness of 200 microns
The entire Si substrate was made porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, another Si substrate having an oxide layer having a thickness of 0.8 μm formed on the surface of the epitaxial layer was superimposed and heated at 900 ° C. for 1.5 hours in an oxygen atmosphere. The substrate was firmly bonded.

Thereafter, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50) and selective etching was performed without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
Angstroms or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 1 μm was formed on SiO ₂ .

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

An NPN bipolar transistor, an N-channel field effect transistor, and a P-type bipolar transistor are formed on the single-crystal silicon layer by a conventional method as described in the first embodiment.
An integrated circuit was fabricated by fabricating and interconnecting channel field effect transistors.

[0146]

As described above in detail, in the semiconductor device according to the present invention, the element is formed on the high-quality single crystal layer formed on the insulating substrate by selectively removing the porous substrate. An integrated circuit composed of high performance bipolar transistors and field effect transistors is obtained.
That is, a bipolar transistor having a small capacitance between the base and the collector and having no soft error due to α rays and a field effect transistor having a small stray capacitance and having no latch-up phenomenon can be manufactured. It is possible to provide an integrated circuit that can exhibit various advantages as an SOI, such as being capable of operation, at a low price.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing one configuration example of a semiconductor device according to the present invention.

FIG. 2 is a process chart showing a method for manufacturing a substrate of the semiconductor device in FIG. 1;

FIG. 3 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 4 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 5 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 6 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 7 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 8 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 9 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 10 is a diagram showing etching characteristics of porous Si and non-porous Si.

11 is a process chart showing a method for manufacturing the bipolar transistor of the semiconductor device in FIG. 1;

12 is a process chart illustrating a method for manufacturing the field-effect transistor of the semiconductor device in FIG. 1;

FIG. 13 is a diagram illustrating a circuit configuration of the semiconductor device of FIG. 1;

14 is a process chart illustrating a method for manufacturing the substrate of the semiconductor device in FIG. 1;

[Explanation of symbols]

 2 Si substrate 4 Insulator layer 6, 8, 10 Island-shaped single crystal layer 12 Si oxide film 14 Insulating layer 16 Base electrode 18 Emitter electrode 20 Collector electrode 22, 32 Gate oxide film 24, 34 Gate 26, 36 Source electrode 28, Reference Signs List 38 Drain electrode 30, 40 Gate electrode 52 Si substrate 54 Single crystal Si layer 56 Oxide layer 58 Si substrate 60 Insulator layer 72 Si substrate 73 Porous Si substrate 74 Single crystal Si layer 76 Si substrate 78 Insulator layer BT Bipolar transistor NFET , PFET field effect transistor

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 21/336 H01L 27/06 H01L 27/12 H01L 29/786

Claims (1)

(57) [Claims] 1. A semiconductor device having a bipolar transistor and a field-effect transistor, wherein the bipolar transistor and the field-effect transistor are formed on an insulating substrate, and form active regions of the bipolar transistor and the field-effect transistor. The single crystal layer includes a porous single crystal semiconductor layer and a non-porous single crystal semiconductor layer.
A first base having a layer and a second base via an insulating layer.
The multi-layer in which the non-porous single-crystal semiconductor layer is located inside
After bonding so that a structure is obtained , the multilayer structure
A semiconductor device, which is a single crystal layer obtained by removing the porous single crystal semiconductor layer from a body .