JP3086043B2 - Semiconductor read-only memory sense amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit used for a semiconductor read only memory (ROM).

[0002]

2. Description of the Related Art Generally, in a semiconductor memory in which each memory cell is composed of one MOS transistor, data is written to the memory cell by changing the threshold voltage of the MOS transistor as the memory cell. I have. Then, the data written in the memory cell is applied to the current capacity of the memory cell and the load MOS by the sense amplifier circuit.
The voltage is converted based on the current capability of the transistor and detected.

As such a sense amplifier circuit, there is a conventional one as shown in FIG. This sense amplifier circuit connects the data line 7 to the memory cell 6 via the column selector 5.
The bit line 8 which is the output line of is connected. A column selection line 9 is connected to the gate of the column selector 5, and a word line 10 is connected to the gate of the memory cell 6.

In such a configuration, the column selection line 9
When the potential of word line 10 attains _VDD level, memory cell 6 is selected. When the memory cell 6 has a low threshold voltage, the data line is at "H" level (high level).
If so, the memory cell 6 is discharged by the discharge current,
If the data line 7 is at “L” level (low level), the inverter circuit 4 charges the load transistors 1 and 2 via the NMOS transistor 3.

As a result, as shown in FIG. 4A, the potential V _DATA of the data line 7 is stabilized at V _B at which the charging current of the load transistors 1 and 2 and the discharging current of the memory cell 6 are in an equilibrium state. At this time, the sense output SA _OUT is set to the “L” level.

On the other hand, when memory cell 6 has a high threshold voltage, almost no current flows in memory cell 6, and therefore, when data line 7 (bit line 8) is at "L" level,
The inverter circuit 4 detects the potential of the data line 7, the output thereof becomes “H” level, and the load transistors 1 and 2 are charged via the NMOS transistor 3.

When the potential of the data line 7 reaches V _A , as shown in FIG.
Is turned off, and the sense output SA _OUT reaches the V _DD level by the load transistor 1.

[0008]

In the conventional sense amplifier circuit, the current capability of the load transistors 1 and 2 is determined by the current capability of the memory cell 6. That is, when the current capabilities of the load transistors 1 and 2 are larger than necessary, the charging speed of the data line 7 is high, that is, the potential of the data line 7 is changed from the "L" level (worst case, 0V) to the predetermined "H" level Although the transition time to the data line 7 becomes faster, the transition time of the potential of the data line 7 from the “H” level to the “L” level becomes longer. As a result, the "L" level of the sense output SA _OUT
Since the level deteriorates, the amplitude decreases and the margin decreases.

For this reason, the current capability of the load transistors 1 and 2 is optimally set in association with the current capability of the memory cell 6, so that when the current of the memory cell 6 becomes smaller due to miniaturization or the like, the speed is increased. Becomes very difficult. In particular, it takes time for the potential of the data line 7 to transition from the “L” level to the “H” level.

The present invention solves such a problem of the prior art, in which the transition time of the data line from the "L" level to the "H" level can be shortened without reducing the amplitude of the sense output. It is an object of the present invention to provide a sense amplifier circuit of a semiconductor read-only memory that can perform a high-speed read operation of the semiconductor read-only memory.

[0011]

A sense amplifier circuit of a semiconductor read-only memory according to the present invention has a potential having an inverter having a data line connected to a bit line as an output line of a memory cell via a selection circuit as an input. A gate terminal is connected to a detection circuit and an output of the potential detection circuit, and a drain terminal is connected to a charging circuit or a power supply line to charge the data line.
A first charging NMOS transistor, and the first charging NM
A gate end and a drain end are connected to a source end of the OS transistor, and a source end is connected to the data line . A second charging NMOS transistor for charging the data line, and a gate end is connected to an output of the potential detection circuit. Connected, and the source end is connected to the data line, and the data line
A current detection NMOS transistor for detecting a current and a current detection circuit having a current detection load device connected in series to the current detection NMOS transistor are provided, thereby achieving the above object.

[0012]

According to the above arrangement, the first charging NMOS transistor and the second charging NMOS transistor connected in series to the first charging NMOS transistor provide high-speed charging to near the inversion voltage of the sense amplifier connected to the sense amplifier circuit. It becomes possible.

[0013]

Embodiments of the present invention will be described below.

FIG. 1 shows a circuit configuration of a sense amplifier circuit of a semiconductor read-only memory according to the present invention. A bit line 8 which is an output line of a memory cell 6 is connected to a data line 7 via a column selector 5. A column selection line 9 is connected to the gate of the column selector 5, and a word line 10 is connected to the gate of the memory cell 6.

In addition, an inverter circuit 4, a charging NMOS transistor 12, a charging NMOS transistor 11 and an NMOS transistor 3 are connected to the data line 7, and the load transistors 1 and 2 are connected to the drain side of the NMOS transistor 3. . The specific connection form between the charging NMOS transistors 11 and 12 and another device is as follows.

That is, the charging NMOS transistor 12
Has a gate terminal connected to the output of the inverter 4 and a source terminal connected to a gate terminal and a drain terminal of the charging NMOS transistor 11. The source terminal of the charging NMOS transistor 11 is connected to the data line 7.

In the above configuration, when the potentials of the column selection line 9 and the word line 10 reach the V _DD level, the memory cell 6 is selected. When the potential _{VDATA of the} data line 7 (bit line 8) is at the "L" level, the bit line 8 has its output at the "H" level by the inverter circuit 4 detecting the potential of the data line. Thus, charging is performed from the load transistors 1 and 2.

Subsequently, the charging NMOS transistors 11 and 12 having a larger charging ability are also turned on, and charging is performed. Thereby, the transition time of the data line 7 from the “L” level to the “H” level can be reduced.

Then, as shown in FIG. 2A, when the potential of the data line 7 reaches V _C near the inversion voltage of the sense amplifier, the charging NMOS transistors 11 and 12 are turned off,
Charging ends. Further, the data line 7 is charged by the load transistors 1 and 2 in the vicinity of the inversion voltage (V _Dの_VA ) of the sense amplifier where a high gain is obtained.

As can be seen from FIG. 2B, when the memory cell 6 has a high threshold voltage, the potential of the data line 7 is stabilized at _VA , and the sense output SA _OUT becomes V _DD .

On the other hand, as can be seen from FIG. 2A, when the memory cell 6 has a low threshold voltage, the load transistors 1 and
2 (I ₁ + I ₂ ) and the discharge current I of the memory cell 6
₃ is stabilized at V _B at which the balance is obtained, and the sense output SA _OUT is also at the “L” level.

[0022]

According to the sense amplifier circuit of the semiconductor read-only memory of the present invention described above, a circuit configuration is provided in which the first charging NMOS transistor and the second charging NMOS transistor having a large charging capability are provided. It is possible to perform high-speed charging up to the vicinity of the inversion voltage of the sense amplifier without impairing high gain. Therefore, according to the present invention, a high-speed read operation of the semiconductor read-only memory can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a sense amplifier circuit of a semiconductor read-only memory of the present invention.

FIG. 2 is a graph showing characteristics of a sense amplifier circuit of the semiconductor read-only memory of the present invention.

FIG. 3 is a circuit diagram showing a conventional example of a sense amplifier circuit.

FIG. 4 is a graph showing characteristics of the sense amplifier circuit shown in FIG. 3;

[Explanation of symbols]

 1, 2 Load transistor 3 NMOS transistor 4 Inverter circuit 5 Column selector 6 Memory cell 7 Data line 8 Bit line 9 Column select line 10 Word line 11, 12 Charge NMOS transistor

Claims (1)

(57) [Claims] A potential detection circuit having an inverter inputting a data line connected to a bit line, which is an output line of a memory cell, via a selection circuit; a gate terminal connected to an output of the potential detection circuit; The drain terminal is connected to a charging circuit or a power supply line, and the data line
A first charging NMOS transistor that charges the data line, a second charging terminal that has a gate terminal and a drain terminal connected to a source terminal of the first charging NMOS transistor, and a source terminal connected to the data line, and charges the data line. NMO
An S transistor and a gate terminal are connected to an output of the potential detection circuit, and a source terminal is connected to the data line, and a current is detected from the data line.
Sense amplifier circuit of a semiconductor read only memory comprising a current sensing circuit having a current detecting load devices connected in series to the NMOS transistor and said current detector NMOS transistor current sensing and out.