JP2924451B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundancy circuit.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional semiconductor memory device includes a plurality of memory cells arranged in a matrix in a row direction and a column direction, respectively, and stores data in a memory cell selected by an address signal AD. A plurality of memory cell arrays MA1 to MA4 for writing and storing and reading data stored in the memory cells, and defective memory cells exist in corresponding memory cell arrays provided corresponding to the respective memory cell arrays MA1 to MA4. A plurality of redundancy memory cell arrays RMA1 to RMA4 which are selected when writing and storing and reading data in place of the defective memory cells, and the corresponding memory cell arrays provided corresponding to these redundancy memory cell arrays RMA1 to RMA4, respectively. When there is a defective memory cell And a plurality of redundancy address determination circuits 1 for outputting a redundancy address selection signal RASS which becomes an active level when an address signal AD designates the stored address, and each of these redundancy address determinations. When the redundancy address selection signal RAS from the circuit 1 is at the active level, a plurality of redundancy address selection circuits RAS1 to RAS4 for selecting a corresponding redundancy memory cell array (RAM1 to RAM4) are provided. Memory cell arrays MA1 to MA4
When a defective memory cell exists in a memory cell, a redundancy memory cell array (RMA) is usually provided in units of rows or columns.
1 to RMA4).

Since much of the power of the semiconductor memory device is consumed by the operation of the memory cell arrays MA1 to MA4, the memory cell array is usually divided in this manner and the memory cell array not including the address specified by the address signal AD. Is performing a partial operation so as not to operate. The redundancy memory cell arrays R correspond to these memory cell arrays MA1 to MA4, respectively.
MA1 to RMA4 and a redundancy address circuit 1 are provided.

[0004]

As the storage capacity of a semiconductor memory device, that is, the number of memory cells increases, the number of defective memory cells per semiconductor memory device tends to increase. Therefore, in order to enhance the redundancy function,
Although it is necessary to increase the redundancy address determination circuit and the redundancy address selection circuit, in the above-described conventional semiconductor memory device, the redundancy address selection circuit RAS
1 to RAS4 and the respective redundancy address determination circuits 1 correspond to each other, and the number of redundancy control signal lines 3a increases, and there is a spatial restriction on the arrangement of circuits for realizing the redundancy function and the routing of wirings. There is a problem that the redundancy cannot be strengthened in accordance with the increase in capacity.

It is an object of the present invention to provide a semiconductor memory device which can reduce restrictions such as routing of a redundancy control signal line and can enhance a redundancy function corresponding to a storage capacity.

[0006]

A semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a matrix in a row direction and a column direction, respectively, and writes and stores data in the memory cells selected by an address signal. A plurality of memory cell arrays for reading data stored in the memory cells; and a memory cell array provided corresponding to each of the memory cell arrays, selected when a defective memory cell exists in the corresponding memory cell array, and A plurality of rows for writing, storing and reading data in place of cells
When a defective memory cell is present in a corresponding redundant memory cell array provided in correspondence with each of the redundant memory cell arrays formed of columns and the corresponding memory cell array, the address of the defective memory cell is stored, and the address signal is used as an address signal. A plurality of redundancy address determination circuits that output a redundancy address selection signal that becomes an active level when a stored address is specified, and an encoding circuit that encodes a redundancy address selection signal from each of the redundancy address determination circuits into a binary number when the redundancy memory cell array and decoding circuit for decoding the code signal from the encoding circuit based on the redundancy address selection signal, the redundancy address selection signal from the decoding circuit corresponding when active level And having a plurality of redundancy address selection circuit for selecting.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory device shown in FIG. 6 in that each redundancy address determination circuit 1 and redundancy address selection circuits RAS1-R
AS4, the redundancy address selection signal RASS from each redundancy address determination circuit 1 is converted into a binary number.
Encoding circuit 2 for encoding and converting to a predetermined code RAC
And decoding circuits DC1 to DC4 for decoding the code RAC from the encoding circuit 2 into the original redundancy address selection signal RASS.

One of the memory cell arrays MA1 to MA4 operates for one address signal AD in order to reduce power consumption. Therefore, when a defective memory cell exists in the memory cell arrays MA1 to MA4, only one of the plurality of redundancy address selection signals RASS becomes active level. That is, in this embodiment, since it is sufficient to determine which of the eight redundancy address selection signals RASS is at the active level and to code its position. Is possible. In addition to the case where all the redundancy address selection signals RASS are not at the active level, the code RAC has 4 bits. FIG. 2 shows a specific example of such an encoding circuit 2 and decoding circuits DC1 to DC4.
And FIG.

That is, in the conventional example, eight redundancy control signal lines 3a are required, but in this embodiment, the number can be reduced to four.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

In this embodiment, the number of the redundancy address determination circuits 1 to be installed is reduced by the redundancy memory cell array RMA.
1 to RMA4 (8) less than the number of installations (4), and the encoding circuit 2a provides the redundancy memory cell arrays RMA1 to RMA1.
A program circuit provided with a program element for enabling selection of a predetermined one of RMAs 4; the output signal of the program circuit and the redundancy address selection signal RASS from the redundancy address determination circuit 1 are integrated into one and a predetermined Is converted to a circuit RACa.

FIG. 5 shows a specific circuit example of the encoding circuit 2a. The encoding circuit 2a includes a fuse circuit 21 of a program circuit for determining which redundancy memory cell array can be selected by cutting and non-cutting of the fuses F1 to F4, an output signal of the fuse circuit 21, and a redundancy address selection signal. RAS and logic gates G7 to G10 that generate code RACa by integrating them into one.

In this embodiment, the fuse circuit 21
The fuses F1 to F4 allow the code output from the encoding circuit 2a to be set after the circuit of the semiconductor memory device is manufactured, so that it can be associated with an arbitrary redundancy memory cell array according to the address of the defective memory cell. it can.

Further, since it is rare that all the redundancy memory arrays are used up, the number of the redundancy address determination circuits 1 is made smaller than that of the redundancy memory arrays. .

In this embodiment, there is an advantage that the size of the semiconductor memory device can be reduced by reducing the redundancy address determination circuit 1.

[0018]

As described above, according to the present invention, the judgment result of the redundancy address judgment circuit is provided between the redundancy address judgment circuit and the redundancy address selection circuit.
By inserting a coding circuit for coding into a binary number and a decoding circuit for decoding the output code of the coding circuit, the number of redundancy control signal lines can be reduced. There is an effect that the restriction such as the routing of the control signal line is reduced, and the redundancy function that can be easily stored is enhanced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the encoding circuit of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a specific example of the decoding circuit of the embodiment shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific example of the encoding circuit of the embodiment shown in FIG.

FIG. 6 is a block diagram illustrating an example of a conventional semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 1 redundancy address determination circuit 2, 2a encoding circuit 21 fuse circuit DC1 to DC4 decoding circuit G1 to G10 logic gate MA1 to MA4 memory cell array Q1 to Q4 transistor RAS1 to RAS4 redundancy address selection circuit RMA1 to RMA4 redundancy memory cell array

Claims (4)

(57) [Claims] A plurality of memory cells arranged in a matrix in a row direction and a column direction, wherein data is written and stored in the memory cells selected by an address signal, and data stored in the memory cells is read. A plurality of memory cell arrays to be output, and a memory cell array provided in correspondence with each of the memory cell arrays. When a defective memory cell is present in the corresponding memory cell array, the memory cell array is selected to perform data writing, storage and reading in place of the defective memory cell. A redundancy memory cell array comprising a plurality of rows or columns to be performed;
When a defective memory cell exists in the corresponding memory cell array provided in correspondence with each of the redundancy memory cell arrays, the address of the defective memory cell is stored, and the address signal specifies the stored address. A plurality of redundancy address determination circuits that output a redundancy address selection signal that becomes an active level, an encoding circuit that encodes the redundancy address selection signal from each of the redundancy address determination circuits into a binary number, A decoding circuit for decoding the code signal into the original redundancy address selection signal; and a plurality of redundancy address selection circuits for selecting the corresponding redundancy memory cell array when the redundancy address selection signal from the decoding circuit is at the active level. The semiconductor memory device characterized by having a. 2. A signal which indicates a state in which all redundancy address selection signals are unselected in addition to the code signal, and is added to the decoding circuit.
The semiconductor memory device according to claim 1. Wherein less than the number placed in redundancy address decision circuit redundancy memory cell array number of installed, the encoding circuit comprises a circuit having a programming element that can be selected for a predetermined one of said redundancy memory cell array in the configuration, the output signal of the program circuit, a semiconductor memory device according to claim 1 or 2 integrated with coded signals into binary said characterized by comprising in addition to the decoding circuit. 4. The semiconductor memory device according to claim 3, wherein a redundancy memory cell array that can be selected by a program element of a program circuit is determined at the time of a redundancy replacement process.