JP2918531B1 - Cache memory controller - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To improve the probability that data of a read request exists in a low-speed cache memory by effectively utilizing the capacity of a low-speed cache memory. A cache memory control device stores, for a plurality of data stored in the two cache memories, an address for individual data and management information indicating which cache memory is present in the TAG.
The data is stored in the high-speed small-capacity cache 1 so that the storage contents of the memory 7 and the two cache memories are different from each other.
Alternatively, when a write unit 9 that writes data to one of the low-speed and large-capacity caches 2 and writes data management information to the TAG memory 7 and a data read request are received,
A reading unit for reading data management information from the TAG memory and reading data from either the high-speed small-capacity cache or the low-speed large-capacity cache based on the management information;

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache memory control device for controlling a cache memory, and more particularly to a cache memory control device for controlling a high-speed small-capacity cache memory and a low-speed large-capacity cache memory.

[0002]

2. Description of the Related Art Generally, an information processing system such as a computer includes a cache memory device as a buffer device located between a main storage device and a processor such as a CPU. There is a demand for configuring a cache memory device so as to maximize the performance of the processor.

In the conventional cache memory device, the cache memory is constituted by a high-speed RAM such as an SRAM.
According to this configuration, when data exists in the cache memory, the data is read at high speed.

However, since the high-speed RAM is expensive, if a cache memory having a required capacity is constituted by the high-speed RAM, the cost becomes extremely high. Further, since the high-speed RAM does not have a high integration density, if a cache memory having a necessary capacity is constituted by the high-speed RAM, the chip area increases. For this reason, when a cache memory is constituted by a high-speed RAM, the capacity must be reduced, and the hit rate in the cache memory is reduced. As a result, when there are many miss hits, data is frequently read from the main storage device, which hinders speeding up.

On the other hand, there has conventionally been a cache memory device in which the cache memory is constituted by a low-speed RAM such as a DRAM. However, in this cache memory device, although the hit rate in the cache memory can be improved, high-speed data reading cannot be realized.

Accordingly, there is a technique disclosed in Japanese Patent Application Laid-Open No. 5-35589 (hereinafter referred to as a conventional improved technique). According to this conventional improvement, a cache memory system for controlling a cache memory having a hierarchical structure is disclosed. This cache memory system includes a high-speed small-capacity cache memory, a low-speed large-capacity cache memory, and a control unit that controls these. The control operation is, for example, an operation of supplying an address to the cache memory and reading data, an operation of reading data from the main memory and writing the data to the cache memory, and the like.

In the conventional improved cache memory system, a high-speed small-capacity memory such as an SRAM is an upper-layer cache memory, and a low-speed large-capacity memory such as a DRAM is a lower-layer cache memory, and is written in the high-speed small-capacity cache memory. The data to be written is also written in the low-speed large-capacity cache memory.

In response to a data read request,
First, the high-speed small-capacity cache memory is accessed, and when a hit occurs, data is read from the high-speed small-capacity cache memory. If the high-speed small-capacity cache memory does not have the data, the low-speed large-capacity cache memory is accessed. If a hit occurs, data is read from the low-speed small-capacity cache memory.

According to this conventional improvement technique, compared with the case where the cache memory is constituted only by a high-speed small-capacity memory,
The frequency of reading data by accessing the main storage device can be reduced, and high-speed reading of data can be realized as compared with the case where the cache memory is constituted only by a low-speed large-capacity memory.

[0010]

However, the above-mentioned prior art has the following problems. That is,
The low-speed cache memory, which is the lower hierarchy, stores all the data stored in the high-speed, small-capacity cache memory, which is the upper hierarchy, and wastes the storage contents of the low-speed, large-capacity cache memory. Therefore, the probability that the data of the read request exists in the low-speed large-capacity cache memory is reduced.

In the related art, the control unit operates as follows even when reading data existing only in the low-speed large-capacity cache memory. That is,
The control unit first checks whether the data of the read request exists in the high-speed cache memory, and when it is determined that the data does not exist, first checks whether the data of the read request exists in the low-speed cache memory and determines that the data exists. , Data is read from the address. Therefore, the operation of reading data from the low-speed cache memory is delayed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a control device for controlling a high-speed cache memory and a low-speed cache memory by effectively utilizing the capacity of the low-speed cache memory. It is an object of the present invention to provide a device which can improve the probability that the data of the read request exists in the low-speed cache memory and can quickly read the data from the low-speed cache memory.

[0013]

In order to achieve the above object, a cache memory control device according to a first aspect of the present invention comprises a high-speed small-capacity first cache memory and a low-speed large-capacity second cache memory. In the controlling cache memory control device, for a plurality of data stored in the first cache memory,
First management information storage means for storing an address on the first cache memory and management information indicating that the address is in the first cache memory; a plurality of data stored in the first cache memory; For a plurality of data stored in the memory, for each individual data, a cache memory in which the data is stored
A second management information storage means for storing the above address and management information indicating which cache memory is in the cache memory; and a data storage device for storing the storage content of the first cache memory and the storage content of the second cache memory. The first
When the data is written to either the cache memory or the second cache memory and the data is written to the first cache memory, the management information of the data is stored in the second management information storage unit and the first management information. A writing unit that writes the management information of the data to the second management information storage unit; and a data read command unit that issues a data read request when the data is written to the second cache memory. When a data read request is received by the data read command means, the data management information is read from at least one of the first management information storage means or the second management information storage means, and based on the management information, From either the first cache memory or the second cache memory And reading means for reading the data,
Wherein the read means is connected to an arithmetic and control unit via a system bus, and in response to a data read request from the arithmetic and control apparatus, stores the data management information in the second management information storage means. And reading the data from either the first cache memory or the second cache memory when the read operation based on the data read request by the data read command means is not performed.

According to a second aspect of the present invention, in the cache memory control device according to the first aspect, the first management information storage means is a high-speed operation memory, and the second management information storage means is a low-speed operation memory. The system bus is connected to a main storage device and system bus use right granting means for giving a right to use the system bus, and the reading means responds to a data read request by the data read command means. On the other hand, the first management information storage means and the second management information storage means are accessed, and it is determined from the management information sent from the first management information storage means that the data does not exist in the first cache memory. In this case, a request signal for a system bus use right is sent to the system bus use right granting means, and the management information sent from the second management information storage means is transmitted. From the above, when it is determined that the data does not exist in both the first cache memory and the second cache memory, the main storage device is determined based on the system bus usage right granted by the system bus usage right granting means. Is what you access.

[0015]

Preferred embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of a cache memory control system including the cache memory control device according to the first embodiment.

(1-1) Configuration of Cache Memory Control System The cache memory control system includes a high-speed small-capacity cache memory (hereinafter, referred to as a high-speed small-capacity cache) 1 and a low-speed large-capacity cache memory (hereinafter, referred to as a low-speed large-capacity cache). 2, a cache memory control device for controlling these cache memories 1 and 2, and a system bus 3
And a main storage device 4 connected to the cache memory control device via the I / O controller 5.

A peripheral device (not shown) is connected to the I / O controller 5.

(1-2) Each Unit of the Cache Memory Control Device Hereinafter, each unit constituting the cache memory control device will be described.

(1) First TAG Memory and Second TAG Memory The first TAG memory 31 has an address for individual data and an indication that the plurality of data stored in the high-speed small-capacity cache 1 are in the high-speed small-capacity cache 1. Is stored.

The second TAG memory 32 stores, for a plurality of data stored in the high-speed small-capacity cache 1 and a plurality of data stored in the low-speed large-capacity cache 2, addresses for individual data and The management information indicating whether the cache memory exists in the cache memory is stored.

(2) Data read command section The data read command section 8 issues a data read request to a read section described later.

(3) Write Unit The write unit 9 has a write control unit 10 and a write data path selection unit 14.

The write control unit 10 sends information indicating that data is to be written to either the high-speed small-capacity cache 1 or the low-speed large-capacity cache 2 and data to be written to the write data path selecting unit. Is written to the high-speed and small-capacity cache 1, data management information is written to the first TAG memory 31 and the second TAG memory 32, and data is written to the low-speed and large-capacity cache 2.
If the data management information is written in the second TAG,
Write to memory 32. Write data path selector 1
4 writes the data sent from the write control unit 10 to either the high-speed small-capacity cache 1 or the low-speed large-capacity cache 2 based on the information sent from the write control unit 10.

(4) Reading Unit The reading unit 11 has a reading control unit 12 and a reading data path selecting unit.

When receiving a data read request from the data read command unit 8, the read control unit 12
The management information of the data is read from at least one of the TAG memory 31 and the second TAG memory 32. Then, the read control unit 12 sends the management information to the read data path selecting unit 14 and transfers the data from either the high-speed small-capacity cache 1 or the low-speed large-capacity cache 2 via the read data path selecting unit 14. read out.

In response to a data read request from the arithmetic and control unit 30, the read control unit 12 reads data management information only from the second TAG memory 32.
Then, when the read operation based on the data read request by the data read command unit 8 is not being performed, the read control unit 12 sends the management information to the read data path selecting unit 14, and the high-speed small-capacity cache 1 or the low-speed large Data is read from one of the capacity caches 2 via the read data path selector 14.

The read controller 12 reads data from the main storage device 4 via the system bus 3 as necessary. The data written by the writing unit 9 is data read from the main storage device 4 by the read control unit 12.

In this embodiment, the data read command unit 8, the write control unit 10, and the read control unit 12 are mounted on the arithmetic control unit 13. Also,
The read data path selector 14 and the write data path selector 14 are mounted on the data path selector 14.

(1-3) Operations of the cache memory control device (data write operation, data read operation) will be described below.

(1-3-1) Data Write Operation The read control unit 12 receives the first data from the first TAG memory 31 and the second
It accesses the memory 32 and checks whether there is management information of the data A. As a result, when the management information of the data A does not exist, the read control unit 12 reads the data A from the main storage device 4 and sends the data A to the write control unit 10. The write controller 10 writes the data A to the high-speed small-capacity cache 1 via the write data path selector 14.

Further, the write control unit 10 sends the management information of the data A to the first TAG memory 31 and the second TAG memory 32 for updating.

When the writing unit 9 writes the data in the low-speed large-capacity cache 2, the management information of the data is sent to the second TAG memory 32 to update the management information of the data.

(1-3-2) Data Read Operation (1) The data read operation when a data read request is received by the data read command unit 8 will be described below.

The read control unit 12 accesses both the first TAG memory 31 and the second TAG memory 32 and checks whether there is data management information. As a result, if the data management information exists, the data management information is read, and both the high-speed small-capacity cache 1 and the low-speed large-capacity cache 2 are accessed based on the address of the management information.

Then, the read control unit 12 sends management information (information indicating that the data to be read is in the high-speed small-capacity cache 1) to the data path selection unit 14. As a result, the read control unit 12 is connected to the data output unit of the high-speed small-capacity cache 1 via the data path selection unit 14. Then, the read control unit 12 reads data from the high-speed small-capacity cache 1 via the data path selection unit 14.

(2) The data read operation when a data read request is received by the arithmetic and control unit 30 will be described below.

The read control unit 12 accesses only the second TAG memory 32 and checks whether or not there is management information of the data. As a result, when the data management information exists, the data management information is read.

When the read control unit 12 is not performing a read operation to the cache memory based on the read command unit 8, the read control unit 12 stores the high-speed small-capacity cache 1 and the low-speed large-capacity cache based on the address of the management information. Access both of them. That is, when a read operation to the cache memory based on the above-described read command unit 8 is performed, the operation is performed with priority, and after the read operation is completed, the read operation to the cache memory by the arithmetic and control unit 30 is performed. I do. For example, when the read operation to the cache memory based on the read command unit 8 is continuously performed, the arithmetic control unit 30 does not perform the read operation to the cache memory.

When the read operation to the cache memory based on the read command section 8 is not performed,
The read control unit 12 sends management information (information indicating that the data to be read is in the high-speed small-capacity cache) to the data path selection unit 14. As a result, the reading unit 11
Are connected to the data output unit of the high-speed small-capacity cache 1 via the data path selection unit 14. Then, the read control unit 12 reads data from the high-speed small-capacity cache 1 via the data path selection unit 14.

The arithmetic control unit 13 can control the I / O controller 5 to store data from the peripheral device in the main storage device 4.

In the present embodiment, the reading unit 11
Accesses the first TAG memory 31 and the second TAG memory 32 when a data read request is received by the data read command unit 8, but when the data read request is received by the arithmetic and control unit 30, the second TAG memory 32
Access only to. Further, even when receiving a data read request from the arithmetic and control unit 30, the read unit 11 gives priority to the read operation when performing a read operation based on the data read request from the data read command unit 8.

Therefore, even if another arithmetic and control unit 30 is connected to the system bus 3 and the arithmetic and control unit 30 can access the cache memory, the data in the high-speed small-capacity cache 1 is When a read request is continuously received by the read command unit 8, the operation of reading data from the high-speed small-capacity cache 1 at high speed is continuously performed without interruption.

Embodiment 2 FIG. 2 is a diagram showing a configuration of a cache memory control system according to the second embodiment. The cache memory control system according to the second embodiment differs from the cache memory control system according to the seventh embodiment in the following points.

(2-1) Configuration of Cache Memory Control System The system bus 3 according to the second embodiment is connected to a system bus use right granting unit 33 (bus arbitration unit) that gives a right to use the system bus. .

The cache memory control device according to the second embodiment is different from the cache memory control device according to the first embodiment in the configuration of the first TAG memory 31 and the second TAG memory 32 and the function of the read unit 11. Are different.

(1) First TAG Memory and Second TAG Memory The first TAG memory 31 is a high-speed memory,
The G memory 32 is a low-speed memory.

(2) Read Unit The read control unit 12 accesses the first TAG memory 31 and the second TAG memory 32 in response to a data read request from the data read command unit 8, and sends the management information transmitted from the first TAG memory 31. Therefore, when it is determined that the data does not exist in the high-speed small-capacity cache 1, a request signal for a system bus use right is sent to the system bus use right granting unit 33.

Further, the read control unit 12 controls the second TAG
If it is determined from the management information sent from the memory 32 that the data does not exist in both the high-speed small-capacity cache 1 and the low-speed large-capacity cache 2, the system bus usage right granted by the system bus usage right granting unit 33 is given. Access the main storage device 4 based on the

(2-2) Operation of Cache Memory Control Device The operation of the cache memory control device according to the present embodiment will be described.

The read control unit 12 responds to the data read request from the data read command unit 8 by the first TA
The G memory 31 and the second TAG memory 32 are accessed. At this time, since the first TAG memory 31 is a high-speed memory, the first TAG memory 31 returns an access result to the read control unit 12 earlier.

As a result, if the read control unit 12 determines that the read request data does not exist in the high-speed small-capacity cache 1, it sends a system bus use right request signal to the system bus use right granting unit 33 via the system bus 3. send.

Subsequently, the access result is sent to the read control unit 12 from the second TAG memory 32 which is a low-speed memory. When the read control unit 12 determines that the read request data exists in the low-speed large-capacity cache 2 from the access result, the read control unit 12 informs the system bus use right granting unit 33 that the system bus 3 is not used. Is sent.

On the other hand, if the read control unit 12 determines that the read request data does not exist in both the high-speed large-capacity cache 1 and the low-speed large-capacity cache 2 from the access result, the read control unit 12 uses the system bus. It waits until the right granting unit 33 sends the right to use the system bus.

Then, the read control unit 12 accesses the main storage device 4 based on the system bus usage right granted by the system bus usage right granting unit 33 and reads the data.

In the present embodiment, the first TAG memory 31 and the second TAG memory 32 are a high-speed memory and a low-speed memory, respectively. For this reason, the reading unit 11
Indicates that the first TAG memory 3
When both the first and second TAG memories 32 are accessed,
An access result can be obtained from the first TAG memory 31 quickly. If the read request data does not exist in the high-speed small-capacity cache 1, the reading unit 11 issues a system bus use right request to the system bus use right granting unit 33 in advance.

When the access result from the second TAG memory 32 is returned to the reading unit 11 and there is no data in either the high-speed small-capacity cache 1 or the low-speed large-capacity cache 2, the system bus use right request is already issued. , The right to use the system bus can be obtained quickly. As a result, when the read request data does not exist in both the high-speed and small-capacity cache 1 and the low-speed and large-capacity cache 2, the read unit 11 can quickly access the main storage device 4 based on the right to use the system bus. it can. Therefore, in the present embodiment, it is possible to reduce a penalty when a miss occurs in two cache memories.

Embodiment 3 FIG. (3-1) Configuration of Cache Memory Control System FIG. 3 is a diagram showing a configuration of a cache memory control system according to the third embodiment. The cache memory control system according to the third embodiment differs from the cache memory control system according to the second embodiment in the following points.

That is, the cache memory control device according to the third embodiment reads out the data read from the low-speed small-capacity cache 2 and the latest read-out of the data stored in the high-speed large-capacity cache 1 by the reading unit 11. The infrequently exchanged data is exchanged with each other, and the management information of the moved data is stored in the first TAG memory 31 and the second T
Cache memory control unit 3 for updating AG memory 32
5

Further, the first TAG memory 31 and the second TA
The G memory 32 stores the latest reading frequency of each data by the reading unit 11.

(3-2) Operation of Cache Memory Control Device The operation of the cache memory control device according to the present embodiment will be described below.

When data is read from the low-speed large-capacity cache 2 by the reading unit 11, the cache memory control unit 35 moves the read data from the low-speed large-capacity cache 2 to the first buffer 36. Further, the cache memory control unit 35 accesses the first TAG memory 31 or the second TAG memory 32 and reads out the read unit 11 out of the data stored in the high-speed small-capacity cache 1.
And examines the data which has recently been read infrequently by the high-speed small-capacity cache 1 to the second buffer 37.
Move to

Then, the cache memory control unit 35
The data stored in the first buffer 36 is moved to the address where the data in the high-speed small-capacity cache 1 is stored, and the data stored in the second buffer 37 is stored in the low-speed large-capacity cache 2. Move to address. Then, the cache memory control unit 35
Sends management information of new data (data newly stored in the high-speed small-capacity cache 1) to the first TAG memory 31 and the second TAG memory 32, and also stores new data (data newly stored in the low-speed large-capacity cache 2). Data)
Is transmitted to the second TAG memory 32. Then, in the first TAG memory 31 and the second TAG memory 32, the management information of the moved data is updated.

At this time, the first TAG memory 31 and the second TA
Since the operation speed is different from that of the G memory 32, the first TAG memory 31 and the second T
The access to the AG memory 32 is performed by the first TAG memory 31.
And after the update operation in the second TAG memory 32 is completed. Before the update operation of the first TAG memory 31 and the second TAG memory 32 is completed, the read controller 1
When it is desired to start access to the high-speed small-capacity cache 1 by 2, access to the address whose data has been replaced is suppressed.

In this embodiment, when the data read by the reading unit 11 is in the low-speed large-capacity cache 2, the cache memory control unit 35 Of the data, the data that is recently read by the reading unit 11 at a low frequency is interchanged. As a result, when the data read from the low-speed and large-capacity cache 2 is read again by the reading unit 11, the data is read from the high-speed and small-capacity cache 1, and the speed of data reading can be increased.

In this embodiment, the first TA
The G memory 31 can be included in the arithmetic and control unit 13. FIG. 4 shows the configuration of the cache memory control system in this case. Thereby, the read control unit 12
Can access the first TAG memory 31 more quickly.

Embodiment 4 Generally, an information processing device such as a computer uses a memory device and a memory device control device that controls the memory device. Conventionally, one memory device control device has been incorporated in one chip (hereinafter, referred to as a memory device control chip).

FIG. 5 is a diagram showing a configuration of a memory device control system including a conventional memory device control chip.

(4-1) Configuration of Conventional Memory Device Control System The conventional memory device control system includes a memory device 60, a CPU 61, and a memory device controller 6 that controls the memory device 60 based on a command from the CPU 61.
2 including a memory device control chip 63 including

The configuration of the memory device control chip 63 will be described below.

A CP for inputting a signal from the CPU 61 is provided at one end of the memory device control chip 63.
A U input terminal 64 is provided. The other end of the memory device control chip 63 has a memory device output terminal 65 for outputting a signal to the memory device 60 and a memory device output terminal 65 for inputting a signal output from the memory device 60. And an input terminal 66.

The memory device control chip 63 includes a memory device control device 62. The input unit on one side of the memory device control device 62 has a CPU
Input terminal 64. The output unit on the other side of the memory device control device is connected to a memory device output terminal 65. The other input section of the memory device control device 62 is connected to a memory device input terminal 66.

The CPU input terminal 64 of the memory device control chip 63 is connected to the CPU 61 and the memory device output terminal 6 of the memory device control chip 63 is connected.
5 is connected to the input section of the memory device 60, and the memory device input terminal 66 of the memory device control chip 63
Is connected to the output unit of the memory device 60.

The operation of the memory device control system thus configured will be described below.

(4-2) Operation of the Conventional Memory Device Control System The CPU 61 sends a signal to instruct to read data from a predetermined address of the memory device 60 to the CPU input terminal 64 of the memory device control chip 63. The above signal is sent to an input section on one side of the memory device controller 62. The memory device control device 62 sends the predetermined address from the output unit on the other side to the input unit of the memory device 60 via the output terminal 65 for the memory device. As a result, the memory device 60 sends the data stored at the predetermined address from the output unit to the memory device input terminal 66 of the memory device control chip 63. The above data is input from the memory device input terminal 66 to the other input section of the memory device control device 62.

However, the conventional memory device control system has the following problems. That is, conventionally, one memory device control chip includes:
Only one memory device controller could be included. For this reason, when a plurality of memory device control devices are required, it is necessary to manufacture a plurality of memory device control chips, resulting in a problem that the manufacturing cost is increased. In addition, it is necessary to manage each manufactured memory device control chip, and the management cost has increased.

Therefore, an object of the present embodiment is to provide a memory device control system capable of including a plurality of memory device control devices in one memory device control chip.

Generally, since a memory device controller has a small number of gates, a plurality of memory device controllers are
It is possible to include them in one memory device control chip. However, when two memory device control devices are directly included in one chip, the number of terminals provided on the memory device control chip is smaller than the number of terminals provided on the memory device control chip including one memory device control device.
About twice as much. Therefore, the memory device control chip becomes large, and the chip manufacturing cost increases.

In this embodiment, a system in which a plurality of memory device control devices can be included in one memory device control chip and the size of the chip can be reduced will be described below.

FIG. 6 is a diagram showing a configuration of a memory device control system according to the fourth embodiment. For comparison, a configuration of a conventional memory device control system (a memory device A control system for controlling the memory device A and a memory device B control system for controlling the memory device B) is also shown. In FIG. 6, the CPU of the conventional memory device control system is omitted.

(4-3) Configuration of Memory Device Control System of Embodiment 4 The memory device control system comprises a memory device A 60a and a memory device B 60
b, a CPU 61, and a memory device control chip 68 that controls the memory device A 60a and the memory device B 60b based on a command from the CPU 61.

(4-3-1) Configuration of Memory Device Control Chip First, each terminal formed on the memory device control chip 68 will be described.

A CP for inputting a signal from the CPU 61 is provided at one end of the memory device control chip 68.
A U input terminal 70 is provided. The other end of the memory device control chip 68 has a memory device output terminal 7 for outputting a signal to the memory device.
1 and a memory device input terminal 72 for inputting a signal output from the memory device.

The memory device control chip includes a memory device A control device 62a for controlling the memory device A 60a and a memory device B control device 62b for controlling the memory device B 60b.

The input unit on one side of the memory device A control unit 62a and the input unit on one side of the memory device B control unit 62b are both connected to the CPU input terminal 70. Note that some terminals of the CPU input terminal 70 are connected to a first selector unit described later.

In the memory device control chip 68, one of the output unit on the other side of the memory device A control unit 62a and the output unit on the other side of the memory device B control unit 62b is provided. Is connected to the memory device output terminal 71.

A switching signal (a signal indicating which memory device control unit is to be connected to the memory device output terminal 71) is sent from the CPU input terminal 70 to the first selector unit 73. Then, based on the switching signal, the first selector unit 73 outputs one of the output unit on the other side of the memory device A control device 62a and the output unit on the other side of the memory device B control device 62b. To the output terminal 71 for the memory device.
To connect.

The other input portion of the memory device A control device 62a and the other input portion of the memory device B control device 62b are connected to the memory device input terminal 72.

(4-3-2) Description of System Configuration Including Memory Device Control Chip The CPU input terminal 70 of the memory device control chip 68 is connected to the CPU 61. The memory device output terminal 71 of the memory device control chip 68 is connected to the input of the memory device A 60a and the memory device B6.
0b.

The memory device control system includes an output section of the memory device A 60a and a memory device B6.
0b, and a second selector section 7 for connecting one of the output sections to the memory device input terminal 72.
4 Note that the second selector unit 74 includes the CPU 6
A switching signal (a signal indicating which memory device output unit is to be connected to the memory device input terminal 72) is transmitted from 1. Then, based on the switching signal, the second selector unit 74 connects one of the output unit of the memory device A 60a and the output unit of the memory device B 60b to the memory device input terminal 72.
To connect.

In the memory device control system thus configured, the operation of each memory device control device reading data from the corresponding memory device will be described below.

(4-4) Memory device A control device 62
a Reads data from the memory device A 60a (1) Operations to read data from the memory device A 60a The CPU 61 sends a signal instructing the CPU 61 to read data from a predetermined address of the memory device A 60a to the CPU input terminal 70 of the memory device control chip 68. Send to The above signal is sent to one input of the memory device A control device 62a and one input of the memory device B control device 62b. Further, the CPU 61 sends a switching signal (the memory device A control device 62) to the first selector unit 73.
a) indicating whether or not to connect the output unit a to the memory device output terminal 71, and to the second selector unit 74 to determine whether to switch the output unit of the memory device A 60a to the memory device input terminal 72. Signal)
Send.

The memory device A control device 62a and the memory device B control device 62b send the predetermined address to the first selector unit 73 from the other output unit. The memory device A control device 62a outputs an address in a manner suitable for the memory device A 60a to receive a predetermined address, and the memory device B control device 62b
Outputs an address in a manner suitable for the memory device B60b to receive the predetermined address.

In the case of this operation, it is necessary to send a predetermined address from the memory device A control device 62a to the memory device A 60a.
A predetermined address output from the memory device A control device 62a is sent to the memory device A 60a via the memory device output terminal 71 based on the switching signal from the memory device A 60a.

As a result, the memory device A 60 a sends the data stored at the predetermined address from the output section to the second selector section 74. Further, since the predetermined address is also sent to the memory device B 60b,
Data is also sent to the second selector unit 74 from 60b.
In the case of this operation, it is necessary to send data from the memory device A 60a to the memory device A control device 62a.
The second selector 74 sends the data of the memory device A 60 a to the memory device input terminal 72 based on the switching signal from the CPU 61. Then, data is sent from the memory device input terminal 72 to the other input unit of the memory device A control device 62a.

(2) Operation of Reading Data from Memory Device B The CPU 61 sends a signal to instruct to read data from a predetermined address of the memory device B 60 b to the CPU input terminal 70 of the memory device control chip 68. The above signal is sent to one input of the memory device A control device 62a and one input of the memory device B control device 62b. Further, the CPU 61 supplies a switching signal (the memory device B control device 6) to the first selector section 73.
2b) to send the output section 2b to the output terminal 71 for the memory device.
(A signal indicating whether to connect the output unit of the memory device B 60b to the memory device input terminal 72).

The memory device A control device 62a and the memory device B control device 62b send the predetermined address to the first selector unit 73 from the output unit on the other side.

In the case of this operation, it is necessary to send a predetermined address from the memory device B control device 62b to the memory device B 60b.
A predetermined address output from the memory device B control device 62b is sent to the memory device B 60b via the memory device output terminal 71 based on the switching signal from the memory device B 60b. The predetermined address is the memory device A60a
Also sent to the input section.

As a result, both the memory device A 60a and the memory device B 60b send the data stored at the predetermined address from the output section thereof to the second selector section 74. In the case of this operation, since it is necessary to send data from the memory device B 60b to the memory device B control device 62b, the second selector unit 74 converts the data of the memory device B 60b into a memory device input signal based on the switching signal from the CPU 61. Send to terminal 72. Then, from the memory device input terminal 72 to the memory device B control device 62
The data is sent to the input section on the other side of b.

In the memory device control chip 68, based on the I / O signal from the CPU 61, the input unit on the other side of the memory device control device is switched to the output unit, and the data output unit of the memory device is connected to the data input unit. Can be switched to department.

When performing a data write operation, the input unit on the other side of the memory device control device becomes a data output unit based on the I / O signal from the CPU 61, and the data output unit of the memory device becomes Becomes a data input unit. Then, based on the switching signal from the CPU 61, the second selector unit 74 connects the data output unit of the memory device A control device 62a and the memory device control device 62b
One of the data output units is connected to the data input unit of the memory device. As a result, data can be written from the data output unit of the memory device control device to the data input unit of the memory device.

In the present embodiment, a memory device control chip capable of controlling two memory devices has been described. However, it is possible to set so as to control one of the memory devices. For this setting, the first selector unit 73 and the second selector unit 74 are configured when the system is started. That is, the first selector unit 73 is set such that the output unit of any of the memory device control devices is always connected to the output terminal 71 for the memory device. In addition, the second unit is configured such that the output unit of any memory device is always connected to the memory device input terminal 72.
The selector 74 is set. By setting each selector unit in this manner, the memory device control chip can be set to control one of the memory devices.

In this embodiment, three or more memory device controllers can be included in one chip. It is also possible to configure a memory device control chip for controlling three or more memory devices. In this case, the first selector unit 73 and the second selector
The selector unit 74 includes one of three or more pieces of input data.
It is necessary to use a selector that can output two data.

In this embodiment, since a plurality of memory device controllers can be included in one chip, when a plurality of memory device controllers are used, the manufacturing cost and management cost can be reduced. In the present embodiment, the number of terminals of the memory control chip including the plurality of memory device control devices can be substantially equal to the number of terminals of the memory device control chip including one memory device control device. For this reason, even if a plurality of memory device control devices are included in one chip, the size of the chip can be suppressed to a conventional level.

Embodiment 5 FIG. The memory device control device 62 has a function of performing control unique to the memory device and a function of performing control independent of the memory device. When the functions of the memory device control device 62 are implemented as hardware, the memory device control device is divided into the following units. That is, as shown in FIG. 7A, the memory device control device 62 performs the first control for performing the control unique to the memory device.
It is divided into a memory device control unique unit 82 and a second memory device control unique unit 85, and a memory device control common unit 84 that performs control independent of a memory device.

In this embodiment, it is necessary to provide a plurality of first memory device control unique units and a plurality of second memory device control unique units in a memory device control chip for controlling a plurality of memory devices. One device control common unit may be provided. Therefore, when a plurality of memory device control devices are included in one chip, the amount of hardware related to the memory device control common unit can be reduced.

The memory device control system according to the present embodiment differs from the memory device control system according to the fourth embodiment in that the configuration of the memory device control chip is different. Is the same as

(5-1) Configuration of Memory Device Control Chip FIG. 7B is a diagram showing a configuration of a memory device control chip according to the present embodiment.

The memory device control chip 80 according to the present embodiment includes the terminals (CPU input terminal 70, memory device output terminal 71, memory device input terminal 72) of the memory device control chip according to the fourth embodiment. Is provided.

(Regarding Each Unit in Memory Device Control Chip) The memory device control chip 80 is connected to the CPU input terminal 70 and decodes a command signal from the CPU 61 (not shown in FIG. 7B). The first memory device A that sends the decryption result to the memory device control common unit
A control unique unit 82a and a first memory device B control unique unit 82b are included.

Here, the first memory device control specific unit 8
2a and 82b each decode a command signal unique to the memory device to be controlled, so that the configuration of each first memory device control unique unit is a configuration unique to the memory device to be controlled.

The memory device control chip 80 has the first
Of the output unit of the memory device A control unique unit 82a and the output unit of the first memory device B control unique unit 82b, CP
Based on a switching signal from U61, a third selector unit 83 for connecting one of the output units to a memory device control common unit to be described later, and an output (decoding result) from the third selector unit 83 to a second to be described later. A memory device control common unit 84 for sending to the memory device A control unique unit and the second memory device B control unique unit.

Note that some terminals of the CPU input terminal 70 are connected to the third selector unit 83, and a switching signal is sent from the CPU 61 to the third selector unit 83 via the CPU input terminal 70. . Also, the memory device control common unit 84 can temporarily hold the decryption result, if necessary, when a second memory device control specific unit described later is operating.

The memory device control chip 80 executes a command from the CPU 61 based on the decoding result sent from the memory device control common unit 84 (for example, transmits an address). A second memory device B control unique part 85b and a fourth selector for connecting one of the outputs to the memory device output terminal 71 based on a switching signal from the CPU 61, based on the output of the second memory device control unique part Part 8
And 6.

Note that some terminals of the CPU input terminal 72 are connected to the fourth selector unit 86, and a switching signal from the CPU 61 is transmitted to the fourth selector unit 86 via the CPU input terminal 72. Can be

The second memory device A control unique unit 8
The input part on the other side of 5a and the input part on the other side of the second memory device B control unique part 85b are connected to the memory device input terminal 72.

(5-2) Operation of Memory Device Control Chip The operation of the memory device control chip 80 in the present embodiment will be described in the case where data is read from the memory device A.

The CPU 61 sends a command signal instructing to read data from the memory device A 60a to the CPU input terminal 70 of the memory device control chip 80. The command signal is transmitted to the first memory device A control unique unit 82a.
Of the first memory device B control unique unit 82b. Each first memory device control specific section decodes a command from the CPU 61,
The decoding result is sent to the third selector unit 83. In the case of this operation,
Since the decoding result of the first memory device A control unique unit 82a is required, the third selector unit 83 outputs a switching signal from the CPU 61 (a signal that the output unit of the first memory device A control unique unit is connected to the memory device control common unit). Based on the first memory device A control unique unit 82
The decoding result output from a is sent to the memory device control common unit 84.

The decryption result is sent from the memory device control common unit 84 to the second memory device A control unique unit 85a and the second memory device B control unique unit 85b. Second
The memory device A control unique unit 85a and the second memory device B control unique unit 85b transmit addresses based on the decryption result. Then, the address is sent to the fourth selector unit 86. In this operation, since it is necessary to send an address from the second memory device A control unique unit 85a to the memory device A 60a, the fourth selector unit 86
Outputs the address output from the second memory device A control unique unit 85a to the memory device output terminal 71 based on the switching signal from the CPU 61. This address is sent to the inputs of the memory device A 60a and the memory device B 60b.

As a result, both the memory device A 60a and the memory device B 60b send the data stored at the predetermined address from the output section thereof to the second selector section 74. The second selector 74 sends the data of the memory device A 60 a to the memory device input terminal 72 based on the switching signal from the CPU 61. Then, data is sent from the memory device input terminal 72 to the other input portion of the second memory device A control unique portion 85a.

In the present embodiment, the memory device control device included in the memory device control chip 80 is divided into a plurality (a first memory device control specific portion, a second memory device control specific portion, a memory device control common portion). ). Then, only one memory device control common unit 84 is included in the memory device control chip of the present embodiment. Therefore, when a plurality of memory device control devices are included in one chip, the amount of hardware related to the memory device control common unit can be reduced.

[0122]

According to the first aspect of the present invention, the writing means reads the data (read from the main storage device) such that the storage contents of the first cache memory and the second cache memory are different. Data) is written to either the first cache memory or the second cache memory. For this reason, the storage contents of the second cache memory are all different from the storage contents of the first cache memory, so that the capacity of the second cache memory can be effectively utilized, and when the second cache memory is accessed. Hit rate can be improved.

Further, the first management information storage means stores management information of data stored in the first cache memory.
The second management information storage means stores management information of data stored in the first cache memory and management information of data stored in the second cache memory. When receiving the data read request, the read unit can read the data management information, and can know the address and the cache memory of the data of the read request. For this reason, the reading means, based on the management information,
Data can be quickly read from the cache memory where the data exists.

When the read means receives a data read request from the data read command means, it accesses the first management information storage means and the second management information storage means, but receives the data read request from the arithmetic and control unit. In this case, only the second management information storage unit is accessed. Further, the reading means gives priority to the reading operation, even when receiving the data reading request from the arithmetic and control unit, when the reading operation is being performed based on the data reading request by the data reading instruction means.

Therefore, even if the arithmetic and control unit is connected to the system bus and this arithmetic and control unit can access the cache memory, the data in the first cache memory is continuously read by the data read command means. , The operation of reading data from the first cache memory at high speed is continuously performed without interruption.

According to the second aspect of the present invention, the first management information storage means and the second management information storage means each
High-speed memory and low-speed memory. For this reason, when the readout unit accesses both the first management information storage unit and the second management information storage unit for the read request data, the readout unit can quickly obtain an access result from the first management information storage unit. If the read request data does not exist in the first cache memory, the read unit issues a system bus use right request to the system bus use right grant unit in advance.

When the access result from the second management information storage means is returned to the reading means, and there is no data in either the first cache memory or the second cache memory, a system bus use right request is already issued. Therefore, the right to use the system bus can be obtained quickly. As a result, when the read request data does not exist in both the first cache memory and the second cache memory, the read unit can quickly access the main storage device based on the right to use the system bus. Therefore, it is possible to reduce a penalty when a miss occurs in two cache memories.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a cache memory control system according to a first embodiment;

FIG. 2 is a diagram illustrating a configuration of a cache memory control system according to a second embodiment;

FIG. 3 is a diagram illustrating a configuration of a cache memory control system according to a third embodiment;

FIG. 4 is a diagram illustrating another configuration of the cache memory control system according to the third embodiment;

FIG. 5 is a diagram showing a configuration of a conventional memory device control system.

FIG. 6 is a diagram illustrating a configuration of a memory device control system according to a fourth embodiment;

FIG. 7 is a diagram illustrating a memory device control device according to a fifth embodiment.

[Explanation of symbols]

1 High-speed small-capacity cache, 2 Low-speed large-capacity cache, 3 system bus, 4 main memory, 5 I / O controller, 8 data read command section, 9 write section, 10 write control section, 11 read section, 12
Read control unit, 13 operation control unit, 14 data path selection unit (read data path selection unit and write data path selection unit), 15, 35 cache memory control unit, 30 operation control unit, 31 first TAG memory, 32
Second TAG memory, 33 system bus use right granting unit, 36 first buffer, 37 second buffer, 60,
60a, 60b memory device, 61 CPU, 6
2, 62a, 62b memory device control device, 63,
80 memory device control chip, 64, 64a, 64
b, 65, 65a, 65b, 71 output terminal for memory device, 66, 66a, 66b, 72 input terminal for memory device, 70 CPU input terminal, 73 first selector section, 74 second selector section, 82, 82a, 82b
1st memory device control specific section, 83 3rd selector section, 84 memory device control common section, 85, 85a,
85b second memory device control specific part, 86 fourth selector part.

Continuation of the front page (56) References JP-A-4-288645 (JP, A) JP-A-61-241853 (JP, A) JP-A-53-33023 (JP, A) JP-A-62-260248 (JP, A) JP-A-6-250926 (JP, A) JP-A-3-63852 (JP, A) JP-A-6-168119 (JP, A) JP-A-3-225695 (JP, A) 5-73415 (JP, A) JP-A-4-319746 (JP, A) JP-A-61-15247 (JP, A) JP-A-4-288644 (JP, A) JP-A-3-42745 (JP, A A) JP-A-52-35533 (JP, A) JP-A-1-166147 (JP, A) Motorola Inc. Author, "MC68020 Users Manual", 6th edition, CQ Publishing Co., Ltd., May 30, 1988, p. 89-91 (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 12/08 G06F 12/02

Claims (2)

(57) [Claims] 1. A cache memory control device for controlling a high-speed small-capacity first cache memory and a low-speed large-capacity second cache memory, wherein a plurality of data stored in the first cache memory are individually The first cache for data
First management information storage means for storing an address on the memory and management information indicating that the address is in the first cache memory; a plurality of data stored in the first cache memory; and a plurality of data stored in the second cache memory respect, a plurality of data is, in its data for individual data
A second management information storage means for storing management information indicating whether data is in the address and any of the cache memory in the cache memory is stored, the memory storage contents of said first cache memory of the second cache memory The data is written to either the first cache memory or the second cache memory so that the contents are different from each other. When the data is written to the first cache memory, the management information of the data is written to the first cache memory or the second cache memory. Writing means for writing to the second management information storage means and the first management information storage means, and when the data is written to the second cache memory, writing means for writing the management information of the data to the second management information storage means; Data read command means for requesting data read, and the data read command means When receiving the chromatography data read request, the first management information storage means or said second
Reading means for reading the management information of the data from at least one of the management information storage means, and reading the data from either the first cache memory or the second cache memory based on the management information. The readout means is connected to an arithmetic and control unit via a system bus, and in response to a data readout request by the arithmetic and control unit, the data management information is transmitted only from the second management information storage means. A cache memory for reading the data from one of the first cache memory and the second cache memory when a read operation is not being performed based on a data read request by the data read command unit; Control device. 2. The first management information storage means is a high-speed operation memory, the second management information storage means is a low-speed operation memory, and the system bus has a main storage device and a system bus. And a system bus use right granting means for granting a use right of the first and second management information. The readout means responds to a data read request by the data read command means with the first management information storage means and the second management information. Accessing the storage means, from the management information sent from the first management information storage means,
When it is determined that the data does not exist in the first cache memory, a request signal for a system bus use right is sent to the system bus use right granting means, and ,
If it is determined that the data does not exist in both the first cache memory and the second cache memory, access to the main storage device is performed based on the system bus usage right granted by the system bus usage right granting means. 2. The cache memory control device according to claim 1, wherein: