JP2913737B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Summary] The present invention relates to a method for manufacturing a thin film transistor matrix used for driving a liquid crystal display device, electroluminescence, etc., by eliminating a gap between a protective film and a source / drain electrode without contaminating the surface of an active semiconductor layer and improving a thin film transistor characteristic. For the purpose of stabilization, a gate electrode, a gate insulating film, and an active semiconductor layer are laminated in this order on a transparent insulating substrate, and a protective film is disposed immediately above the gate electrode on the active semiconductor layer, with the protective film interposed therebetween. In producing a thin film transistor having a source electrode and a drain electrode opposed to each other on both sides thereof, a gate electrode is formed on a transparent insulating substrate, and then a lower film including a gate insulating film, an operating semiconductor layer, and an insulating film is formed. Laminating a multilayer film with an upper film that can be selectively etched with respect to the lower film,
A resist film self-aligned with the gate electrode was formed on the multilayer film, and the exposed portion of the upper film of the multilayer film was selectively removed using the resist film as a mask, and then the resist film was removed. Thereafter, the exposed portion of the lower film is removed to define a protective film, and then, a source electrode and a drain electrode whose edges are overlapped on the edge of the protective film are formed. [Industrial Application Field] The present invention relates to a thin film transistor matrix used for driving a liquid crystal display device, electroluminescence, and the like, and a method for manufacturing the same. The above thin film transistor matrix is composed of several hundred thousand TFTs.
Must be manufactured without defects. In addition, the characteristics need to be stable even after long-time use, and in order to obtain a clear image, various characteristics such as the on / off characteristics of the thin film transistor need to be good. [Prior Art] FIG. 5 shows a method of manufacturing a self-aligned thin film transistor using a conventional lift-off method. In the figure, G is a gate electrode, 1 is a transparent insulating substrate such as a glass substrate, 2 is a gate insulating film such as a SiN film, 3 is a working semiconductor layer such as an a-Si layer, and 4 is a protective film such as SiO.
₂ film, 5 is an a-Si layer as an adhesion layer, 6 is a contact layer, for example, an n ⁺ a-Si layer, 7 is a source and drain electrode metal film, for example, a Ti film, D is a drain electrode, and S is a source electrode. It is.

[See FIG. 5 (a)] After a gate electrode G is formed on the transparent insulating substrate 1, P
A protective film 4 composed of a SiN film as a gate insulating film 2, an a-Si layer as an operating semiconductor layer 3, and a SiO ₂ film, a-Si by a CVD method;
An adhesion layer 5 composed of layers is continuously formed. Next, a positive photoresist is applied thereon.
Exposure is performed from the back surface of the transparent insulating substrate 1 using the gate electrode G as a mask to form a resist film 8 self-aligned with the gate electrode G.

[See Fig. (B)]

The resist film 8 adhesion layer 5 as a mask to remove the exposed portion of the protective film 4, after which, as a contact layer 6 n ⁺ a
-Si, a Ti film as the electrode metal film 7 is continuously formed.

[Refer to Fig. (C)]

Next, the resist film 8 is removed, and the electrode metal film 7 and the contact layer 6 adhered thereon are lifted off.

[Refer to Fig. (D)]

Next, a resist film (not shown) for covering the element portion is formed, and using this as a mask, Cl-based gas plasma etching is performed to perform element isolation. [Problem to be Solved by the Invention] In the thin film transistor manufactured in the above process, a gap 9 is generated between the protective film 4 and the adjacent source electrode S and drain electrode D during lift-off. When the gap 9 is thus generated, cracks are easily generated in the gate insulating film 2 due to a difference in thermal expansion coefficient, and as a result, a leak current occurs between a source and a gate, and a point defect occurs on display. In the manufacturing method using the lift-off method, the resist film 8 is formed when the contact layer 6 and the electrode metal film 7 are formed.
Exists. Therefore, in these film forming steps, the film forming temperature is
It must be below 120 ° C. Therefore, various characteristics of the thin film transistor are likely to be unstable. Therefore, if the step does not use the lift-off method, it is necessary to remove the resist film used as a mask after the etching for forming the protective film 4 is completed. In this resist stripping step, since the active semiconductor layer 3 is exposed after the removal of the protective film 4, there is a problem that the surface of the active semiconductor layer 3 is contaminated by the resist stripping solution, and the thin film transistor characteristics are degraded. As described above, in the conventional manufacturing method, there are some problems from the step of forming the protective film to the step of forming the source and drain electrodes. An object of the present invention is to eliminate the gap between the protective film and the source and drain electrodes without contaminating the surface of the active semiconductor layer, and to improve and stabilize the characteristics of the thin film transistor. [Means for Solving the Problems] A method for manufacturing a thin film transistor according to the present invention will be described with reference to FIG.

[See FIG. 1 (a)] After forming a gate electrode G on a transparent insulating substrate 1,
A gate insulating film 2 and an operating semiconductor layer 3 are formed so as to cover them, and a multilayer film 15 including a lower film 13 and an upper film 14 is further formed. In the multilayer film 15, for example, the lower film 13 is an insulating film, and the upper film 14 is an insulating film that can be selectively etched with respect to the lower film 13.

Referring to FIG. 1 (b), a resist film 8 self-aligned with the gate electrode G is formed on the upper film 14, and the exposed portion of the upper film 14 is removed by etching using this as a mask. In this step, since the upper layer film 14 is made of a material that can be selectively etched with respect to the lower layer film 13, the etching is performed on the upper film layer.
Stop when the 14 exposed parts are removed. Therefore, the control of the etching is easy.

Referring to FIG. 1C, the resist film 8 used as the mask is removed. In this step, since the operating semiconductor layer 3 is covered with the lower film 13, contamination by the resist stripping solution does not occur.

[See FIG. 1 (d)] The lower layer film 13 is etched, the exposed portion is removed, and the operating semiconductor layer 3 is exposed. In the present invention, no resist stripping solution is used in the step of exposing the working semiconductor layer, so that no contamination of the working semiconductor layer occurs. In the above etching step, the upper layer film 14 functions as a mask for etching instead of the resist film 8. Therefore,
The upper layer film 14 may also be etched to reduce its thickness or be completely removed. In addition, it does not matter if it is not etched. The figure shows an example in which the thickness of the upper layer film 14 is reduced. Thus, the protective film 4 is formed. The pattern of the protective film 4 thus formed has the same pattern as the resist film 8 which is self-aligned with the gate electrode G, and the precision of forming the protective film 4 is not different from the conventional one. Moreover, it is not necessary to form another resist film other than the resist film 8.

Next, a contact layer 6 and an electrode metal film 7 are formed, and element isolation is performed using a resist film (not shown) as a mask to complete a thin film transistor as shown in the figure. In the device isolation step, the source electrode S and the drain electrode D are separated from each other by defining the device region and removing the electrode metal film 7 and the contact layer 6 immediately above the gate electrode G. At this time, the ends of the source electrode S and the drain electrode D are overlapped on the end of the protective film 4. When forming the contact layer 6 and the electrode metal film 7, since the resist film does not exist, the film formation temperature is set to 120 ° C.
The above high temperature can be set. Therefore, the contact with the operating semiconductor layer 3 is improved, and the characteristics of the thin film transistor are improved. [Operation] As described above, according to the present invention, since the lift-off method is not used, no gap is formed between the protective film 4 and the source electrode S and the drain electrode D. Since the active semiconductor layer 3 is not exposed in the stripping step, contamination by the resist stripping liquid does not occur. Further, since the temperature can be raised to a temperature required in the step of forming the contact layer 6 and the electrode metal film 7, the source electrode S
In addition, the contact between the drain electrode D and the active semiconductor layer 3 is improved, and the characteristics of the thin film transistor are improved. [Examples] Hereinafter, the present invention will be described in detail with reference to examples. First, a first embodiment of the present invention will be described in the order of steps with reference to FIG. The present embodiment is an example in which the lower film 13 is a laminated film of the SiO ₂ film 11 and the a-Si film 12 as an etching stopper film.

[See FIG. 2 (a)] After forming the gate electrode G on the glass substrate 1, the P-CV
D (chemical vapor deposition) method, SiN film 2, a-Si layer 3, the above SiO
_{The two} films 11, the a-Si film 12, the SiO ₂ film 14 as the above film, and the a-Si film 5 as the adhesion layer of the resist are continuously formed. The thickness of each of the above-mentioned films is, for example, about 800 .ANG. Of Ti film for the gate electrode G, about 3000 .ANG. For the SiN film of the gate insulating film, about 300 .ANG. SiO ₂
The film 11 is about 500 °, and the a-Si film 12 as an etching stop film is about 20 mm.
Å, the upper layer SiO ₂ is about 900Å, and the a-Si film of the adhesion layer is about 30
Å

Referring to FIG. 2 (b), a resist film 8 self-aligned with the gate electrode G is formed on the a-Si film 5 as the above-mentioned adhesion layer. Etching is performed using the resist film 8 as a mask to remove exposed portions of the a-Si film 5 and the SiO ₂ film 14 as an upper layer film. In this etching step, a-Si film 12 as an etching stop layer, because it is not attacked in the etching solution of the SiO ₂ film 14, the etching of the SiO ₂ film 14 is a-Si film
Stop when 12 is exposed. Therefore, control of the etching amount or time is easy.

Referring to FIG. 2C, the resist film 8 used as the mask is removed. In this step, since the surface of the a-Si layer 3 of the operating semiconductor layer is not exposed, the a-Si layer 3 is not contaminated by the resist stripper.

[See FIG. 2 (d)] The a-Si film 12 and the SiO ₂ film 11 as the etching stopper films are removed. In this step, since the a-Si film 5 as the adhesion layer and the SiO ₂ film 14 as the upper layer remain immediately above the gate electrode, the a-Si film 12 and the SiO ₂ film as the etching stopper film remain. Acting as a mask for etching of the film 11, the a-Si film 12 and the SiO ₂ film 11 serving as an etching stopper film in this portion.
Is not removed. Since the a-Si film 5 of the mask layer is made of the same material as the etching stopper film, it is removed at the same time.
The SiO ₂ film 14 is etched simultaneously with the lower SiO ₂ film 11 to reduce its thickness. If the thickness of the SiO ₂ film 14 is thicker than that of the SiO ₂ film 11, a part of the SiO ₂ film 14 remains after the etching in this step as illustrated. The upper layer film 14 remaining in this step and the etching stopper film Si
The laminated film of the lower film 13 composed of the O ₂ film 12 and the SiO ₂ film 11 under the O ₂ film 12 forms the protective film 4 of the present embodiment.

[See FIG. 2 (e)] Next, an n ⁺ a-Si layer 6 as a contact layer is formed to a thickness of about 500 ° by a P-CVD method in an atmosphere of SiH ₄ and PH _{3 at} about 250 ° C. A Ti film 7 of a source / drain electrode metal is deposited at a substrate temperature of about 120 ° C. to a thickness of about 1000 °. In this embodiment, since the resist film 8 is removed before this step, the film formation temperature can be selected without considering the resist film.

[See FIG. 2 (f)] A resist film 10 for element isolation is formed. The pattern has an opening 25 smaller than the protective film 4 immediately above the protective film 4.

[See FIG. 2 (g)] Ti film 7, n ⁺ a-Si layer 6 and a
-The exposed portion of the Si layer 3 is removed, the source electrode S and the drain electrode D are formed, and element isolation is performed, thereby completing the illustrated thin film transistor. In the thin film transistor obtained in the above steps, the ends of the source electrode S and the drain electrode D overlap with the ends of the protective film 4, and there is no gap between them. Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is an example in which the lower film 13 and the upper film 14 are each composed of only one insulating film. However, the upper film 14 is a combination that can be selectively etched without affecting the lower film 13.

[See FIG. 3 (a)] After forming the gate electrode G on the glass substrate 1, the P-CV
By method D, SiN film (thickness approx. 3000 mm) 2, a-Si layer (thickness approx.
Å） 3, SiO ₂ film as lower film (thickness about 500 Å) 13, upper film
An SiN film 14 (thickness: about 1000) 14 'and an a-Si film (thickness: about 30) 5 as an adhesion layer are continuously formed.

[See Fig. (B)]

A resist film 8 self-aligned with the gate electrode G is formed.

[Refer to Fig. (C)]

Using the resist film 8 as a mask, the exposed portions of the a-Si film 5 of the adhesion layer and the SiN film 14 'of the upper layer are removed by etching with gas plasma. In this step, the SiO ₂ film 13 is not etched, and the SiN film 14 ′
Only those are selectively removed. That is, the lower layer SiO ₂ film 13
Also serves as an etching stop film for etching the upper layer film.

[Refer to Fig. (D)]

After removing the resist film 8, the exposed portion of the lower film 13 is etched with a buffered hydrofluoric acid aqueous solution. In this step, the SiN film 14 'functions as a mask, and the protective film 4 is formed by the SiN film 14' and the underlying SiO ₂ film 13. Subsequent steps may proceed in the same manner as in the first embodiment.

[Refer to Fig. (E)]

That is, the n ⁺ a-Si layer 6 is formed at about 250 ° C. by the P-CVD method.
Deposited by the SiH ₄ and PH ₃ atmosphere, a source, a Ti film 7 of the drain electrode material is deposited at a substrate temperature of about 120 ° C..

[Refer to Fig. (F)]

A resist film 10 for element isolation is formed. This pattern is a pattern having an opening 25 smaller than the protective film 4 immediately above the protective film 4.

[Refer to Fig. (G)]

Ti film 7, n ⁺ a-Si by Cl-based gas plasma etching
The exposed portions of the layer 6 and the a-Si layer 3 as an operating semiconductor layer are removed to form a source electrode S and a drain electrode D, and at the same time, perform element isolation to complete the illustrated thin film transistor. Also in this embodiment, when the resist film 8 is removed,
Since the operating semiconductor layer 3 is not exposed, it is not contaminated by the resist stripper, and since the resist film has already been removed when the contact layer 6 and the electrode metal film 7 are formed, the film is formed. The temperature can be selected without being restricted by the resist film, and further, since the end portions of the source / drain electrodes SD and the end portions of the protective film 4 are overlapped with each other, there is no gap between them. This is the same as in the first embodiment. FIG. 4 shows the contact characteristics with respect to the film forming temperature when Ti is used as the electrode metal film and the n ⁺ a-Si layer is used as the contact layer. The vertical axis represents the on-current [A], and the horizontal axis represents the voltage drop [V] between the operating semiconductor layer and the electrode. Curve A shows the conventional manufacturing method, that is, the Ti film is n ⁺ a at room temperature.
The curve B shows the contact characteristics when the film was formed at about 120 ° C., and the curve C shows the contact characteristics when the n ⁺ a-Si layer was formed at about 250 ° C. When the film was formed at ℃,
Curve D shows the contact characteristics when the Ti film was formed at about 120 ° C. and the n ⁺ a-Si layer was formed at about 250 ° C. As is apparent from the figure, it is understood that the higher the film formation temperature, the smaller the voltage drop. As described above, in the present invention, it is necessary that the upper layer film be a combination capable of being selectively etched with respect to the lower layer film, and that a film including at least the remaining lower layer film constitute a protective film. To this end, the lower film is formed by stacking a lower insulating film and an etching stopper film in an etching process of the upper film [first film].
Or a combination in which the upper layer film can be selectively etched with respect to the lower layer film [refer to the second embodiment].
Any of the configurations described above may be used. Also, various modifications such as a configuration using a semiconductor film as the etching stop film (see the first embodiment) or a configuration using an insulating film having a lower etch rate than the upper film for the etchant of the upper film. Can be implemented. [Effects of the Invention] As described above, according to the present invention, the lift-off method is not used, and the end portions of the source / drain electrodes and the protective film are overlapped. In addition, cracks in the gate insulating film and the like can be prevented.
Therefore, occurrence of point defects is prevented. In addition, even though the lift-off method is not used, the working semiconductor layer is not contaminated by the resist stripping solution. Further, since the film formation temperature of the contact layer, source and drain electrode material films can be increased, the on-current characteristics of the thin film transistor are improved and stabilized.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the structure of the present invention, FIG. 2 is an explanatory view of a first embodiment of the present invention, FIG. 3 is an explanatory view of a second embodiment of the present invention, and FIG. FIG. 5 is an explanatory view of a conventional problem. In the figure, 1 is a transparent insulating substrate (glass substrate), 2 is a gate insulating film (SiN film), 3 is an operating semiconductor layer (a-Si
Layer, 4 is a protective film, 5 is an adhesion layer (a-Si film), 6 is a contact layer (n ⁺ a-Si layer), 7 is an electrode metal film (Ti film), 8
Is a resist film, 9 is a gap, 10 is a resist film, 11 is a lower insulating film (SiO ₂ film), 12 is an etching stop film (a-Si film),
Reference numeral 13 denotes a lower film, 14 denotes an upper film, 15 denotes a multilayer film, 25 denotes an opening, G denotes a gate electrode, S denotes a source electrode, and D denotes a drain electrode.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomotaka Matsumoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-62-8570 (JP, A) JP-A-59-113666 (JP, A) JP-A-2-62051 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/786 H01L 21/336

Claims (5)

(57) [Claims] 1. A gate electrode (G), a gate insulating film (2) and a working semiconductor layer (3) on a transparent insulating substrate (1).
Are stacked in this order, and a protective film (4) is provided immediately above the gate electrode on the operating semiconductor layer, and a source electrode (S) and a drain electrode (D) are opposed to each other on both sides of the protective film. When manufacturing a thin film transistor, a gate electrode is formed on a transparent insulating substrate, and then a gate insulating film, a working semiconductor layer, and an underlying film including an insulating film (13)
And an upper layer film selectively etchable with respect to the lower layer film (14)
Forming a resist film (8) self-aligned with the gate electrode on the multilayer film, and selectively exposing the exposed portion of the upper film of the multilayer film using the resist film as a mask. After removing the resist film, the exposed portion of the underlayer film is removed to define a protective film. Then, a source electrode and a drain electrode whose ends are overlapped on the ends of the protective film Forming a thin film transistor. 2. The method according to claim 1, wherein the lower film (13) is a lower insulating film (11).
And an etching stop film (12) formed of a material having a lower etch rate with respect to an etchant used in the etching process of the upper layer film (14) and a material smaller than that of the upper layer film. 2. The method according to claim 1, wherein the upper layer film is selectively etched by stopping at a stop film. 3. The etching stop film (12) is a semiconductor film having a lower etch rate with respect to an etchant used in an etching process of the upper layer film (14) than the upper layer film. Method for manufacturing thin film transistor. 4. The etching stop film according to claim 2, wherein an etching rate of an etchant used in an etching process of said upper film is smaller than that of said upper film. Method for manufacturing thin film transistor. 5. An upper film (14) of the multilayer film is used as an insulating film, and an insulating film whose etch rate with respect to an etchant used in an etching process of the upper film is smaller than the upper film is used as a lower film (13). 2. The method for manufacturing a thin film transistor according to claim 1, wherein: