JP2882117B2 - Data playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus suitable for reproducing digitally recorded signals, and more particularly to a data reproducing apparatus equipped with an adaptive equalizer and an adaptive equalizing control method therefor.

[0002]

2. Description of the Related Art Digital signal reproducing apparatuses are moving toward higher density and higher capacity. For example, in a magnetic tape device, the capacity has been increased from the conventional 9 tracks to the recording of 18 tracks and 36 tracks. Against this background,
Conventionally, in order to correctly reproduce data from magnetic tape,
Various techniques have been proposed.

The first prior art is disclosed in Japanese Patent Laid-Open No. 2-720.
There is one that uses a reproduction equalization circuit as described in Japanese Patent Publication No. 3 (JP-A) No. 3 (1999) -1995.

FIG. 41 shows a data reproducing apparatus according to the first prior art. 41, 1 is a read head, 2 is a preamplifier that amplifies a signal read from the head 1 to a constant amplitude value, 3 is an analog-to-digital converter (A / D converter), 4 is a digital filter, and 5 is A digital / analog converter (D / A converter) 6 is a clock supply circuit.

When the magnetic tape 8 is moving at the first speed, the read signal passed through the head 1 and the preamplifier 2 is A / A
An equalizing circuit composed of a D converter 3, a digital filter 4, and a D / A converter 5 equalizes the waveform to an appropriate waveform and outputs the waveform. Next, when the magnetic tape 8 is moving at the second speed 2, the read signal that has passed through the head 1 and the preamplifier 2 shifts in a direction with a higher frequency than at the first speed. Therefore, the clock switching signal 7 is input to the clock supply circuit 6 to change the frequency characteristics of the equalization circuit. As a result, a clock having a frequency different from that described above is output from the clock supply circuit 6, and the frequency characteristics of the equalization circuit including the A / D converter 3, the digital filter 4, and the D / A converter 5 change. As a result, a signal equalized to an appropriate waveform is output from the equalizing circuit having characteristics suitable for the second speed.

As a second prior art, Japanese Patent Laid-Open No.
As described in 112568, by reading out a reproduction signal of an electromagnetic conversion system for converting a magnetic change of a magnetic recording medium into an electric signal through a waveform equalization circuit, the frequency characteristic of the magnetic conversion system is corrected by the waveform equalization circuit. Something you are doing.

FIG. 42 is a block diagram showing a configuration of such a conventional reproducing apparatus. In the figure, 8 is a magnetic tape, 1 is a magnetic head, 903 is an automatic gain variable amplifier (AGC), 905 is a first waveform equalizing circuit, 906, 9
07 is a delay circuit, 908 to 910 are multipliers, 911 and 9
73 denotes an adder, 970 denotes a second waveform equalizing circuit, 971 denotes an integrating circuit, and 972 denotes a differentiating circuit.

The reproducing apparatus of the second prior art converts a magnetic signal due to a magnetic change recorded on the magnetic tape 8 into a magnetic signal by the magnetic head 1. This part is called an electromagnetic conversion system, and has a frequency characteristic such that the frequency fo has a maximum value and falls to a low band and a high band as shown in FIG. 43 (a). For this reason, a signal with a low magnetic change or a signal with a high magnetic change causes a rise in the reproduction bit error rate due to a decrease in signal level or waveform distortion. Therefore, in the prior art, the AGC 903 makes the amplitude of the magnetic tape reproduction signal constant, and the first waveform equalization circuit 905 and the second waveform equalization circuit 970 correct the frequency characteristics of the electromagnetic conversion system. I am taking.

The first waveform equalizing circuit 905 includes a delay circuit 9
06, 907, multipliers 908 to 910, and adder 91
1 to form a wide-pass filter, and the K filter shown in FIG.
As shown in FIG. 2, a high frequency band is amplified from fo of the electromagnetic conversion system. On the other hand, the second waveform equalizing circuit 970 includes an integrating circuit 97
43, a differentiating circuit 972 and an adder 973 constitute a low-pass filter, and as shown by K1 in FIG.
Amplify the low band below o. Thus, the first waveform equalization circuit 905 and the second waveform equalization circuit 970
A filter having the frequency characteristic shown in FIG. 43B is formed.
The frequency characteristic has a characteristic opposite to that of the electromagnetic conversion system. Therefore, the magnetic signal on the magnetic tape 8 is transmitted to the electromagnetic conversion system by the first and second waveform equalizing circuits 905 and 970 in FIG.
Reproduction is performed with flat frequency characteristics as shown in FIG. This reduces the signal level and waveform distortion,
Reproduction bit errors can be reduced.

[0010]

The equalizing circuit according to the prior art described above can absorb a change in the characteristics of the data reproducing system. However, it has been found that these conventional techniques have the following problems.

In the first prior art, since the equalizing circuit is switched and used in response to a change in the running speed of the tape, changes in other characteristics, for example, whether the matching with the tape is good or not, a change in the time of the system, etc. Cannot adapt to changes in

In the second prior art, the DC signal component is suppressed, so that the reproduction of data with small intersymbol interference and a bit error rate sufficiently low for practical use can be performed. As for adapting to fluctuations in system properties,
There is no consideration.

In both the first and second prior arts, no consideration is given to reproduction of multiple tracks.
Generally, a magnetic tape composed of a plurality of tracks (for example,
In the reproducing circuit of the MT device of the computer), it is necessary to provide an electromagnetic conversion system and an equalizing circuit for each track. Further, the frequency characteristics of each electromagnetic conversion system differ between tracks due to variations in manufacturing the magnetic head. Therefore, the equalization circuit for correcting the frequency characteristics of each electromagnetic conversion system needs to adjust the frequency characteristics for each track, and there is a problem that the adjustment is troublesome. In particular, when the number of tracks is large, the range of variations in the characteristics of the system for those tracks is widened. Therefore, if the adjustment of the equalizing circuit cannot be performed sufficiently, the read margin of the data reproducing apparatus becomes small and the reliability decreases. A problem arises, and the device is easily affected by restrictions such as the quality of matching with the tape, and is difficult to use.

Further, according to the above-mentioned conventional technique, when there is an abnormality in the reproduced data, it is not possible to distinguish whether the adaptation state of the equalizing circuit is defective or the reproduction system is abnormal. There's a problem.

Further, some recent magnetic tape devices reproduce data not only when the magnetic tape runs in the forward direction but also in the reverse direction. In such a case,
Since the reproduction conditions are different, the characteristics of the reproduction system are different between the forward direction and the reverse direction. However, no consideration is given to this point in each of the conventional techniques.

A first object of the present invention is to make it possible to adapt an equalizing circuit in response to fluctuations in the characteristics of a data reproducing system, and to easily perform adaptation even in the case of a large number of tracks, thereby increasing the read margin. And a highly reliable data reproduction method and apparatus.

A second object of the present invention is to provide a data reproducing method and apparatus which can easily detect an abnormality.

A third object of the present invention is to provide a data reproducing method and apparatus capable of appropriately and easily adapting an equalizing circuit when reproducing under different reproducing conditions, for example, when performing bidirectional running or the like. To provide.

A fourth object of the present invention is to provide a data reproducing apparatus which is provided with means for stopping an equalization function and switching a coefficient in the event of the following abnormalities and in which adaptive equalization does not malfunction, and an adaptive equalization control method. It is in.

(1) When the equalization error suddenly reaches an excessively large level during the start of adaptive learning and during adaptive equalization.

(2) When an input signal level is out of a discrimination range set for signal discrimination or a signal having an ambiguous value is detected.

(3) When an input signal having no periodicity is detected in adaptive learning.

(4) When the peak value of the input signal and the clock signal synchronized with the peak value exceed a predetermined value.

(5) When abnormal demodulation is detected when demodulating a signal.

(6) When the coefficient value of the adaptive equalizer exceeds a predetermined value, there is provided means for switching a preset gain to the coefficient value or a step gain for updating the coefficient.

[0026] A fifth object of the present invention is to provide a magnetic recording / reproducing apparatus which is capable of detecting a discrimination error in the data discriminating means.
An object of the present invention is to provide a data reproducing apparatus having a function of presetting or resetting a coefficient value of an adaptive equalizer and retrying an adaptive equalizing operation, and an adaptive equalizing control method.

[0027]

According to the present invention, there is provided a data reproducing method using an adaptive equalizing circuit for reproducing data recorded on a storage medium. Detects a signal that can be used for adaptive learning, and performs adaptive learning of the adaptive equalizer using this signal to extract the characteristics of the input signal in a specific pattern area and adjust the coefficient value of the adaptive equalizer appropriately. After that, a data reproduction method is provided in which adaptive equalization is performed in a data area.

According to the present invention, in order to achieve the second object, when reproducing data from a storage medium having a plurality of tracks, adaptive learning is performed on a plurality of adaptive equalization circuits corresponding to each track. And a data reproducing method for detecting the presence or absence of an abnormality by comparing the adaptation result in each adaptive equalization circuit.

Further, in order to achieve the third object,
In a data reproducing method for reproducing data recorded on a storage medium using an adaptive equalizing circuit, when performing reproducing with different characteristics, adaptive learning of the adaptive equalizing circuit is performed using a certain characteristic as a basic characteristic. The adaptive learning for the other characteristics is performed by calculating the adaptive learning result obtained for the basic characteristics using the relative characteristics between the two characteristics.

Similarly, according to another aspect, when performing reproduction with different characteristics, the adaptive learning of the adaptive equalizer circuit is performed with a certain characteristic, and the adaptive learning for the other characteristic is performed by initializing the learning result. It is characterized in that it is performed by setting a value.

Similarly, according to still another mode, when performing reproduction with different characteristics, an initial value is given to each of them and adaptive learning is performed for each.

On the other hand, in order to achieve the first object, according to the present invention, the apparatus has an adaptive equalization circuit for performing equalization processing on a signal read from a storage medium, and an adaptive equalization circuit reading from the storage medium. Adaptive signal detection means for detecting a signal that can be used for adaptive learning of the adaptive equalization circuit from the signal to be output; and an error for comparing the output of the adaptive equalization circuit with an expected value to output an error signal. Detecting means for detecting a signal that can be used for adaptive learning by the adaptive signal detecting means, the adaptive equalizing circuit is set inside the adaptive equalizing circuit using the signal. A function of performing an adaptive operation according to a coefficient according to an adaptive operation that receives an error signal fed back from the error detecting means and updates an internal coefficient of the signal to change its characteristic. Data reproducing device is provided which is characterized by having a function of performing learning.

According to one aspect of the present invention, a means for reading a coefficient value of an adaptive equalizing circuit and detecting an abnormality from a time change of the read coefficient value. And a data reproducing apparatus comprising:

According to another aspect, there are means for reading a coefficient value of each adaptive equalizer circuit having a plurality of adaptive equalizer circuits, and means for detecting an abnormality by comparing the read coefficient values. A data reproducing device comprising:

Further, in order to achieve the third object,
According to one aspect of the present invention, an adaptive equalization circuit that performs equalization processing on a signal read from a storage medium, a unit that retains a relative characteristic between different characteristics, Means for reading a set coefficient as a result of the adaptive operation of the equalizing circuit, and converting the read coefficient into a coefficient that can be placed in another characteristic using the relative characteristic, And a data reproducing device.

Similarly, according to another aspect, an adaptive equalization circuit that can change characteristics by adaptive learning and performs equalization processing on a signal read from a storage medium, and an adaptive equalization circuit for each of different characteristics. Means for storing and holding the set coefficient as a result of the adaptive operation of the equalization circuit, and means for selecting the held coefficient according to the characteristic and setting the selected coefficient in the adaptive equalization circuit. A featured data reproducing apparatus is provided.

[0037]

The adaptive signal detecting circuit detects the adaptive signal read prior to the data and outputs the signal to an adaptive equalizing circuit (hereinafter, also simply referred to as an equalizing circuit). When the signal is input to the equalizer, the equalizer uses an adaptive signal so as to output an optimal signal to the data discriminator, and changes and adapts each coefficient of the equalizer. As a result, variations in the head are suppressed, and a signal suitable for data discrimination is output.

The above operation is performed before data is read out.
Alternatively, for example, in the case of a magnetic tape, if the operation is performed when the tape is mounted on the apparatus, a signal suitable for the data discrimination circuit can be output in response to the aging of the head.

Further, by providing means for comparing the output of the equalizer circuit with the expected value and changing the rate at which the result is fed back, the output from the equalizer circuit becomes the expected value. Then, the return ratio is reduced. Further, during the adaptive learning or the adaptive operation, the magnitude of the error amount output by the error detection means is monitored, and the error amount is compared with a preset allowable value. If the error amount exceeds the allowable value, This error is judged to be a sudden temporary abnormal state, and an error allowable excess signal is transmitted to the error correction means or the error correction stop means so as not to temporarily correct the coefficient due to this error. The error correction means receives the error allowable excess signal, automatically corrects the error amount to an appropriate value, and sends the value to the adaptive equalizer as a correction error. As a result, in the adaptive equalization, the coefficient does not diverge due to the update of the coefficient due to the temporary abnormal value. The coefficient correcting means is used as an alternative to the error correcting means, and stops the adaptive equalizer from correcting the coefficient in response to the error allowable excess signal. As a result, it is possible to prevent the divergence of the coefficient and the decrease in the convergence speed of the coefficient caused by correcting the coefficient by the temporary abnormal input.

The discriminating means discriminates the output signal of the adaptive equalizer based on a discrimination range limited by preset upper and lower thresholds. At this time, the discrimination abnormal means monitors the state of the discrimination, and sends out an abnormal signal when detecting a signal having an ambiguous level that does not belong to any discrimination range. The coefficient correction stopping means stops the adaptive equalizer from correcting the coefficient upon receiving the abnormality detection signal. As a result, when an ambiguous signal is erroneously discriminated, erroneous correction of the coefficient due to the erroneous discrimination result is prevented.

Further, the demodulation means decodes the modulated signal into an original data bit sequence according to the modulation scheme. At this time, the decoding abnormality detecting means monitors this state, and sends out an abnormality detection signal when a demodulation error is detected. The coefficient correction stopping means stops the adaptive equalizer from correcting the coefficient in response to the abnormal signal. Thus, when a demodulation error occurs, it is determined that some abnormal state has occurred in the transfer system, and the characteristic of this abnormal state is prevented from being reflected in the adaptive equalization coefficient.

Further, in the magnetic recording apparatus, when the demodulation error is detected, the detection signal is received, and the coefficient of the adaptive equalizer is preset to an initial value or a parameter stored in an external memory is loaded. The error portion of the medium in which the demodulation error has occurred is retried a predetermined number of times. As a result, data can be reproduced even from a dropout signal on the medium, and the reliability is improved.

Further, by providing means for reading out the coefficient value from the equalizing circuit, when the coefficient value becomes abnormal,
An abnormal operation of the data reproducing apparatus can be suppressed by notifying the host system of the fact or replacing it with a provisional value.
Further, the provision of the setting means for the equalizing circuit makes it possible to set the previous coefficient value or reset the coefficient value when the power of the apparatus is turned on. To cope with reproduction in bidirectional running, the adaptive state of the equalization circuit is changed in the forward and reverse directions,
It is necessary to change each time, and it takes time and effort to adjust, and the circuit for the adjustment becomes complicated. These problems are particularly serious in the case of multiple tracks.

Such a problem occurs not only in the difference in the traveling direction but also generally in the case where the reproduction condition is different. Similarly, some countermeasure is required.

To achieve the fifth object, an external storage memory for initially setting coefficients of the adaptive equalizer, discriminating means for an output signal of the adaptive equalizer, and demodulating means for demodulating an output signal of the adaptive equalizer into a data bit sequence based on the discriminated signal. A demodulation abnormality detecting means for detecting a demodulation abnormality generated by the means and transmitting an abnormality detection signal; and an adaptive equalizer by switching some parameters stored in an external memory in accordance with the abnormality detection signal. A data reproducing apparatus provided with means for changing the coefficient of adaptive equalization and repeating the adaptive equalization operation a predetermined number of times at the same location on the recording medium where demodulation abnormality has occurred. . In addition, the input signal switching circuit allows the input to the equalization circuit to which the adaptation signal is not input via another head, thereby enabling the adaptive operation of the plurality of equalization circuits. In addition, since each of the above-mentioned means can perform digital signal processing, it can be easily implemented as an LSI, and a high-density mounting of a data reproducing apparatus is possible.

In addition, the adaptive operation of the adaptive equalization circuit between different characteristics can be dealt with by converting from the basic characteristics and using the result of learning of one characteristic as the initial value of the adaptive operation for the other characteristic. For example, adaptive learning at the time of bidirectional running of a tape is appropriately and easily performed.

[0047]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, it is divided from the first on the data reproduction method for performing optimal adaptive equivalence to the twelfth embodiment, the from the (1) relates to the abnormality detecting method further using these techniques ( Example 6) will be described.

FIG. 1 shows the configuration of the first embodiment of the present invention.

In FIG. 1, 101 is a magnetic tape as a recording medium, 102 is a reading head, 103 is a preamplifier, 104 is a differentiating circuit, 105 is a peak pulse generating circuit, and 106 is a phase in which a change point of a peak pulse is synchronized. A reference clock generation circuit for generating a clock signal, 107 is a NAND circuit, 108 is a peak data pulse interval monitoring circuit, and 109 and 110 are analog-to-digital converters (A / D
Converter), 111 is a subtractor, 112 is an adaptive equalization circuit that can change the characteristics and performs equalization processing on a signal read from a recording medium, and 113 is a Japanese Patent Application Laid-Open No. Heisei 2-016256.
Reference numeral 114 denotes a data discriminating circuit for identifying data as 1 or 0 by the maximum likelihood decoding method, 114 denotes an expected value generating circuit for generating an expected value of the adaptive equalizing circuit, and 115 denotes a tape format detecting circuit.

In the adaptive equalization circuit 112, 11
Reference numerals 6 to 121 denote delay circuits for delaying data, and include latch circuits and the like. 125 to 129 are multiplication circuits, 130
To 132 are coefficient circuits for determining coefficients of the multiplication circuit;
3 is the delay circuits 116 to 119 and the multiplication circuits 125 to 1
This is an addition circuit for summing up the signals passing through 29. With these circuits, the adaptive equalization circuit 112 receives the function of performing the adaptive operation according to the coefficient set therein and the error signal obtained for the signal output as a result of the adaptive operation, and updates the coefficient. Thus, the function of changing the characteristic and performing the adaptive equalization is configured and realized.

Reference numeral 114 denotes an expected value for generating an expected value a corresponding to the output of the peak data pulse generating circuit 105 which is an expected value at the time of adaptive learning and the output of the data discriminating circuit 113 which is an expected value at the time of adaptive equalization. It is a generation circuit. An error detection circuit (adder) 158 functions as an error detection unit that outputs an error signal by comparing the output of the equalization circuit 112 with the expected value a . Reference numeral 134 denotes a coefficient switching circuit that switches an error feedback coefficient, 135 and 136 denote feedback coefficient circuits that set a feedback coefficient α that determines the ratio of error feedback, and 137 denotes a multiplication circuit. This constitutes a means for determining the proportion of feedback to the error adaptive circuit.

The coefficient circuit 131 includes the coefficient circuits 130 and 13
It is the figure which showed the details of 1 and 132. In the figure, 1
38 is a multiplication circuit, 139 and 140 are delay circuits for delaying data, 141 is a delay circuit 139 and a delay circuit 1
39, an addition circuit for adding the signals passed through the delay circuit 140; Delay circuits 139 and 140, and addition circuit 141
FIR filter (finite impulse
response) . FIR type fill
Is characterized by the ability to achieve perfect linear phase characteristics.
You. The error signal that has passed through the FIR filter is added to each of the multiplication circuits 125
To 129, and the coefficient is updated. 108
In FIG. 2, the reference pattern clock signal 205 counts up from the position A of the peak data pulse 204, which is the output signal of the NAND circuit 107, to generate the specific pattern period detection window signal 206 existing outside the data block on the tape format. Generate.

Further, if the next peak pulse 204 is present in this window, the "H" level is set, and if not, the tone pattern (100
0001000001 repetition period pattern) signal 20
7 is output. That is, the interval value X of the peak data pulse 204 is a signal between the lower limit value N1 and the upper limit value N2 of the tone pattern signal 207. The tone pattern signal 207 is output to the tape format detection circuit 11.
5 is input to the OR circuit 156 together with the output signal. The expected value generation circuit 114 is provided in the tape format detection circuit 11.
5, the recording density identification unit (Densi
When a ty ID Mark or less is simply referred to as DenID Mark) or an inter block gap existing between data blocks (hereinafter simply referred to as IBG) is detected, a peak data pulse is obtained from discrimination data in other cases. Sets of four AND circuits 147, 148, 149, 1
50 and two sets of OR circuits 151 and 152 and a memory 153 in advance at a timing synchronized with the selected signal.
A memory 153 that outputs the positive and negative expected value a set in
And an expected value generation circuit including selection circuits 154 and 155.

The operation of the present invention will be described below with reference to FIGS.

The data recorded on the magnetic tape 101 is
Via the read head 102 and the preamplifier 103, the operation type A / D conversion circuits 109 and 110 and the differentiation circuit 1
04. And an operation type A / D conversion circuit 109,
At 110, the digital signal quantized at the interval of the reference clock signal whose phase is synchronized with the peak value of the input signal is converted into a single signal by the subtraction circuit 111,
16 to 119, multiplication circuits 125 to 129, addition circuit 13
The waveform is shaped (waveform equalized) by the transversal type filter constituted by 3 and output from the equalizing circuit 112.
Thereafter, the signal output from the equalization circuit 112 is discriminated by the data discrimination circuit 113 into data “1” or data “0”.

On the other hand, in the differentiating circuit 104, after generating a differential waveform that crosses zero at the peak point of the analog waveform,
The data is sent to the peak data circuit 105. The peak data circuit 105 generates a peak data pulse 202 having a predetermined pulse width when the analog signal has a peak on the positive side, and generates a peak data pulse 203 having a predetermined pulse width when the analog signal has a peak on the negative side. And output. Then, the peak pulse data pulse is output to the NAND circuit 107.
Are sent to the peak data pulse interval monitoring circuit 108 and the reference clock generation circuit 106 via

Subsequently, the reference clock generation circuit 106 generates a clock signal 205 whose phase is synchronized with the transition point of the peak data pulse, and sends it to the peak data pulse interval monitoring circuit 108 and the A / D conversion circuit.

On the other hand, the peak pulse interval monitoring circuit 108 monitors the interval of the peak pulse with the reference clock, and sets the "H" level for the tone pattern which is a specific pattern other than the data block DB. If it is a pattern, the “L” level is set. That is, the interval X between the peak data pulses is a signal between the lower limit value N1 and the upper limit value N2 of the tone pattern signal. The tone pattern signal is supplied to the OR circuit 1
56 is input. Peak data pulse monitoring circuit 108
The purpose of is to modify the coefficients by returning the equalization error signal only for the correct expected value signal in the adaptive learning in the Den ID Mark section and the IBG section to change the characteristics of the adaptive equalizer 112. In this case, the peak data monitoring circuit 1
When 08 detects an abnormal signal that is not a tone pattern,
Since the gate 157 is closed via the OR circuit 156 and zero is output to stop updating the coefficient, the characteristics of the adaptive equalization 112 are not changed.

According to the adaptive equalizer of this embodiment, since the peak data pulse monitoring circuit 108 is provided, the adaptive learning operation is temporarily performed only in the case of an abnormal input signal which is not a repetition pattern of the tone pattern period during the adaptive learning. Can be stopped. As a result, the adaptive learning operation does not follow an erroneous input signal.

On the other hand, the head of the magnetic tape is recorded in the format shown in FIG. That is, prior to the data block DB, the Den ID Mark section,
ID separator mark (ID Sept mark)
And an IBG section, a data block DB, and an IBG section are provided in this order. Tape format detection circuit 115
Is the Den ID recorded near the beginning of the tape
Mark or IB existing between data blocks DB
When the G section is detected, an L level signal is output, and when other signals are detected, an "H" level signal is output. That is,
This is because it is determined that the signal of the mark portion is suitable as the adaptive learning signal because it is known in advance what is recorded. The “L” level signal is sent to the OR circuit 156, the coefficient switching circuit 134, and the expected value generation circuit 114. An “L” level signal is output from the expected value generation circuit 114.
, The peak data pulse is selected, the expected value signal a corresponding to “1”, “0”, and “−1” of the peak data pulse is changed to the signal of the “H” level.
When the data is inputted to the data discriminator 14, an expected value signal a corresponding to the data "1", "0", "-1" of the output signal from the data discriminator 113 is outputted. The error detection circuit 158 outputs an error signal which is a difference between the expected value signal and the output of the adaptive equalization circuit 112. The error signal is output to the gate circuit 15
7

On the other hand, when an "L" level signal is input to the coefficient switching circuit 134, the position is switched to the position shown in FIG. 1, and a feedback coefficient 136 having a large feedback coefficient α1 is selected. This large feedback coefficient α1 is determined by delay circuits 116-1
The input signal passed through 19 is multiplied by the multiplication circuit 137, and is fed back to the corresponding coefficient circuits 130, 131 and 132 via the delay circuit 120 and the delay circuit 121.

The signal output from adaptive equalization circuit 112 is ideally desired to be the same as the expected value signal, but is actually different. The input signal multiplied by the large set value of α1 by the multiplication circuit 137 is output to the coefficient circuits 130 and 13
1 and 132. In the coefficient circuits 130, 131, and 132, the multiplied circuit 138 calculates the error signal output from the error detecting circuit 158 by the corresponding multiplying circuit 138, and then calculates the delayed input signal. The signal is filtered by an adder circuit 141, the adder circuit 142, the delay circuit 1
43, a new coefficient value obtained by adding or subtracting an error value from the previous coefficient value is output.
9, the input and output signals of the delay circuits 116 to 129 are multiplied by a coefficient and input to the addition circuit 133.
Output signal.

The coefficient values of the coefficient circuits 130 to 132 are as follows:
As shown in FIG. 3, the adaptation circuit 112 is not adapted,
In the early stage of adaptive learning, where the error from the expected value is large, it changes greatly, and the equalization circuit 112 adapts, and the change in the coefficient decreases as the value approaches the expected value. Then, the output signal of the equalizer circuit and the output signal 2 of the peak data pulse circuit 105
The coefficient is updated by an error signal which is a difference between expected values generated from the coefficients 02 and 203. When the coefficient becomes smaller to some extent, the coefficient stops changing. The coefficient of the coefficient circuit 130 is A1, and the coefficient of the coefficient circuit 131 is A2. It is decided.

The time until each coefficient does not change is the adaptive learning time T, and the Den IDMark part or I
While the BG section is being read, the adaptive learning is performed only for the correct expected value signal a monitored by the time monitoring circuit 108.

When an incorrect peak data pulse signal is detected by the pulse interval monitoring circuit 108, the pulse interval monitoring circuit 108 outputs an "L" level signal, and this signal is output through the OR circuit 156. When the signal is input to the gate circuit 157, the switch is switched to the position opposite to that in FIG. 1 and becomes zero, and thus the coefficient is not updated by this error signal.

Thereafter, the tape advances, and the read head 1
When the data block DB is read from 02, the tape format detection circuit 115 outputs an "H" level signal as shown in FIG. The “H” level signal of the tape format detection circuit 115 is
56, expected value generation circuit 114, coefficient switching circuit 134
Sent to When the “H” level signal is input to the OR circuit 156, the gate circuit 157 outputs the signal via the OR circuit.
The switch is selected at the position shown in FIG.

On the other hand, the expected value generation circuit 114 selects the discrimination data in response to the "H" level signal, and the coefficient switching circuit switches the switch to the position opposite to the position shown in FIG. Is selected. This is because, after the adaptive learning operation is completed, the equalization circuit 112 absorbs the variation of the medium, the head, and the like, and equalizes the medium to the optimum state. As a result, the error signal from the error detection circuit 158 is large. This is because if a large error signal is output, it is determined as temporary noise and ignored.

When the small feedback coefficient α2 is selected as described above, the temporary large error signal is also multiplied by the multiplication circuit 138.
And the coefficient values of the coefficient circuits 130 to 132 are not greatly changed. In addition, at the time of dropout in which a large error signal is continuously output, even if the feedback coefficient α2 is small, the error is gradually fed back to the coefficient circuits 130 to 132. Therefore, after the adaptive learning operation, an optimal operation is performed in which the adaptive learning operation is not adapted to a temporary noise signal but is adapted to continuous operation such as dropout.

As described above, (1) Den ID Ma on magnetic tape format
The adaptive learning is performed only on the correct expected value signal in the rk and the IBG area, and then the adaptive signal is switched to the expected value signal generated from the discrimination circuit 113 in the data area. The recording data can be read and executed in an adaptive equalization state.

(2) At the time of adaptive equalization, a small coefficient α2 is selected and data is read and reproduced while performing a gentle adaptive equalization operation. Therefore, the expected value temporarily generated from the timing of the discrimination data due to dropout or the like. However, even if an error occurs, the equalizing circuit 112 does not malfunction.

In the above-described embodiment, an example has been described in which the adaptive equalization operation is performed after the adaptive learning using the specific pattern signal recorded in the format signal of the magnetic tape. However, the present invention is not limited to the above-described embodiment. It goes without saying that various changes can be made without departing from the spirit of the invention. For example, the present invention is widely applicable to other magnetic recording / reproducing devices such as a magnetic disk and an optical disk.

In the above embodiment, the description is made using the equalizing circuit 112 of one read head, and the other tracks are described in the same manner. However, it is also possible to perform a different adaptive operation as in the following embodiment.

Next, a second embodiment of the present invention will be described.

This embodiment is particularly suitable for reproducing a magnetic tape having a specific format. FIG. 5 (a)
FIG. 4 is a diagram showing contents recorded in an IBG area existing between data blocks of a magnetic tape. In the odd-numbered track, only a signal of data “1” called “all 1” is recorded, and in the even-numbered track, a repeated signal of data “1000001” called a tone pattern is recorded.

FIG. 6 is a block diagram showing a data reproducing apparatus of a magnetic tape device according to a second embodiment of the present invention. FIG.
, 36 is an A / D conversion circuit for the first track, 3
8 is a track switching circuit, 39 and 40 are respective adaptive equalization circuits, and 41 is a switching control circuit.

Hereinafter, the operation of this embodiment will be described with reference to FIGS. Note that the adapting operation itself is the same as that of the embodiment shown in FIG.
The switching control circuit 41 is provided with a tape format detecting function as in the embodiment shown in FIG.

The track switching control circuit 41 detects the presence of the IBG area based on the combination of the tone pattern signal recorded prior to the data block on the magnetic tape and the all "1" data pattern, and as shown in FIG. Then, a signal of level “1” is input to the track switching circuit 38 as a track switching signal. Level "1"
The track switching circuit 38 switches to the position shown in FIG. 6 and the signal from the second track A / D conversion circuit 37 is input to the first track adaptive equalization circuit 39. Is done. Therefore, FIG.
The tone pattern signal recorded on the second track shown in (a) is input to the first track adaptive equalization circuit 39, and the adaptive learning operation of the equalization circuit 39 is performed. Thereafter, after a time T sufficient for completing the adaptive learning operation, a signal of “0” level is output from the switching control circuit 41,
The track switching circuit 38 is switched to a position opposite to that in FIG. Therefore, the data signal recorded on the first track shown in FIG. 5A is input to the first track adaptive equalization circuit 39. Then, an adaptive operation is performed by a data signal corresponding to each track.

As described above, the track switching circuit 38
Accordingly, it is possible to input a tone pattern signal to an adaptive equalization circuit to which an all-one signal is originally input, thereby enabling adaptive learning. In addition, the first and second adaptive equalizing circuits 3
After the completion of the adaptive learning operation in steps 9 and 40, the adaptive operation is performed with a small feedback coefficient α2 as in the embodiment of FIG.

In FIG. 7, reference numerals 42 and 43 denote A / D conversion circuits, and reference numerals 44 and 45 denote adaptive equalization circuits similar to those of the above-described embodiment. The coefficient values of the respective multiplication circuits become readable / writable. I have. 46 and 47 are data discrimination circuits.
Reference numeral 48 denotes a microcomputer, which is an adaptive equalizing circuit 4
It reads out each coefficient value of 4, 45, sets an arbitrary value, and notifies and receives various kinds of information to an upper central processing circuit (not shown). 49 is a memory circuit. The microcomputer 48 has a function as a coefficient value reading / setting means as a part of each function. In this embodiment, a switching control circuit may be provided as in the embodiment shown in FIG.

As in the first and second embodiments, the DenID Mark or IBG recorded on the tape is used.
Using the signals, the adaptive equalization circuits 44 and 45 perform an adaptive learning operation. Thereafter, the microcomputer 48 reads out the respective coefficient values of the multiplication circuits in the adaptive equalization circuits 44 and 45 and stores them in the memory circuit 49.

Then, the magnetic tape of the data reproducing apparatus is
Assume that the tape has been replaced with another magnetic tape. The microcomputer 48 reads the previously stored coefficient value from the memory circuit 49 to prevent each of the adaptive equalizer circuits 44 and 45 from performing an adaptive operation from zero, and stores the read coefficient value in each of the corresponding adaptive equalizer circuit. Set.

With the above configuration, it is possible to shorten the time required for adapting the newly mounted magnetic tape to the optimum equalized state. This is because the coefficient value includes the variation of each head, and as a result, the adaptive operation starts from the middle of the curve in FIG.

The memory circuit 49 is made nonvolatile by using a battery or the like, and immediately after the power of the data reproducing apparatus is turned on, as described above,
It is also possible to initialize each coefficient value.

Also, the memory circuit is not nonvolatile, and immediately after the power of the data reproducing apparatus is turned on, various kinds of tape recording densities, optimal recording / reproducing, and forward / backward optimum coefficients are obtained from the floppy 50 as shown in FIG. Is written into the X register 53, and the Den ID M recorded at the head of the tape is written.
From the ark information, a target coefficient value is loaded from the X register 53 to the memory 54 by a control signal, and the coefficient value read from the memory 54 is set in the adaptive equalization circuit 55, so that the recording density and the operation mode , And it is also possible to adapt earlier than adapting from a completely new value. .

In the data reproducing apparatus, when a reproduction error occurs, the error occurrence position on the magnetic tape is retried about 40 times, and if the data cannot be read, a permanent read error is generated. By reading the coefficient set in the RAM during the 40 trials and changing the coefficient value and retrying, data that could not be read by the conventional trial of the fixed coefficient value is read during the retry. can do.

In the embodiment shown in FIGS. 7 and 8, an example is shown in which the microcomputer 48 or the memory 54 is used as coefficient value setting means to set the coefficient value of the adaptive equalization circuit. However, the same effects as above can be obtained by using another circuit and setting an arbitrary value when the power is turned on, changing an arbitrary coefficient value during the adaptive equalization operation, or presetting to an initial value. .

In the embodiment shown in FIGS. 7 and 8, an example is shown in which the memory 54 and the microcomputer 48 are used as coefficient value reading means to read out the coefficient values of the adaptive equalization circuit. It is also possible to cause another operation. That is, the memory 54 and the microcomputer 4
8 is used to function also as abnormality detection means (the first embodiment).

FIGS. 9A and 9B are diagrams for explaining the operation when an abnormality such as a dropout exists in the data block DB of the magnetic tape and the IBG.

The tape format detection circuit 1 shown in FIG.
15 detects the Den ID Mark signal, and the coefficient switching circuit 134 shown in FIG.
Is selected and the adaptive learning operation is executed. If there is an abnormality such as dropout during the adaptive learning,
The change in the coefficient value of each of the multiplication circuits 125 to 129 is not a monotonous change as shown in FIG. For example, the change of the coefficient value fluctuates up and down. When the process proceeds further, an abnormality such as a coefficient value exceeding a predetermined value appears.

When the microcomputer 48 detects this, the adaptive learning or the adaptive operation is temporarily stopped. Alternatively, malfunction of the adaptive equalizer due to an abnormal signal can be prevented beforehand by presetting the coefficient value to an initial set value or zero.

Further, a second operation for temporarily stopping the adaptive equalization operation is described.
FIG. 10 shows an embodiment (2).

In the figure, 101 is a magnetic tape, 10
2 is a magnetic head 57 is an automatic gain variable amplifier (AGC),
109 analog-to-digital converter (A / D), 61 is a transversal equalizer, 130 to 132 are coefficient update circuits, 60 is an error detector that calculates an output signal of the equalizer and an expected value to generate an error signal A comparison circuit 59 compares the output of the error detection circuit 60 with a predetermined value (1A, 2A) which is the maximum allowable range of the equalization error at the beginning of adaptive learning and during adaptive equalization. It consists of a gate that opens and closes according to the result, monitors the magnitude of the equalization error,
The adaptive learning and the adaptive equalizing operation are temporarily stopped when an equalization error during the adaptive learning or the adaptive equalization exceeds a predetermined value.

Next, the operation of this embodiment will be described.
First, the A / D conversion output value X of the input signal at time Tj
j is the transversal equalization circuit 61 and the coefficient circuit 130
To 132. The output Y of the equalizing circuit 61
j is input to the error detection circuit 60, and the error detection circuit 60 outputs the difference between the equalized output Yj and the expected value dj, that is, the equalized error ej.

Further, the equalization error ej is input to the comparing circuit 59, and the set value 1A of the allowable value range of the initial equalization error during adaptive learning and the set value of the allowable value range of the equalization error during adaptive equalization Compared to 2A. At the same time, the equalization error ej is
8 and is gated by the output of the comparator 59. In other words, as shown in FIG.
When j is larger than a predetermined value 1A, the equalization error e during adaptive equalization e
When j is larger than a predetermined value 2A, the gate 58 is closed and zero is output. On the other hand, when the equalization error ej is smaller than or equal to the predetermined values 1A and 2A, the gate 58 is opened and the equalization error ej is opened. The same value as is output.

The outputs of the gate 58 are input to coefficient circuits 130 to 132, respectively.
Updates the coefficient by the adaptive algorithm described in the embodiment of FIG. 1 and changes the equalization characteristic of the equalizer 61. In this case, during the period in which the gate 58 is closed and zero is output, the output of the equalization circuit 61 is determined to be in a form most suitable for the purpose, so that the characteristics of the equalization circuit 61 are not changed. .

Therefore, according to the adaptive equalizer of this embodiment,
A comparator 59 is combined with a predetermined value 1A which is the maximum allowable range of the equalization error ej at the time of the equalization learning and a predetermined value 2A which is the maximum allowable range of the equalization error ej at the time of the adaptive equalization. By providing the gate 58 that is opened and closed, the equalization error e
adaptive learning only when j exceeds predetermined values 1A, 2A,
Adaptive equalization can be suspended. This allows
Without following the input signal xj larger than the maximum allowable range, the adaptive learning and the adaptive equalization operation are made to follow only the input signal Xj having the predetermined value 1A or less than 2A, thereby preventing the malfunction of the adaptive equalization operation due to the dropout or the like. Can be prevented.

FIG. 12 is a block diagram showing an adaptive equalizer according to a third embodiment for temporarily stopping the adaptive equalizing operation, and FIG. 13 is a diagram showing an equalization error in the adaptive equalization according to the present embodiment. FIG. 5 is an explanatory diagram showing a relationship between a lapse of time and a predetermined value (2A).

The adaptive equalizer of this embodiment is, for example, an adaptive equalizer used in a data reproducing apparatus. The adaptive equalizer 61 converts an input signal under a predetermined condition and a characteristic condition of the equalizer 61. Controlling coefficient circuits 130 to 132 and equalizing circuit 6
An error detection circuit 60 for calculating the output of 1 and the expected value;
A comparator 59 for comparing the output of the error detection circuit 60 with a predetermined value 2A which is a minimum allowable range of the equalization error; a latch circuit 63 for setting a state according to the result of the comparator 59; Gates 64 to 66 that open and close in response to
The difference from the embodiment shown in FIG.
Latch circuits 64 to 66 are connected to the subsequent stage, and when the equalization error falls below a predetermined value, the subsequent adaptive equalization operation is stopped.

That is, in this embodiment, the equalization error ej output from the error detection circuit 60 is
0 to 132 and the comparator 59. And
In the coefficient circuits 130 to 132, coefficient values for changing the characteristics of the equalizer 61 are output from the input signal Xj and the equalization error ej to the multiplication circuits 125 to 129 by the coefficient update algorithm described in FIG. You.

On the other hand, the equalization error e input to the comparator 59
j is compared with a predetermined value 2A. And the equalization error ej
And the result of the comparison with the predetermined value 2A, that is, the output of the comparator 59 is input to the latch circuit 63. Further, the latch circuit 6
3 is latched when the output of the comparator 59 indicates that the equalization error ej has become smaller than the predetermined value 2A as shown in FIG. Then, the output of the latch circuit 63 is input to the gates 64-66, and the coefficient circuits 130-1
32 outputs are gated. In this case, the gates 64 to
The output of 66 is used to change the characteristics of the equalizer 61.

Therefore, according to the adaptive equalizer of this embodiment,
A comparator 59 with a predetermined value 2A which is a minimum allowable range of the equalization error ej, and a latch circuit 64 for setting a state according to the comparator 59
To 66, the equalization error ej becomes the predetermined value 2
When the value becomes smaller than A, the state is latched by the latch circuit 63, and the outputs of the coefficient circuits 130 to 132 can be gated to stop the adaptive operation of the equalizer 12 thereafter. This allows the adaptive equalization operation to follow only the input signal Xj exceeding the predetermined value 2A without following the input signal Xj smaller than the minimum allowable range, thereby stopping the adaptive equalization operation.

FIG. 14 is a block diagram showing an adaptive equalizer according to a (4th) embodiment for temporarily stopping the equalizing operation in the adaptive equalizing control method according to the present invention.

The adaptive equalizer of this embodiment is, for example, an adaptive equalizer used in a data reproducing apparatus, and converts an input signal into a reference clock signal 106 whose phase is synchronized with the peak value of the input signal.
, An analog / digital converter 109, an equalizer 61 for changing the characteristics of an input signal under predetermined conditions, coefficient circuits 130 to 132 for controlling the characteristics of the equalizer, and an output signal of the equalizer. Discrimination means 113 and discrimination abnormality detection means 6
7, demodulation means 68 for demodulating discrimination data, demodulation means 69 for detecting abnormal demodulation, reference clock means 106 synchronized in phase with the peak value of the input signal, and the peak value of the input signal and the phase of the reference clock signal. It comprises a phase abnormality detection means 71 for monitoring the relationship and detecting a phase difference abnormality, an OR circuit 70 for ORing each abnormality signal, and a gate 58 opened / closed corresponding to the output of the OR circuit 70. Example FIG.
0, the difference from FIG. 13 is that the discrimination abnormality detection means 67, the demodulation abnormality detection means 69, and the phase abnormality detection means 71 are connected,
The adaptive operation is stopped using the detection result of the abnormal signal.

That is, in this embodiment, the data recorded on the magnetic tape 101 is
2. The clock signal is input to the A / D conversion circuit 109 and the peak data generation circuit 105 via the AGC circuit 57, and the reference clock circuit 106 outputs a clock signal synchronized with the output peak data. The clock signal is sent to the A / D converter 109 and the phase abnormality detecting means 71. The A / D converter 109 outputs a quantized signal obtained by subjecting the input signal to analog / digital conversion at a transition point of the reference clock. On the other hand, the phase abnormality detecting means 71 operates to detect that the phase difference between the peak data and the reference clock exceeds a predetermined value. Then, the output of the phase abnormality means 71 is input to the gate 58 via the OR circuit 70, and the error detection circuit 60
Is gated, that is, when the phase difference between the peak data pulse and the reference clock signal exceeds a predetermined value, the gate 58 is closed to output zero, and at other times, the gate 58 is output. When opened, the same value as the equalization error ej is output.

The output of the gate 58 is supplied to the coefficient circuit 13
The coefficient circuits 130 to 132 change the characteristics of the equalizer 61 through multiplication circuits 125 to 129 by an adaptive algorithm. In this case, gate 5
During a period in which 8 is closed and zero is output, the output of the equalizer 61 is determined to be in a form most suitable for the purpose, so that the characteristics of the equalizer 61 are not changed. Therefore, according to the adaptive equalizer of the present embodiment, by providing the phase abnormality detecting means for detecting the abnormality of the phase difference between the peak data pulse and the reference clock, the adaptive operation is performed only when the phase difference exceeds a predetermined value. Can be temporarily stopped. Accordingly, when the phase difference between the peak pulse and the reference clock signal exceeds a predetermined value due to speed fluctuation of the magnetic tape, noise, or the like, the A / D converter 109 causes the reference value shifted from the peak value of the input analog signal. Without following the temporary fluctuation of the frequency component by sampling with the clock signal,
It is possible to make the adaptive operation follow only a predetermined input signal xj, thereby preventing a malfunction of the adaptive equalization operation.

Next, there is provided a method for temporarily stopping the adaptive equalizing operation.
The embodiment (5) will be described. In the embodiment of FIG. 14, when the adaptive equalization output signal of the equalization circuit 61 is discriminated into data “1” or data “0” by the discrimination means 113, the expected value does not show a correct value as a result of erroneous discrimination. Things can happen. In this case, the coefficient circuits 130 to 132 are erroneously corrected by the error signal output from the error detection circuit 60. This example is shown in FIG. FIG.
When a signal whose output waveform from the reproducing head 57 has significantly deteriorated characteristics due to scratches, breaks, adhesion of dust, etc. on the magnetic tape is input to the data discriminating circuit 113 via the adaptive equalizer 61, the discriminating circuit If the data 113 is erroneously discriminated from the data “1” level as “0” level, the coefficient values of the coefficient circuits 130 to 132 are updated with the error signal corresponding to the erroneous expected value, and the high frequency band of the equalization characteristic is updated. It is erroneously corrected to emphasize. Thereafter, the normal reproduced waveform xj is applied to the adaptive equalizer 61.
, The high frequency is emphasized by the adaptive equalizer 61, and the characteristic is deteriorated as shown in FIG. If such incorrect correction of the coefficient is repeated, the coefficient may be overfollowed and diverged. Therefore, three causes of gushing, disappearing, and projecting as shown in FIG. 16 can be considered as causes of erroneous discrimination. For this reason, if the slice level exceeds the slice level + A, -A, the discriminating means 113 discriminates the data as "1", or if the slice level does not exceed the + A, -A, as data "0".
And the input signal having the slice level ± A ± r value is “1”.
A pointer generating means for judging the input signal having the level and the value of 0 ± r to be 0 level is provided, and the correlation between the discriminating means and the pointer detection is monitored by the discriminating abnormality detecting means 67. The output of the discrimination abnormality detection means 67 is input to the gate 58 via the OR circuit, and is input from the error error detection circuit 60 to the effect that the outputs from the discrimination means and the pointer detection means do not match. The error ej is gated. That is, when the discrimination abnormality signal is detected, the gate 58 is closed and zero is output. At other times, the gate 58 opens to output the same value as the equalization error ej.

As described above, when the signal characteristic deteriorates over a relatively long time such as dropout, the correction of the coefficient is immediately prohibited, and adverse effects such as divergence of the coefficient due to erroneous correction can be prevented.

Next, the adaptive equalizing operation is temporarily stopped.
An example of (6) will be described. In the embodiment of FIG. 14, when demodulating a data bit string from the data discriminating means 113,
If the discriminating means 113 at the preceding stage sends an erroneous discrimination data signal, a demodulation error occurs. When the discriminating means 113 makes an erroneous discrimination, it is conceivable that the reading characteristic of the magnetic head 102 is temporarily deteriorated for some reason. Therefore, the coefficient correction of the adaptive equalizing circuit 61 at this time is considered. Will be incorrectly corrected. If the decoder 68 generates an error during decoding, the decoding abnormality detecting means 69 detects this and inputs an abnormality detection signal to the gate 58 via the OR circuit 70.
The equalization error ej input from the error detection circuit 60 is gated. That is, when the abnormal demodulation signal is detected, the gate 58 is closed and zero is output. At other times, the gate 58 opens to output the same value as the equalization error ej. As described above, when a demodulation error occurs, the correction of the coefficient by the signal is prohibited, so that the adverse effect due to the erroneous correction can be prevented.

As described above, according to the first to sixth embodiments, the adaptive equalizing operation is temporarily stopped for an abnormal input signal such as a dropout, so that the abnormal The embodiments of the control method of the adaptive equalizer that can prevent the malfunction of the adaptive equalization operation without being affected by the input signal are shown individually. It is possible to prevent the characteristic of the adaptive equalizer from being deteriorated due to the correction.

Further, when the above abnormality is detected, it is notified to a higher-level central processing unit by a microcomputer and other means, so that it is possible to inspect the deterioration of the tape and the abnormality of the read head earlier. Become.

In the above description, the case of an abnormality on the tape has been described as an example, but the present invention is not limited to this. For example, the microcomputer examines each coefficient value after the completion of the adaptive operation, and when it has a certain abnormal value, it is possible to determine that the head has become defective.

The detection of an abnormal value can be performed, for example, by reading out the coefficients of a plurality of adaptive equalization circuits and comparing them. In the example of FIG. 8, two circuits 44 and 45 are shown for the sake of simplicity. However, since a large number of circuits are actually used, an abnormality can be easily detected by comparing these circuits.

In the embodiment shown in FIG. 6, the adaptive operation of another adaptive equalizing circuit is performed by using the track switching circuit, but the microcomputer is used to set the coefficient of the first equalizing circuit to the second equalizing circuit. Even if it is set as the coefficient value of the equalizing circuit, the adaptive equalizing circuit has almost satisfactory performance.

For example, in the embodiment shown in FIG. 8, adaptive learning is performed by the adaptive equalization circuit 44, and the coefficients obtained as a result are stored in the memory circuit 49 and set in another adaptive equalization circuit 45. It can be configured. Further, learning can be performed on a plurality of equalization circuits, and the learning results can be set in other plurality of equalization circuits that have not learned.

In this embodiment, the read margin can be increased by adaptation, and even if the range of variation of the head is large, the head can be applied to a data reproducing apparatus, and the production yield of the head can be improved. This leads to a reduction in the cost of the data reproducing device.

Further, by switching the feedback coefficient between before and after the adaptation, the adaptive operation of the equalizer circuit can be performed more quickly, and the sudden abnormal input such as dropout can be performed.
There is no malfunction. That is, the reliability of data reproduction is improved.

By providing the track switching circuit, the equalizing circuit to which the adaptation signal is not input can also perform the adaptive operation.

Also, by making the coefficient values readable and writable,
Initialization of coefficient values can be performed, and quick adaptive operation can be performed.

Further, since the abnormal operation of the adaptive operation can be detected early, the abnormal operation of the data reproducing apparatus can be prevented.

In each of the above embodiments, two adaptive equalizers are shown as examples of the plurality of adaptive equalizers.
This is merely for convenience of explanation, and in practice, an adaptive equalization circuit can be provided for a larger number of tracks. In that case, it goes without saying that each of the above embodiments can be applied.

Next, a fourth embodiment of the present invention will be described.

In the following embodiments, since the reproduction conditions are different, it is suitable for the case where the characteristics at the time of reproduction are different due to variations between devices, variations between storage media, variations between tracks such as heads, and the like. An embodiment capable of coping with the above will be described. Here, the case where the tape running direction changes from the forward direction to the reverse direction will be described using an example of a magnetic tape device in which the tape running direction can be changed.

FIG. 17 is a block diagram showing the configuration of the fourth embodiment of the present invention. In the figure, 8 is a magnetic tape composed of a plurality of tracks, 1 is a magnetic head, 203 is an automatic gain variable amplifier (AGC), 204 is an analog-to-digital converter (A / D), 205 is an adaptive equalizing circuit, and 206 and 20.
7, a delay circuit; 208 to 210, multipliers; 211, an adder; 212, a comparator for comparing a read signal with an expected value; 213, a coefficient generation circuit for generating a multiplier of the multiplier;
14 to 216 are coefficient storage circuits for storing coefficients, 217 is an arithmetic processing circuit (MPU) for performing internal control of the equalization circuit,
A read-only memory (ROM) 218 stores a program of the MPU 217 and the like, a read-write memory (RAM) 219, which is a work area of the MPU 217, 22
Reference numeral 0 denotes an input port for notifying the MPU 217 of the direction in which the magnetic tape runs, and reference numeral 221 denotes a system bus used by the MPU 217 to control each circuit.

The magnetic head 1 reads magnetic information of only one of a plurality of tracks recorded on the magnetic tape 8 and converts the magnetic information into an electric signal. The read electric signal is stabilized to a constant signal amplitude by the AGC 203 and absorbed by the A / D 204 in order to absorb a change in signal amplitude due to a change in characteristics of the medium of the magnetic tape 8 and the magnetic head 1.
The A / D 204 digitizes an analog read signal and inputs the digitized signal to an adaptive equalization circuit 205 including a digital circuit.

The adaptive equalization circuit 205 includes delay circuits 206 to
207, multipliers 208 to 210, and an adder 211, a non-recursive digital filter, a comparator 212 for comparing an output value with an expected output value, and multipliers 208 to 210 based on the obtained error amount. And a coefficient generation circuit 213 for calculating the coefficient of
Coefficient storage circuit 2 for making each coefficient readable and writable from 217
14 to 216.

The non-recursive digital filter is connected to the multiplier 20
Coefficients 8 to 210, that is, coefficient storage circuits 214 to 2
The frequency characteristics are determined by the coefficient values a _{0 to} a ₂ output from 16. As shown in FIG. 19, the coefficient values a _{0 to} a ₂ change until the output signal of the non-recursive digital filter matches the expected value of the output, and finally each of the coefficient values a ₀ to a ₂
a ₂ settles down to a certain value (called a learning process). Therefore, the frequency characteristic of the adaptive equalization circuit is determined so as to match the expected value regardless of the frequency characteristic of the read signal, and the output characteristic of the equalizer circuit with respect to the read signal is made constant.

The respective coefficient values a ₀ -a of such an equalizing circuit
₂ has a configuration in which the MPU 217 can read and write via the system bus 221. Coefficient storage circuits 214-2
16 has basically the same configuration.
7 only differs from the address referred to.
The configuration of the coefficient storage circuit 214 is shown in FIG.
become that way.

Address bus 221a, data bus 221
b, IOWC 221c and IORC 221d are signal paths in the system bus 221, and signals are output from the MPU 217. Different addresses are assigned to the coefficient storage circuits 214 to 216, and the MPU 217 sends the addresses of the coefficient storage circuits 214 to 216 to be controlled to the address bus 221a.

The decoder 222 has an address bus 221a.
If the address information is the address of the coefficient storage circuit 214, the select signal cs is activated, otherwise, it is deactivated.

When the select signal cs is inactive, the selection circuits 223 and 224 select a coefficient input and a latch pulse and transmit them to the storage circuit 226. Therefore, the coefficient input is stored in the storage circuit 226 by the latch pulse, and is output to the multiplier 208 as a coefficient output.

On the other hand, when the select signal cs is active, the MPU 217 stores the coefficient value in the coefficient storage circuit 214
To read or write, either the IORC signal or the IOWC signal is activated. When the MPU 217 reads the coefficient value, the select signal cs and the IORC signal become active, and the AND circuit 225 turns on the gate circuit 227 and operates to output the coefficient output value to the data bus 221b. The MPU 217 has a data bus 221
The value on b is received, and the coefficient value in the coefficient storage circuit 214 is known.

When the MPU 217 writes a coefficient value, the MPU 217 writes the coefficient value to be written on the data bus 22.
1b to activate the IOWC signal. Since the select signal cs is active, the selection circuits 223 and 224 store the value on the data bus 221b and the IOWC 22
The signal on 1c is transmitted to the storage circuit 226. Therefore,
The storage circuit 226 stores the coefficient value output from the MPU 217.

With such a configuration, the coefficient storage circuits 214 to 216 can read and write from the MPU 217.

The read / write operation of MPU 217 is performed when forward / reverse selection signal FB changes. M
The PU 217 monitors the state of the forward / reverse selection signal FB via the input port 220 in accordance with the program stored in the ROM 218. A coefficient value in the reverse direction is calculated based on the coefficient value of.

Upon detecting that the tape running direction has changed from the forward direction (FWD) to the reverse direction (BWD) (step 1301), the MPU 217 stores the coefficients of the respective coefficient storage circuits 214 to 216 via the system bus 221. R
Transfer to the FWD coefficient area of AM 219 (step 13
02). Next, the process proceeds to step 1303, where the FWD
The coefficient an in the coefficient area is calculated according to Σ (an × TBLn) → an ′ according to the content T of the operation table prepared in advance.
BL _n is multiplied, and an operation for obtaining the sum is performed. The result an 'is stored in the BWD coefficient area of the RAM 219. This calculation table is stored in the ROM 218, for example.
Alternatively, it can be provided in the RAM 219.

In order to make this calculation easy to understand, it will be further described with reference to FIG.

For example, when obtaining the BWD coefficient a ₀ ′,
FBL coefficients a ₀ , a ₁ , and a ₂ are calculated by using TBL
₀₀ , TBL ₀₁ , and TBL ₀₂ are multiplied, and the sum is obtained. Similarly, for the BWD coefficients a ₁ ′ and a ₂ ′, the other calculation tables TBL ₁₀ to TBL ₁₂ , TBL ₂₀ to
Calculate using TBL ₂₂ . BWD determined in this way
_{a 0 ', a 1',} a 2 ' is transferred to the coefficient memories 214 to 216 from the BWD coefficient area by MPU 217.

At this time, the value TBLn in the operation table is for calculating a relative difference between the forward frequency characteristic and the backward frequency characteristic. For example, as shown in FIG.
The frequency characteristics required for the equalization circuit are affected by the characteristics of the magnetic tape and the magnetic head.
It has characteristics like (I) and (II).

The difference between the characteristics of the magnetic tape and the magnetic head uniformly affects the forward frequency characteristics and the reverse frequency characteristics. Therefore, the relative characteristics of the forward and reverse frequency characteristics are constant irrespective of the difference in the characteristics of the magnetic tape and the magnetic head. If this characteristic is replaced with a numerical value in the calculation table, the backward frequency characteristic can be calculated from the forward frequency characteristic.

According to this embodiment, a plurality of frequency characteristics can be compensated with high accuracy with a simple configuration.

Next, a fifth embodiment of the present invention will be described with reference to FIG. For the sake of simplicity, the circuit configuration will be the same as that of the fourth embodiment, and only the program stored in the ROM 218 will be described.

FIG. 23 is an operation flowchart of the fifth embodiment.

The MPU 217 monitors the state of the forward / reverse selection signal FB via the input port 220 (step 1601). When the forward / backward switching is performed, the coefficients a _{0 to} a ₂ are changed. The coefficients are transferred to the FWD coefficient area of the RAM 219, and then the coefficients of the BWD coefficient area are transferred to the coefficient storage circuits 214 to 216 (steps 1602 and 160).
3). On the other hand, when switching from the reverse direction to the forward direction (step 1604), the coefficients a _{0 to} a ₂ are transferred to the BWD coefficient area, and the coefficients in the FWD coefficient area are stored in the coefficient storage circuit 21.
4 to 216 (steps 1605 and 160)
6). If the forward / reverse selection signal FB does not change, the MPU 217 does not perform this processing (step 1604).

As described above, the forward / reverse selection signal FB
Is changed, the coefficient storage circuits 214 to 216 and the coefficient area of the RAM 219 are exchanged depending on the tape running direction. Therefore, in the FWD / BWD coefficient area of the RAM 219, the coefficient after learning corresponding to the tape running direction is stored, and the frequency characteristic of the equalization circuit is determined.

Next, a sixth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

This embodiment is an example in which the same function as that of the equalizer circuit constituted by a program is realized as in the fifth embodiment. Note that, in the same figure, components having the same functions as those in FIG. 17 are denoted by the same reference numerals.

Numerals 203 to 232 denote coefficient setting circuits for selectively outputting each coefficient value depending on the tape running direction. 233 and 236 are selection circuits, 234 and 235 are storage circuits, and 234 is a forward direction, 2
35 stores the coefficient in the reverse direction.

The operation of this embodiment is similar to the operation of the coefficient setting circuit 230-
Since the fourth embodiment is the same as the fourth embodiment except for the H.232, the operation of the coefficient setting circuits 230 to 232 will be described below.

When the forward / reverse selection signal FB indicates the forward direction, the selection circuit 233 outputs a latch clock to the storage circuit 234, and the coefficient input is stored in the storage circuit 234. Further, the selection circuit 236 outputs the coefficient of the storage circuit 234 to the multiplier 208. At this time, the storage circuit 23
The value of 5 holds the previous value because no latch clock is input. Therefore, the adaptive equalization circuit learns so as to correct the frequency characteristic of the reproduced signal in the forward direction, and the finally learned coefficient is stored in the storage circuit 234.

Next, when the forward / reverse selection signal FB changes from the forward direction to the reverse direction, the selection circuit 233 supplies the latch clock to the storage circuit 235.
The 34 coefficient values are saved. The selection circuit 236 outputs the coefficient stored in the storage circuit 235 to the multiplier 208.
Therefore, the adaptive equalization circuit learns using the reproduced signal in the reverse direction and corrects the frequency characteristic.

As described above, the coefficient after learning in the forward direction is stored in the storage circuit 234, and the coefficient after learning in the reverse direction is stored in the storage circuit 235. It operates with the coefficients after learning and corrects the frequency characteristics.

According to this embodiment, the memory (RO) is
M, RAM) are not required, the circuit can be simplified, and the difference in frequency characteristics for each tape running direction can be completely corrected.
Further, the adaptive equalization circuit does not need to learn every time the tape running direction is switched, so that a high-speed operation is possible.

Next, a seventh embodiment of the present invention will be described with reference to FIG.

In the above-described embodiment, the coefficient values input to the respective multipliers are switched according to the tape running direction. However, an adaptive equalizing circuit is provided for each of the forward and backward tape running directions, and the adaptive equalizing circuit is provided depending on the tape running direction. Even when the output of the equalized waveform is selected, it is the same as in the above-described embodiment. FIG. 25 shows the configuration diagram. In the figure, the same components as those in FIG. 17 are denoted by the same reference numerals.

In the figure, reference numerals 240 to 242 denote storage circuits with a clock permission terminal, and 243 denotes an adaptive equalization circuit 20.
Reference numeral 244 denotes an inverting circuit, and 245 is a selecting circuit.

Storage circuit 240 of adaptive equalization circuit 205
２４242 receive the latch clock when the clock enable terminal G is “H” and store the coefficient input, and hold the previous value when the clock enable terminal G is “L”. When the forward / reverse selection signal FB is “H”, the forward direction is “L”, and when the backward direction is the reverse direction, the storage circuits 240 to 242 of the adaptive equalization circuit 205 store the latch clock in the forward direction. Then, the frequency characteristic is corrected by performing the learning described above. At this time,
The adaptive equalization circuit 243 does not operate, and holds each coefficient value.

On the other hand, when the tape running direction is the reverse direction, the adaptive equalizing circuit 243 is operated by the inverting circuit 244, and the correction of the frequency characteristic is learned by receiving the reproduced signal.

As described above, when the tape running direction is the forward direction, the adaptive equalizing circuit 205 operates, and when the tape running direction is the reverse direction, the adaptive equalizing circuit 243 operates. This result is output to the selection circuit 2
45 is selected by a forward / reverse selection signal FB,
This constitutes an equalizing circuit. As described above, in this embodiment, the circuit scale is larger than that of the above embodiment, but the effect is the same.

Next, an eighth embodiment of the present invention will be described with reference to FIG.

In the figure, reference numerals 245 to 247 denote storage circuits, and other symbols are the same as those in FIG. These operations differ only in the initial value of each coefficient given when the tape running direction changes, and the subsequent learning process and the like are the same as in the above-described fourth embodiment.

If the initial value of each coefficient is not changed depending on the tape running direction, and the currently learned coefficient is used as the initial value to learn the opposite tape running direction, the storage circuits 245 to 245 are used.
247 can be realized with a simple configuration as shown in FIG. According to this, the latch 248 stores the coefficient input by the latch clock regardless of the tape running direction, and outputs the coefficient input to the multipliers 280 to 210 as the coefficient output.

For example, as shown in FIG. 28, a case where the tape running direction changes from the forward direction to the reverse direction will be described.

Each of the coefficients a _{0 to} a ₂ receives the reproduced signal in the forward direction and has completed learning, and the coefficient values are (n ₀ ∞, n ₁ ∞,
n ₂ ∞). Next, when the tape running direction is switched from the forward direction to the reverse direction, the immediately preceding coefficient values a _{0 to} a ₂ retain the previous forward coefficient values. Thereafter, with this value as an initial value, a reproduction signal in the reverse direction is received, and each coefficient a _{0 to} a ₂ is changed so as to correct the frequency characteristic. Finally, each coefficient a _{0 to} a ₂ is inverted. It converges to the values of (n ₀ ∞ ″, n ₁ ∞ ″, n ₂ ∞ ″) that determine the frequency characteristics in the direction.

According to this embodiment, the circuit configuration is simple and the number of parts is small, but the learning time when the tape running direction is changed is long.

Thus, a memory circuit suitable for reducing the learning time will be described.

FIG. 29 shows a structure of one embodiment of the storage circuit.

The storage circuits 245 to 247 shown in the figure include a selection circuit 249 for selecting a forward initial value n ₀₀ and a reverse initial value m ₀₀ , and a selection circuit when the forward / reverse selection signal FB changes. 249 is stored as an initial value.
And a presettable latch 250 for learning based on a coefficient input and a latch clock.

In the operation, as shown in FIG. 30, a reproduced signal in the forward direction is received, and each of the coefficients a _{0 to} a ₂ is (n ₀ ∞, n
₁学習, n ₂ ∞), learning has been completed. Next, when the tape running direction is changed in the opposite direction from the forward, selection circuit 249, since the forward / backward select signal FB is reversed direction, selects the reverse initial value m _00. Presettable latch 250 stores this. Accordingly, the coefficients a _{0 to} a ₂ are initialized to (m ₀₀ , m ₁₀ , m ₂₀ ), and thereafter, learning is performed using the reproduction signal in the reverse direction.

[0169] Also, when the tape running direction is changed from the reverse direction in the forward direction to the reverse, the selection circuit 249 outputs the forward initial value n ₀₀ to presettable latch 250, each of the coefficients a ₀ ~a ₂ Is initialized to (n ₀₀ , n ₁₀ , n ₂₀ ) and starts learning.

At this time, the forward initial value and the backward initial value are
The learning time can be reduced by using a value calculated from a frequency characteristic known in advance in the forward direction or the backward direction.

As described above, according to this embodiment, it is possible to suppress an increase in the number of parts and to shorten the learning time.

Next, a ninth embodiment of the present invention will be described with reference to FIG.

In this embodiment, an adaptive equalizing circuit for correcting reproduced signals from a plurality of tracks is simply realized.
For convenience of explanation, it is assumed that the characteristics of the magnetic tape, the magnetic head, and the like between the tracks all change the same.

FIG. 31 shows a configuration diagram of the present embodiment.

In the figure, reference numerals 251 and 252 denote non-recursive digital filters, and the other components are the same as those shown in FIG.

Each magnetic head 2 is arranged in the vertical direction (tape running direction) with respect to the magnetic tape 8, and converts only corresponding magnetic signals from a plurality of tracks into electric signals. This electric signal is sent to the equalization circuit via the AGC 203 and the A / D 204, and the magnetic tape 8 and the magnetic head 1
To correct the frequency characteristics. The equalizing circuit on the first track is the above-described adaptive equalizing circuit 5, and each of the multipliers 208 to 210 has the same value so that the read signal and the expected value are the same.
The coefficients a ₀ ~a ₂ is changed, and finally obtain the coefficients a ₀ ~a ₂ for correcting the frequency characteristic of the magnetic tape 8 and the magnetic head 1.

At this time, since the frequency characteristics of the magnetic tape 8 and each magnetic head 1 are the same, the equalization circuits of the other tracks may be the same as the frequency characteristics of the equalization circuit of the first track. Therefore, the equalizing circuits for the other tracks include the delay circuits 206 and 207 and the multiplier 20 of the adaptive equalizing circuit 205.
The non-recursive digital filters 251 and 252 are composed of 8 to 210 and the adder 211, and the coefficients of the multipliers 208 to 210 use the coefficients a _{0 to} a ₂ of the first track as they are.

Thus, the equalizing circuit for each track has the same frequency characteristic, and the characteristic absorbs the difference in the frequency characteristic of the magnetic tape or the magnetic head.

According to this embodiment, it is not necessary to provide an adaptive equalization circuit for each track, and the circuit scale of the comparator, the coefficient generation circuit, and the storage circuit can be reduced. Further, in the present embodiment, the configuration of the adaptive equalization circuit on the first track has been described using the eighth embodiment, but it goes without saying that the configuration of any embodiment disclosed in the present invention operates similarly. .

The above embodiment is effective when the frequency characteristics of the magnetic tape and the magnetic head between the tracks are all the same or uniform to the extent that they can be neglected. Is large, which can cause problems.

Therefore, a tenth embodiment of the present invention, which is effective in such a case, will be described with reference to FIG.

In the figure, reference numeral 260 denotes a register for storing the coefficient of each track. Other configurations are the same as those in FIG.
7, the same as FIG.

The equalizing circuit 205 for the first track is an adaptive equalizing circuit as shown in the fourth embodiment.
Each of the coefficient values 14 to 216 can be read and written from the MPU 217. This operation is the same as that of the fourth embodiment and will not be described.

On the other hand, the equalization circuit 251 of the other track
This is a configuration in which a register 260 for giving the coefficients of the multipliers 208 to 210 from the MPU 217 to the equalization circuit 251 shown in FIG. 31 is added. As shown in FIG. 33, the register 260 includes a system bus 221 (address bus 221a, data bus 221b, IOWC 221c, IORC 22d).
Via the MPU 217.

In order for the MPU 217 to read the coefficient value of the register 260, the address of the register 260 corresponding to the address bus 221a is output, and the signal path IORC 221d
Activate the signal. The decoder 222 activates the chip select signal CS because the information on the address bus 221a is its own address. AND circuit 2
Reference numeral 25 indicates that the gate circuit 227 is turned off because the chip select signal CS and the IORC 22d are both active.
N, and the gate circuit 227 sends the coefficient output value stored in the storage circuit 226 to the data bus 221b. MP
U217 reads the coefficient value of the register 260 by receiving the coefficient output value on the data bus 221b.

On the other hand, when the MPU 217 writes the coefficient value to the register 260, the address of the register 260 to be written to the address bus 221b and the data bus 2
The coefficient to be written to 21b is output, and the signal of IOWC 221c is activated. By adding a malfunction detection circuit to the register and the adaptive equalization circuit, the reliability of the system can be improved.

Furthermore, since the entire adaptive equalization circuit can be digitized, high integration is possible.

[0188]

According to the present invention as described above,
The equalization circuit can be adapted in response to a change in the characteristics of the data reproducing system, and the adaptation can be easily performed even in the case of a multi-track. Thereby, a read margin is large and data can be reproduced with high reliability.

Further, according to the present invention, an abnormality can be easily detected, and in some embodiments, it can be repaired.

Further, according to the present invention, the equalizing circuit can be appropriately and easily adapted even in the case where the reproducing conditions are different, such as in bidirectional running.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention;

FIG. 2 is a diagram showing a time chart of a peak data interval monitoring circuit suitably used in the embodiment,

FIG. 3 is a graph showing a time change characteristic of a coefficient by adaptive learning;

FIGS. 4A and 4B are explanatory diagrams showing a format of a magnetic tape used in the present embodiment and a coefficient switching signal corresponding thereto.

FIGS. 5A and 5B are explanatory diagrams showing contents recorded in an inter-block gap existing between data blocks on a magnetic tape and a track switching signal corresponding thereto;

FIG. 6 is a block diagram showing a data reproducing device of a magnetic tape device according to a second embodiment of the present invention;

FIG. 7 is a block diagram showing the configuration of a third embodiment of the present invention;

FIG. 8 is a block diagram showing the configuration of a third embodiment of the present invention;

FIGS. 9A and 9B are explanatory diagrams showing a state when an abnormality such as a dropout exists in a data block of a magnetic tape and an IBG area;

FIG. 10 is a block diagram showing a configuration of a fourth embodiment of the present invention;

FIG. 11 is a graph showing a time change characteristic of an equalization error when an abnormality occurs;

FIG. 12 is a block diagram showing the configuration of a fifth embodiment of the present invention;

FIG. 13 is a graph showing a time change characteristic of an equalization error in a normal case;

FIG. 14 is a block diagram showing a configuration of a sixth embodiment of the present invention;

FIG. 15 is a diagram showing a data discrimination input waveform at the time of abnormality.

FIG. 16 shows data discrimination and pointer detection Swiss level;

FIG. 17 is a block diagram showing a configuration of a fourth embodiment of the present invention;

FIG. 18 is a logic circuit diagram showing a configuration of one embodiment of a coefficient storage circuit used in the above embodiment;

FIG. 19 is a waveform chart showing a learning process of a non-recursive filter,

FIG. 20 is a flowchart showing the operation of the MPU used in the fourth embodiment;

FIG. 21 is an explanatory view schematically showing an operation performed by the MPU;

22 (a) and 22 (b) are graphs showing a difference in frequency characteristics during bidirectional running of a magnetic tape,

FIG. 23 is a flowchart showing the operation of the fifth embodiment of the present invention;

FIG. 24 is a block diagram showing a configuration of a sixth embodiment of the present invention;

FIG. 25 is a block diagram showing a configuration of a seventh embodiment of the present invention;

FIG. 26 is a block diagram showing a configuration of an eighth embodiment of the present invention;

FIG. 27 is a block diagram showing a configuration of one embodiment of a storage circuit used in the above embodiment.

FIG. 28 is a time chart showing changes in coefficients when the tape running direction changes from the forward direction to the reverse direction;

FIG. 29 is a block diagram illustrating a configuration of an embodiment of a storage circuit.

FIG. 30 is a time chart showing the operation of the storage circuit;

FIG. 31 is a block diagram showing a configuration of a ninth embodiment of the present invention;

FIG. 32 is a block diagram showing the configuration of a tenth embodiment of the present invention;

FIG. 33 is a logic circuit diagram showing an example of a register used in the embodiment.

FIG. 34 is a flowchart showing a processing operation of the MPU in the embodiment;

FIG. 35 is an explanatory diagram schematically showing an operation performed by the MPU;

FIG. 36 is a block diagram showing a configuration of an eleventh embodiment of the present invention;

FIG. 37 is a flowchart showing a processing operation of the MPU in the embodiment,

FIG. 38 is an explanatory view schematically showing processing executed by the MPU when there is an abnormality in a track;

FIG. 39 is a flowchart showing an operation of a method for restoring a malfunction of the equalization circuit as described above according to a twelfth embodiment of the present invention;

FIG. 40 is an explanatory view schematically showing processing executed by the MPU in the embodiment.

FIG. 41 is a block diagram showing a data reproducing apparatus according to the related art;

FIG. 42 is a block diagram showing a configuration of a conventional reproducing apparatus;

FIG. 43 is a graph showing waveform frequency characteristics.

[Explanation of symbols]

101: magnetic tape, 102: head, 103: preamplifier, 104: differentiation circuit, 105: peak data pulse generation circuit, 106: reference clock circuit, 107: NAN
D circuit, 108 ... peak data monitoring circuit, 109 to 11
0: A / D conversion circuit, 111: subtraction circuit, 112: adaptive equalization circuit, 113: data discrimination circuit, 114: expected value generation circuit, 115: tape format detection circuit, 116
121 to delay circuit, 125 to 129 multiplication circuit, 13
0 to 132: coefficient updating circuit, 134: coefficient switching circuit, 135 to 136 ... feedback coefficient, 137 to 138 ... multiplication circuit, 139 to 140 ... delay circuit, 141 ... addition circuit,
142 addition circuit, 143 delay circuit, 144 OR circuit, 145 pulse monitoring circuit, 146 tone pattern detection circuit, 147 to 150 AND circuit, 151 to 15
2 ... OR circuit, 153-155 ... Expected value.

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. Hei 2-317777 (32) Priority date Hei 2 (1990) November 26 (33) Priority claim country Japan (JP) (72) Inventor Hideki Miyasaka 2880 Kozu, Kodawara-shi, Kanagawa Prefecture, Ltd.Odawara Plant, Hitachi, Ltd. 292, Yoshida-cho, Totsuka-ku, Ltd.Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Kazunori Iwabuchi, 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Japan Microelectronics Device Development Laboratory (Hitachi, Ltd.) 72) Inventor Terumi Takashi Hitachi, Ltd.Micro Corporation 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Electronic Devices Development Laboratory (72) Naoto Matsunami Inventor 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Yokohama, Japan Inside the Microelectronics Devices Development Laboratory, Hitachi, Ltd. (56) References JP-A-59-160807 (JP) , A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G11B 20/10 321

Claims (2)

(57) [Claims] 1. A signal reading circuit for reading a signal from a storage medium.
Path and equalization processing for a read signal from the signal read circuit
And an output of the adaptive equalizer that performs
To generate a first expected value for the identified signal waveform.
A first expected value generation circuit to generate
A file for detecting a predetermined format recorded on a storage medium.
A format detection circuit and an output of the format detection circuit.
Monitoring whether the read signal is periodic based on force
A monitoring circuit, and the read signal monitored by the monitoring circuit;
A second expected value generation circuit for generating a second expected value from
Difference between the output of the adaptive equalization circuit and the first expected value
Is generated, and an adaptive equalization is performed.
Indicating the difference between the output of the conversion circuit and the second expected value
Signal, perform adaptive learning, and
An error detection circuit that feeds back to the equalization circuit;
Based on the output of the
Has a selection circuit to select the error signal for equalization or adaptive learning
Data reproducing apparatus for. 2. The data reproducing apparatus according to claim 1, wherein
Further, the format detection circuit may further include a predetermined format.
When a cut is detected, a value larger than the predetermined feedback amount is
A data reproduction device having a feedback amount conversion circuit for setting .