JP2861925B2 - Ferroelectric memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device, and more particularly to a ferroelectric memory device having a structure in which memory cells including capacitors using ferroelectric materials are arranged.

[0002]

2. Description of the Related Art In recent years, by using a ferroelectric material having a hysteresis characteristic, such as Pb (Zr, Ti) O _3, for a memory cell, a nonvolatile memory having a function of retaining data even when power is turned off has been developed. Has been realized. An example of such a ferroelectric memory device is disclosed in JP-A-63-2019.
No. 98, JP-A-1-158691, 1994
International Conference on Solid-State Circuits (February 1998)
nal Solid-State Circuits
Conference. ISSCC) Proceedings 268 pages.

Next, a memory cell used in this ferroelectric memory device includes one switching transistor and a ferroelectric capacitor in which electrodes are attached to both surfaces of the ferroelectric (hereinafter, 1T /). The characteristics and operation of the memory cell will be described in the case of using a 1C type memory cell.

FIG. 29 is a circuit diagram using 1T / 1C type memory cells. The memory cell MC includes a switching transistor Tr and one electrode connected to the transistor Tr.
And a ferroelectric capacitor C connected to one of the source and the drain of the transistor Tr. The other electrode of the ferroelectric capacitor C is connected to the plate line PL, and the gate of the transistor Tr is Those connected to the word line WL and not connected to the ferroelectric capacitor C among the sources and drains of the transistor Tr are connected to the bit line BL.

The characteristics (polarization characteristics) of the polarization amount p with respect to the voltage V between both electrodes of the ferroelectric capacitor C in the memory cell MC are shown in FIGS. 30A and 30B. FIG. 30 (A),
As shown in (B), the ferroelectric capacitor C shows a hysteresis characteristic with respect to the voltage V between both electrodes, and the voltage V = 0
The binary information is stored according to the difference (points a and e) of the polarization amount P when For example, the point a is made to correspond to one data “1” of the binary information, and the point e is made to correspond to the other data “0” (the following description assumes this correspondence).

The word line WL is set to high level to turn on the transistor Tr, and the bit line BL and the plate line P
When a voltage at which the voltage V between both electrodes of the ferroelectric capacitor C becomes −Ve is applied between L, the polarization amount p changes from a → b → c → d at data “1” (point a), Charge Q1 corresponding to this change is obtained via bit line BL (FIG. 30).
(A)). At data “0” (point e), the polarization amount P is e
→ d, and a charge Q0 corresponding to this change is obtained via the bit line BL (FIG. 30B).

In this manner, data is read from and written to the memory cell MC. As is apparent from this operation, Q
The charge amount corresponding to 1-Q0, that is, twice (2Pr) of the remanent polarization (Pr) of the ferroelectric substance, is a read margin for data "1" and "0".

FIG. 31 shows an example of a conventional ferroelectric memory device in which such memory cells MC are arranged. This ferroelectric memory device includes a memory cell array 1 and a control signal X.
A plate line voltage generating circuit 7 for applying a plate line voltage Vp to the plate line PL at a predetermined timing according to C;
A word line selection control circuit 6 for setting one of the word lines WL1 to WLm to a selection level at a predetermined timing in accordance with an external address signal ADx and a control signal XC, and a bit line BL11 to B in accordance with a discharge control signal BLDC.
A bit line discharge circuit 2 for setting Lm2 to a ground voltage at a predetermined timing, and a reference voltage for a bit line paired with a bit line connected to a selected memory cell at a predetermined timing according to reference potential generation control signals RLC1 and RLC2. Amplifying and outputting read data transmitted between a pair of first and second bit lines (for example, between BL11 and BL12) activated in accordance with a sense amplification control signal SAC and a reference potential generation circuit 3 for supplying A plurality of sense amplifiers 4 for supplying write data to a pair of first and second bit lines; a bit line discharge circuit 2, a reference potential generating circuit 3, and a sense amplifier 4 in accordance with a control signal word XC
And a sense amplifier control circuit 5 that performs the above control.

The memory cell array 1 includes a plurality of 1T / 1C memory cells MC1 arranged in a row direction and a column direction.
1 to MCnm and memory cells MC11 to MC for each column.
and a pair of first and second bit lines BL1 connected to the source or drain of a transistor Tr of nm and transmitting write data and read data of these memory cells.
1, BL12 to BLml, BLm2 and the transistors T for each row of the plurality of memory cells MC11 to MCnm.
a plurality of word lines WL1 to WLm which are connected to the gate of the memory cell r to select the memory cells and the corresponding bit lines when the memory cells are at the selected level, and the memory cells MC11 to MCm
and a plate line PL connected to one electrode of the n ferroelectric capacitors C.

Next, the read operation of the ferroelectric memory device shown in FIG. 31 will be described with reference to the voltage waveform diagram of each part shown in FIG. 32 and the diagram showing the polarization state of the memory cell MC11. . First, in the period T1, the discharge of the bit lines BL11 to BLm2 is released by setting the discharge control signal BLDC to low level. Next, in a period T2, the word line WL1 and the plate line PL are each raised to a high level to change the polarization state of the memory cell MC11, and a charge corresponding to data stored in the memory cell MC11 is output to the bit line BL11.

In the figure, data "1" is stored in the memory cell MC11.
Is stored, but when data "0" is stored, the polarization is performed in the opposite direction.

Also, the reference potential generation control signal RLC2 is raised to a high level, and the bit line B
L12 is set to the reference voltage. Thereafter, in a period T3, the sense amplifier control signal SAC is set to a high level to activate the sense amplifier 4 of the differential amplifier circuit,
The difference voltage between the paired bit lines BL11 and BL12 is sense-amplified. In this way, it is determined whether the data stored in the memory cell MC11 is “1” or “0”.

Thereafter, in a period T4, the plate line P
Let L be a low level. In the next period T5, the sense amplifier control signal SAC is set to low level to deactivate the sense amplifier 4, and further, the discharge control signal BLDC is set to high level, and the level of the bit line BL11 is set to the ground voltage.

By doing so, the memory cell MC11
Of the ferroelectric capacitor C can be returned to the state of the period T1 before data reading. Finally, the word line W
L1 is lowered to a low level, the transistor Tr of the memory cell MC11 is turned off, and the read operation of the memory cell MC11 is completed.

[0015]

SUMMARY OF THE INVENTION However, MOS
With the demand from the scaling law of the transistor and the lowering of the voltage of the processor for transmitting data to and from the ferroelectric memory device, it is necessary to lower the operating voltage of the ferroelectric memory device. Further, in order to realize a highly integrated ferroelectric memory device, it is necessary to reduce the memory cell size. For that purpose, it is necessary to reduce the size of the ferroelectric capacitor.

However, the polarization of the ferroelectric depends on the size of the capacitor, and when the size is reduced, the voltage dependence of the polarization is significantly deteriorated. FIG. 33 shows SrBi ₂ Ta ₂₀ as a ferroelectric substance.
₉ is a graph in which the measured value of 2Pr is plotted against applied voltage for ferroelectric pairs of different sizes when using No. 9;

As shown in the figure, particularly when the capacitance size is 3 μm square or less, the polarization value when a low voltage of 3 V or less is applied decreases. As described in the description of the operation method, the difference between the charges output from the memory cell to the bit line in the case of data "1" and "0" corresponds to 2Pr, so that when 2Pr decreases, the read margin decreases. . In severe cases, sense amplification cannot be performed, so that the number of defective cells increases and the yield decreases.

An object of the present invention is to improve the polarization characteristics when a low voltage is applied to a ferroelectric capacitor having a fine size, to operate at a low voltage, and to obtain a highly integrated ferroelectric memory with a good yield. It is to provide a device.

[0019]

In order to achieve the above object, a ferroelectric memory device according to the present invention has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines. In a ferroelectric memory device, the memory cell array includes a plurality of memory cells arranged in a matrix in a row direction and a column direction. Each memory cell includes at least one switching transistor and one electrode. And a combination of at least one ferroelectric capacitor connected to one of a source and a drain of the transistor, wherein the plurality of word lines are gates of switching transistors in a column direction of the memory cell array. And the plurality of bit lines are used for switching in a row direction of the memory cell array. A source or a drain of the transistor, which is connected to the ferroelectric capacitor not connected thereto, wherein the plurality of plate lines are connected to the other electrode of the ferroelectric capacitor of each of the memory cells; A constant voltage is applied to the ferroelectric capacitor to
The information of "0" and "1" is obtained by polarizing the dielectric.
Polarization reversal when a constant voltage is applied again
Of discriminating "0" and "1" information depending on the presence or absence of
The highest applied during the operation.
Excitation voltage having a voltage value higher than the
The pre-application of the amount increases the polarization of the ferroelectric.
It was a thing .

[0020]

[0021]

[0022] The all memory cells, when the test signal inputted to the ferroelectric memory device of the first level, between the ferroelectric capacitance of the electrode, which the excitation voltage is applied It is.

Further test signal from the outside is input to the ferroelectric memory device, when the test signal is in the first level, the plurality of all the bit lines, the voltage is held at the ground voltage, the All of the plurality of plate lines are maintained at a voltage higher than the bit line by the voltage value of the excitation voltage , and the plurality of word lines are alternately switched within the test signal input period. Thus, the voltage is held at the operating voltage of each transistor.

Further test signal from the outside is input to the ferroelectric memory device, when the test signal of the first level, the plurality of all the plate lines, the voltage is held at the ground voltage, the plurality All bit lines are held at a voltage higher than the plate line by the voltage value of the excitation voltage , and the plurality of word lines are alternately switched within the test signal input period. It is held at the operating voltage of each transistor.

Also, the apparatus has an internal address generation circuit, an address switching circuit, and an X decoder circuit. When the test signal is at the first level, an address signal from the internal address generation circuit is passed through the address switching circuit. The word lines are alternately switched within an input period of the test signal based on a signal inputted to the X decoder circuit and decoded by the X decoder circuit.

Also, the apparatus has an internal address generating circuit, an address switching circuit, and an X decoder circuit. When the test signal is at the first level, an address signal from the internal address generating circuit is passed through the address switching circuit. And input to the X decoder circuit, and simultaneously switch the plurality of word lines within the test signal input period based on the signal decoded by the X decoder circuit.

Further the memory cell, when the test signal inputted to the ferroelectric memory device of the first level, between the electrodes of any of the ferroelectric capacitor is selected, the excitation voltage is applied Things.

The test signal from the outside to the ferroelectric memory device is input, when the test signal is in the first level, the plurality of all the bit lines, the voltage is held at the ground voltage, the plurality All the plate lines are held at a voltage higher than the bit line by the voltage value of the excitation voltage , and the switching transistors connected to the ferroelectric capacitors are arbitrarily selected and turned on. Things.

When a test signal is input from the outside to the ferroelectric memory device and the test signal is at the first level,
The voltage of all of the plurality of plate lines is maintained at a ground voltage, and the voltage of all of the plurality of bit lines is maintained at a voltage higher than the plate line by the voltage value of the high voltage. The switching transistor connected to the ferroelectric capacitor is arbitrarily selected and turned on.

An address buffer circuit and an X decoder circuit are provided, and when the test signal is at the first level, an address signal input from the outside to the ferroelectric memory device via the address buffer circuit. A word line is selected according to a signal input to the X decoder circuit and decoded by the X decoder circuit, and a switching transistor connected to the ferroelectric capacitor is arbitrarily selected and turned on.

A dummy cell, a plurality of dummy word lines, a plurality of dummy plate lines, a reference potential generating circuit,
A dummy transistor, comprising: a switching transistor connected to the plurality of bit lines; and electrodes attached to both surfaces of the ferroelectric, and one of the electrodes is connected to one of a source and a drain of the transistor. And a plurality of dummy word lines connected to the gates of the transistors of the plurality of dummy cells and connected to a ferroelectric memory device. When the test signal to be supplied is at a first level, the transistor is turned on. The dummy plate line is connected to the other electrode of the ferroelectric capacitors of the plurality of dummy cells, and generates a reference potential. The circuit generates a reference voltage during the sensing operation, and the sense amplifier control circuit controls the reference potential generation circuit In addition, all of the dummy cells have the reference voltage applied between both electrodes of the ferroelectric capacitor when the test signal input to the ferroelectric memory device is at the first level. is there.

Further, when the test signal inputted to the ferroelectric memory device of the first level, the plurality of all the bit lines, the voltage is held at the ground voltage, the dummy plate line, the The voltage is maintained at a voltage higher than the bit line by the voltage value of the excitation voltage , and the plurality of dummy word lines are alternately switched within the test signal input period to operate the dummy cell transistor. Is held in the

Further, when the test signal inputted to the ferroelectric memory device of the first level, the dummy plate line, the voltage is held at the ground voltage, the plurality of all the bit lines, the The voltage is maintained at a voltage higher than the dummy plate line by the voltage value of the excitation voltage , and the plurality of dummy word lines are alternately switched within the test signal input period to operate the dummy cell transistor. It is held at voltage.

[0034]

The voltage applied to the ferroelectric capacitor (the voltage VCC in FIG. 1B) (FIG. 1B) is higher than the voltage (FIG. 1B) applied to the ferroelectric capacitor at the time of memory operation before the memory contents are stored, for example, in the memory manufacturing stage. ) Is applied to the ferroelectric capacitor in advance. Further, during a test period (T8 in FIG. 7) performed for shipment from the factory, the high voltage Vex is applied to the ferroelectric capacitor.

By applying a high voltage Vex to the ferroelectric capacitor, the domains of the ferroelectric capacitor can be rearranged. Therefore, the domain in which the domain inversion is inhibited due to an increase in defects in the ferroelectric capacitor due to the size reduction or the like can be domain-inverted by rearrangement. Due to such an effect, the polarization characteristics when a low voltage is applied to a ferroelectric capacitor having a smaller size are improved. After the polarization characteristics have been improved, an operation of storing the memory contents is performed, and the memory device is used as a memory device.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to the figure, a ferroelectric memory device according to the present invention has a memory cell array 1, a plurality of word lines WL (WL1, WL2... WLn) and a plurality of bit lines BL (BL11, BL11, BL12 ... BLm2)
And a plurality of plate lines PL.

The memory cell array 1 is arranged in the row direction (MC1
1, MC21, ..., MCn1, ..., MC1m, MC2m ...
MCnm) and column direction (MC11,... MC1m, MC21)
.. MC2m,..., MCn1... MCnm). Each memory cell has at least one switching transistor Tr and electrodes attached to both sides of a ferroelectric material. It comprises a combination with at least one ferroelectric capacitor C whose one electrode is connected to one of the source and the drain of the transistor Tr.

A plurality of word lines WL (WL1, WL2...)
WLn) is connected to the gate of the switching transistor Tr in the column direction of the memory cell array 1. The plurality of bit lines BL (BL1, BL2... BLn)
The ferroelectric capacitor C of the source or the drain of the switching transistor Tr in the row direction of the memory cell array 1
Is connected to something that is not connected. The plurality of plate lines PL are connected to the ferroelectric capacitors C of each memory cell MC.
Is connected to the other electrode.

Further, in the ferroelectric capacitor C, a high voltage is applied in advance between the two electrodes to increase the polarization of the ferroelectric. The improvement of the polarization characteristics is performed in a stage before storing the memory contents, for example, in a manufacturing stage of the memory, or in a test period performed for shipment from a factory.

Then, after the above-mentioned polarization characteristics have been improved, the operation of storing the memory contents is performed, and the memory device is used as a memory device.

(Embodiment 1) Next, a specific example of the present invention is shown in FIG.
This will be described with reference to the embodiment shown in FIG. FIG. 1 (a)
FIG. 2 is a circuit diagram illustrating a memory cell of the ferroelectric memory device according to the first embodiment of the present invention, and FIG. 2B is a voltage waveform diagram illustrating an operation according to the first embodiment of the present invention.

The memory cell MC used in the ferroelectric memory device according to the first embodiment of the present invention shown in FIG. 1A is composed of one switching transistor Tr and one ferroelectric ferroelectric capacitor C. Composed of combinations. The ferroelectric capacitor C has a structure in which the ferroelectric is sandwiched between two electrodes, one of which is connected to the source of the transistor Tr, and the other electrode is connected to the plate line PL.

The word line WL is connected to the gate of the transistor Tr of the memory cell MC.
L is connected to one of the drains of the transistor Tr. In FIG. 1, the ferroelectric capacitor C is connected to the source of the transistor Tr, and the bit line BL is connected to the drain of the transistor Tr. However, the connection may be reversed.

The memory cell MC shown in FIG.
, MCn, MC21,... MCn
1,..., MC1m, MC2m... MCnm) and the column direction (MC11,... MC1m, MC21... MC2m,.
Cn1... MCnm) to form a memory cell array 1.

The plurality of word lines WL1 and WLn are
The memory cells MC (MC11 ... MC1) arranged in the column direction
, MCn1,..., MCnm) are commonly connected to the gates of the transistors Tr. The plurality of bit lines BL11... BLm2 are connected to the memory cells M arranged in the row direction.
C (MC11... MCn1,..., MC1m... MCnm) are commonly connected to the drain (or source) of the transistor Tr.

The plurality of plate lines PL are connected to memory cells MC (MC11... MC1m,.
(Cn1... MCnm) are commonly connected to the other electrode of the ferroelectric capacitor C connected to the source (or drain) of the transistor Tr.

Further, a voltage higher than the voltage applied during the memory operation is applied between both electrodes of the ferroelectric capacitor C of each memory cell MC in a stage before storing the memory contents, for example, in a memory manufacturing stage. Excites the polarization of the ferroelectric, thereby increasing the polarization of the ferroelectric.

That is, as shown in FIG. 1B, in the first embodiment of the present invention, the bit line BL connected to the memory cell MC shown in FIG.
When the word line WL of C is set to the high level, the memory cell MC
Is turned on, and the voltage of the memory cell MC plate line PL is set to the voltage Vex which is higher than the voltage VCC which is the high level of the normal plate line PL. During a period in which the transistor Tr of the MC is turned on, a voltage Vex higher than the voltage VCC during normal operation is applied between both electrodes of the ferroelectric capacitor C in advance.

Here, the inventor of the present invention has found that the polarization of the ferroelectric used for the ferroelectric capacitor C is such that when the capacitance size is reduced, the voltage dependency is significantly deteriorated.
Based on this knowledge, the voltage higher than the operating voltage during memory operation during the manufacture of a ferroelectric memory device, specifically, the highest voltage applied between both electrodes of the ferroelectric capacitor during the operation of the memory cell Apply a high voltage to the ferroelectric capacitor in advance,
Excite polarization. That is, for example, a ferroelectric memory device that operates at a voltage of 3 V performs polarization inversion of the ferroelectric at a voltage of 5 V. As described above, by performing the polarization inversion on the ferroelectric substance of the ferroelectric capacitor in advance at the high voltage Vex (Vex> VCC), the polarization when a voltage of 3 V is applied can be greatly increased.

(Embodiment 2) FIG. 2 is a voltage waveform diagram showing Embodiment 2 of the present invention. Although the ferroelectric memory device used in the present embodiment has the same configuration as that of FIG. 1A, the present embodiment differs from the first embodiment in that the voltage of the bit line BL is changed to the high level of the normal bit line BL. High voltage Vex higher than the voltage VCC of the plate line PL.
At the ground voltage. Therefore, during the period in which the transistor Tr of the memory cell MC is on, a high voltage having a polarity opposite to that of the first embodiment is applied between the electrodes of the ferroelectric capacitor C. It should be noted that the first and second embodiments may be combined to change the polarity between the electrodes of the ferroelectric capacitor C and apply a voltage to excite the polarization. Further, an operation of changing the polarity and applying a voltage may be used. May be repeated a plurality of times.

(Embodiment 3) FIG. 3 is a circuit diagram showing a specific circuit configuration for driving a ferroelectric memory device configured using memory cells according to Embodiments 1 and 2 of the present invention.

In FIG. 3, in addition to the memory cell array 1 in which the memory cells MC of FIG. 1A are arranged in a matrix, a plate line voltage Vp is applied to the plate line PL at a predetermined timing according to the control signal XC. A plate line potential generation circuit 7, a word line selection control circuit 6 for setting one of the word lines WL1 to WLm to a selection level at a predetermined timing according to an external address signal ADx and a control signal XC, and a bit according to a discharge control signal BLDC. A bit line discharge circuit 2 for setting lines BL11-BLm2 to a ground voltage at a predetermined timing, and a predetermined timing according to reference potential generation control signals RLC1, RLC2 for a bit line paired with a bit line connected to a selected memory cell. Reference voltage generating circuit 3 for supplying a reference voltage at
Between the first and second bit lines which are activated in accordance with the sense amplification control signal SAC (for example, BL11, BL1
Amplify and output the read data transmitted between
A plurality of sense amplifiers 4 for supplying write data to a pair of first and second bit lines; a bit line discharge circuit 2, a reference potential generation circuit 3,
A sense amplifier control circuit 5 for controlling the sense amplifier 4.

In the embodiment shown in FIG. 3, the polarization characteristics of the ferroelectric capacitor of the ferroelectric capacitor are improved during a drive test period or the like performed when the ferroelectric memory device is shipped from the factory. . That is, the voltage applied from the sense amplifier control circuit 5 to the bit line discharge circuit 2 is set to Vex which is higher than the voltage VCC in the case shown in FIG. Is set to Vex which is a voltage higher than the voltage VCC in the case shown in FIG. 31, and writing of data "0" or "1" is performed for each memory cell MC.
Do for By performing such an operation, a voltage higher than the normal operation voltage VCC is applied to the ferroelectric capacitor C of the memory cell MC in which the data “1” or “0” has been written. High voltage Vex across ferroelectric capacitor C
Is applied, the domains of the ferroelectric capacitor C can be rearranged. Therefore, the domain in which the domain inversion is inhibited due to an increase in defects in the ferroelectric capacitor due to the size reduction or the like can be domain-inverted by rearrangement.
Due to such an effect, the polarization characteristics when a low voltage is applied to the ferroelectric capacitor C having a smaller size are improved. After the polarization characteristics have been improved, an operation of storing the memory contents is performed, and the memory device is used as a memory device.

FIG. 4 is obtained by adding a voltage conversion circuit 20 to the circuit configuration of FIG. In FIG. 3, since the normal voltage VCC is changed to the high voltage Vex and applied to all the circuits, the high voltage Vex is limited to the upper limit at which all the circuits operate. However, if the voltage conversion circuit 20 is provided as shown in FIG. 4, the high voltage Vex is applied only to the plate line PL or the bit line BL, and the other circuits can be operated by inputting the normal voltage VCC. it can.

(Embodiment 4) FIG. 5A is a circuit diagram showing a memory cell used in a ferroelectric memory device according to Embodiment 4 of the present invention, and FIG. 5B is a voltage waveform diagram.

The memory cell MC shown in FIG. 5A comprises a combination of two transistors Tr1 and Tr2 and two ferroelectric capacitors C1 and C2.

The gates of the two transistors Tr1 and Tr2 are commonly connected to a word line WL, and the drain (or source) of one transistor Tr1 is connected to a bit line BL1.
The drain (or source) of the other transistor Tr2 is connected to the bit line BL2. The sources (or drains) of the transistors Tr1 and Tr2 are:
One electrode of the ferroelectric capacitors C1 and C2 is connected, and the other electrode of the ferroelectric capacitors C1 and C2 is commonly connected to the plate line PL.

As shown in FIG. 5B, the voltage of the plate line PL is set to a high voltage Vex higher than the normal voltage VCC, the voltages of the bit lines BL1 and BL2 are held at the ground voltage, and the transistors Tr1 and Tr2 Is turned on, a high voltage Vex is applied to the two ferroelectric capacitors C1 and C2. Therefore, the same effect as in the first embodiment can be obtained. Note that, similarly to the second embodiment, the application direction of the high voltage can be reversed.

In the first and second embodiments, a memory cell is formed by combining one or two transistors and a ferroelectric capacitor. However, the number of transistors and ferroelectric capacitors is not limited to this. is not.

(Embodiment 5) FIG. 6 shows Embodiment 5 of the present invention.
FIG. This embodiment is different from the conventional ferroelectric memory device shown in FIG. 31 in that a test signal TEST input from the outside to the ferroelectric memory device is the first signal.
Level (high level), all the memory cells M
The point is that a high voltage Vex which is higher than the voltage VCC applied to the ferroelectric capacitor C during the memory operation is applied between the electrodes of the ferroelectric capacitor C of C11 to MCnm. By doing so, the operations described in the first and second embodiments can be performed at high speed for all the memory cells.

In FIG. 6, the test signal TEST is input to the sense amplifier control circuit 5, the word line selection control circuit 6, and the plate line potential generation circuit 7, and this point is shown in FIG.
Circuit example. FIG. 7 shows an example of operation waveform timing of the circuit shown in FIG.

In FIG. 7, the period T8 is outside the test period, and the periods T7 and T9 are outside the test period. Hereinafter, bit line B
The operations of the three signal lines L11 to BLm2, word lines WL1 to WLn, and plate line PL will be described individually. First, the operation of the bit lines BL11 to BLm2 will be described. In the test period T8, the test signal TEST
Becomes high level (first level), the discharge control signal BLDC becomes high level, and the sense amplifier 4 is deactivated.

FIG. 8 shows a circuit example of the sense amplifier 4. In FIG. 8, the non-inverted output signal SAP of the sense amplification control signal SAC and the inverted output signal SAN obtained by inverting the sense amplification control signal SAC have one of the source and the drain of the N- and P-channel transistors, respectively. Lines BLj11 to BLjm1 and those not connected to BLj12 to BLjm2). The operation waveforms of the bit line discharge circuit 2 and the sense amplifier 4 shown in FIG. 8 are as shown in FIG.
Lm1 and BLm2 are discharged to the ground voltage in the test period T8.

Next, the operation of word lines WL1 to WLn will be described. In the example of FIG. 7, the word lines WL1 to WLn
Are alternately selected only once in the test period T8 and are held at the operating voltage of the transistor Tr. In the fifth embodiment, the voltage (the operating voltage of the transistor Tr) at which the word lines WL1 to WLn are held is changed to the high voltage V
BOOT (VBOOT> VCC) is set. FIG.
0 shows an example of the word line selection control circuit 6 for realizing the operation waveforms of the word lines WL1 to WLn in FIG. The word line selection control circuit 6 includes an X control circuit 8, an address buffer circuit 9, an internal address generation circuit 10, (k + 1) address switching circuits 11, and an X decoder circuit 12.

In FIG. 10, ADC is a control signal for controlling the address buffer circuit 9, IADC is a control signal for controlling the internal address generation circuit 10, ADSWC is a control signal for controlling the address switching circuit 11, XDC is a control signal for controlling the X decoder circuit 12, EXAi (i = 0 to k) is an address buffer output signal, IXAi (i = 0 to k) is an internal address signal, TXAi, NXAi (i = 0 to k). )
These are an address non-inversion output signal and an address inversion output signal, respectively.

FIGS. 11, 12, 13, and 14 show examples of the address buffer circuit 9, the internal address generation circuit 10, the address switching circuit 11, and the X decoder circuit 12.
Hereinafter, the operation of the word line selection control circuit 6 in this example will be described with reference to FIG.

In the test period T8 shown in FIG. 15, the address buffer circuit control signal ADC goes low.
At this time, as apparent from the configuration of FIG. 11, the address buffer circuit 9 is inactivated. The test period T
8, the internal address generation circuit control signal I
The ADC goes high. At this time, as is apparent from the configuration of FIG. 12, the waveform of IXAi (i = 0 to k), which is the output signal from the plurality of binary counters 13, is shown in FIG.
As shown in FIG. 5, the waveform is alternately switched and sequentially output.

In the test period T8, the address switching circuit control signal ADSWC goes high. At this time, the (k + 1) address switching circuits 11 select the internal address signals IXAi (i = 0 to k) as output signals, as is apparent from the configuration of FIG.

In the test period T8, the X decoder circuit control signal XDC is at a high level. At this time, the X decoder circuit 12 shown in FIG. 14 is activated, the level of the voltage VCC is converted to the level of the voltage VBOOT by the internal level conversion circuit 14, the input address is decoded, and the level of the voltage VBOOT is changed. Is output.

As a result, as shown in FIG. 15, during the test period T8, when the test signal is at the first level, that is, at the high level, the address signal from the internal address generation circuit 10 is transmitted through the address switching circuit 11. The word lines WL1 to WLn are alternately switched within a test signal input period based on a signal input to the X decoder circuit 12 and decoded by the X decoder circuit 12.

Finally, the operation of the plate line PL will be described with reference to the circuit example of FIG. 16 and the waveform timing chart of FIG. FIG. 16 is an example of the plate line potential generation circuit 7. In FIG. 16, the plate line potential generation circuit 7
It comprises a system control circuit 15, a potential switching circuit 16, and a plate line driving circuit 17. In FIG. 16, VSW denotes an output level of the potential switching circuit 16, and control signals PLC1 to PLC
Reference numeral 4 denotes an output signal of the X control circuit 15, and the control signal PL
C1 to PLC3 are used for controlling the potential switching circuit 16, and the control signal PLC4 is used for controlling the plate line driving circuit 17, respectively. In the test period T8, the control signal PLC
1 and PL2 become low level and control signals PL3 and PL
C4 is at a high level. At this time, the potential switching circuit 16
Output level VSW is high voltage Vex (Vex> VCC)
And the level of the voltage Vp of the plate line PL is
It is at the level of the high voltage Vex. As a result, the operation waveform shown in FIG. 7 is realized.

Next, another example of operation waveform timing of the circuit shown in FIG. 6 is shown in FIG. This example is different from the timing example of FIG. 7 in that the levels of the word lines WL1 to WLn are always set to the voltage VBOOT level in the test period T8. FIG. 19 shows an example of the X decoder circuit 12 for realizing the operation waveforms of FIG. In the test period T8,
When the test signal TEST goes high, the word line W
A low level is input to each NAND gate that outputs L1 to WLn. As a result, the voltage levels of word lines WL1 to WLn attain the level of voltage VBOOT.

(Embodiment 6) FIG. 20 is a circuit diagram showing Embodiment 6 of the present invention. In the present embodiment, the polarity of the voltage applied between the electrodes of the ferroelectric capacitors C of the memory cells MC11 to MCnm is opposite to that of the fifth embodiment. 20, the bit line charge circuit 18 is added to the circuit shown in FIG. 5, and the X decoder circuit 12 shown in FIG. 13 is modified. FIG. 21 shows an X decoder circuit 12 according to the fifth embodiment. FIG. 22 shows an internal waveform of the circuit shown in FIG.

In the circuit of FIG. 21, the power supply of the last-stage inverter is at voltage VBOOT2, and level conversion circuit 13 converts the level of voltage VCC to the level of voltage VBOOT2. Assuming that the threshold voltage of the transistor Tr of each of the memory cells MC11 to MCnm is Vm, there is a relationship of VBOOT> Vex + Vtn between the level of the voltage VBOOT2 and the level of the voltage VCC, and the strength of the memory cells MC11 to MCnm is high. A high voltage Vex (Vex> VCC) can be applied to the dielectric capacitor C.

(Embodiment 7) Next, Embodiment 7 of the present invention
Will be described. In the present embodiment, unlike the fifth and sixth embodiments, the voltage Vex is applied between the electrodes of the ferroelectric capacitors C of the arbitrary memory cells MC11 to MCnm during the test period T8 using the external address signal ADx. It is made possible. FIG. 23 shows an example of operation waveform timing of a circuit for realizing the present embodiment.

In the test period T8, the address switching circuit control signal ADSWC goes low. At this time,
(K + 1) address switching circuits 10 shown in FIG.
Is an address buffer output signal EXA as an output signal.
Select i (i = 0 to k). By doing this,
The word line selected according to the external address signal ADx is set to the voltage VBOOT level, and a voltage can be applied between the electrodes of the ferroelectric capacitor C of any memory cell.

In this embodiment, as in Embodiments 5 and 6,
There are two possible polarities of the voltage Vex applied between the electrodes of the ferroelectric capacitor C, and the circuit configuration for realizing it is the same as in the fifth and sixth embodiments.

(Eighth Embodiment) FIG. 24 is a circuit diagram showing an eighth embodiment of the present invention. In the embodiment shown in FIG.
A reference potential generating circuit 3, a dummy cell DC provided on the output side of the reference potential generating circuit 3, and a plurality of dummy word lines DWL.
Further, it has a plurality of dummy plate lines DPL, a sense amplifier control circuit 5, and a transfer gate circuit 19.

The dummy cell DC is connected to the plurality of bit lines B
At least one switching transistor T connected to L11 and BL12 to BLm1 and BLm2 and electrodes attached to both sides of the ferroelectric material, and one electrode connected to one of the source and drain of the transistor T And one ferroelectric capacitor C. Further, the plurality of dummy word lines DWL are connected to the gates of the transistors T of the plurality of dummy cells DC, and arbitrarily select the transistors T when the test signal input to the ferroelectric memory device is at the first level. The dummy plate line DPL is connected to the other electrode of the ferroelectric capacitor C of the plurality of dummy cells DC. The reference potential generating circuit 3 generates a reference voltage during a sensing operation. Sense amplifier control circuit 5
Controls the reference potential generating circuit 3. All the dummy cells DC are connected to both electrodes of the ferroelectric capacitor C when the test signal input to the ferroelectric memory device is at the first level. In the meantime, the reference voltage is applied.

In FIG. 24, DTG1 and DTG2 are transfer gate control signals, PDC is a dummy cell precharge control signal, DWL is a dummy word line, and DPL is a dummy plate line. The reference potential generating circuit 3 uses two dummy cells each including a ferroelectric capacitor C.

In the present embodiment, as shown in FIG. 24, when a ferroelectric capacitor C is used as a dummy cell, like the first to sixth embodiments, a memory operation is performed between the electrodes of the ferroelectric capacitor C. Voltage Vex higher than applied voltage VCC
It is characterized in that a test mode for applying the FIG. 25 shows an example of operation waveform timing according to the eighth embodiment of the present invention. In the test period T8, the bit lines BL11 and BLM2 are discharged to the ground voltage,
The voltage level of dummy plate line DPL becomes the level of voltage Vex, and the voltage level of dummy word line DWL becomes the level of voltage VBOOT. Thus, the voltage Vex can be applied between the ferroelectric capacitors of the dummy cells. In FIG. 25, dummy plate line DPL
Although the high voltage is applied to the side, it is also possible to apply the opposite polarity to the ferroelectric capacitor C, and the circuit configuration for realizing it is the same as that of the fifth embodiment.

(Embodiment) In Embodiment 1 of the present invention, FIG.
As the ferroelectric capacitance C of the memory cell shown in FIG.
rBi was used fitted with electrodes on both surfaces are processed to a size of 2μm square with ₂ Ta ₂ 0 ₉ ferroelectric. FIG.
FIG. 5 is a diagram illustrating a hysteresis curve when the ferroelectric capacitor C is operated at a voltage of 2 V and a hysteresis curve after applying a voltage of 5 V as the voltage Vex described in the first embodiment. 2Pr at the time of 2V operation before application of the high voltage Vex is very small, and the read margin is very small. However, 2pr after the application of the voltage of 5V is greatly increased, and data "1" and "0" are not read. The read margin has greatly increased.

[0084] As Example 2, a ferroelectric capacitor C of the memory cell shown in FIG. 1 (a), the electrodes on both surfaces are processed to a size of 3μm angle using SrBi ₂ Tr ₂ 0 ₉ ferroelectric Was used. FIG. 27A shows a high voltage Ve.
(b) shows the frequency distribution of the amount of charge read to the bit line BL at the time of 3V operation after applying 5V as the high voltage Vex before applying x. Although the charge amount for reading data “0” does not change significantly by applying the voltage Vex,
Variations in the amount of charge read for both data "0" and "1" are reduced, and the reliability is improved.

Embodiment 3 will be described with reference to FIG. FIG.
8 is a frequency distribution of the difference between the read charge amounts of the data “1” and “0” when the memory cell shown in the first embodiment is operated at a voltage of 3V. By applying the high voltage Vex, the signal charge amount of the defective cell increased until it became readable. Therefore, defective memory cells at the time of chip selection can be relieved.

[0086] The above ferroelectric ferroelectric capacitive as an embodiment of the present invention has been described an example using SrBi ₂ Ta ₂ 0 _9,
The present invention can be applied to the case where another ferroelectric such as Pb (Zr, Ti) O ₃ is used.

[0087]

As described above, according to the present invention, the polarization of the ferroelectric capacitor at a low voltage is greatly increased, and the signal voltage at the time of sensing is greatly increased. It can be operated with voltage.

Further, since it is possible to reduce the deterioration of the applied voltage of the residual electrode (Pr) due to the reduction in the size of the ferroelectric capacitor, it is possible to realize a high integration of the ferroelectric memory device. .

Further, by using the present invention, a memory operation can be performed, that is, a so-called defective cell can be relieved, and the yield can be improved.

[Brief description of the drawings]

FIG. 1A is a circuit diagram showing a memory cell according to a first embodiment of the present invention, and FIG. 1B is a voltage waveform diagram showing an operation.

FIG. 2 is a voltage waveform diagram showing Embodiment 2 of the present invention.

FIG. 3 is a circuit diagram showing a specific circuit configuration for driving a ferroelectric memory device configured using the memory cells according to Embodiments 1 and 2 of the present invention.

FIG. 4 is a block diagram showing an embodiment in which a voltage conversion circuit is added to the circuit configuration of FIG. 3;

5A is a circuit diagram showing a memory cell according to Embodiment 4 of the present invention, and FIG. 5B is a voltage waveform diagram showing an operation.

FIG. 6 is a block diagram showing a fifth embodiment of the present invention.

FIG. 7 is a voltage waveform diagram for explaining the operation of the embodiment shown in FIG. 6;

FIG. 8 is a circuit diagram showing a specific example of the sense amplifier shown in FIG.

FIG. 9 is a voltage waveform diagram showing an operation of the circuit shown in FIG.

10 is a circuit diagram showing a specific example of the word line selection control circuit shown in FIG.

11 is a circuit diagram showing a specific example of the address buffer circuit shown in FIG.

FIG. 12 is a circuit diagram showing a specific example of the internal address generation circuit shown in FIG.

13 is a circuit diagram showing a specific example of the address switching circuit shown in FIG.

FIG. 14 is a circuit diagram showing a specific example of the X decoder circuit shown in FIG.

FIG. 15 is a voltage waveform diagram illustrating the operation of the circuit shown in FIGS.

FIG. 16 is a circuit diagram showing a specific example of the plate line potential generating circuit shown in FIG.

FIG. 17 is a voltage waveform diagram illustrating the operation of the circuit shown in FIG.

18 is a voltage waveform chart illustrating another timing operation of the embodiment shown in FIG.

FIG. 19 is a circuit diagram showing a specific example of an X decoder circuit that realizes the timing operation shown in FIG.

FIG. 20 is a block diagram showing Embodiment 6 of the present invention.

21 is a circuit diagram showing a specific example of an X decoder circuit in the embodiment shown in FIG.

FIG. 22 is a voltage waveform diagram illustrating the operation of the embodiment shown in FIG.

FIG. 23 is a voltage waveform chart for explaining the operation of the seventh embodiment of the present invention.

FIG. 24 is a block diagram showing Embodiment 8 of the present invention.

FIG. 25 is a voltage waveform chart for explaining the operation of the embodiment shown in FIG. 24;

FIG. 26 is a polarization characteristic diagram showing Example 1 of the present invention.

FIG. 27 is a frequency distribution diagram showing Example 2 of the present invention.

FIG. 28 is a frequency distribution diagram showing Example 3 of the present invention.

FIG. 29 is a circuit diagram showing a connection state of memory cells used in a conventional ferroelectric memory device.

FIG. 30 is a polarization characteristic diagram for explaining the operation of the memory cell shown in FIG. 29.

FIG. 31 is a circuit diagram showing an example of a conventional ferroelectric memory device.

32 is a voltage waveform diagram and a polarization characteristic diagram of each part for describing the operation of the memory cell shown in FIG. 29.

FIG. 33 is a characteristic diagram showing a correlation between the conventional capacitance size and the applied voltage dependence of 2Pr.

[Explanation of symbols]

Reference Signs List 1 memory cell array 2 bit line discharge circuit 3 reference potential generation circuit 4 sense amplifier 5 sense amplifier control circuit 6 word line selection control circuit 7 plate line potential generation circuit 8 X system control circuit 9 address buffer circuit 10 internal address generation circuit 11 address switching Circuit 12 X decoder circuit 13 Binary counter 14 Level conversion circuit 15 X system control circuit 16 Potential switching circuit 17 Plate line driving circuit 18 Bit line charging circuit 19 Transfer gate circuit 20 Voltage conversion circuit BL, BL1, BL2, BL11, BL12 to BLm
1, BLm2 Bit line C, C1, C2 Ferroelectric capacitor Tr, Tr1, Tr2 Transistor WL, WL1, to WLn Word line PL Plate line MC, MC11 to MCnm Memory cell

Continuation of the front page (51) Int.Cl. ⁶ identification symbol FI H01L 27/108 29/788 29/792 (58) Investigated field (Int.Cl. ⁶ , DB name) G11C 11/40-11/409

Claims (13)

(57) [Claims] 1. A ferroelectric memory device having a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines, wherein the memory cell arrays are arranged in a matrix in a row direction and a column direction. , Each memory cell having at least one switching transistor and at least one ferroelectric capacitor having one electrode connected to one of a source and a drain of the transistor. Wherein the plurality of word lines are connected to gates of switching transistors in a column direction of the memory cell array, and the plurality of bit lines are connected in a row direction of the memory cell array. The ferroelectric capacitor of the source or drain of the switching transistor is not connected. The plurality of plate lines are connected to the other electrode of the ferroelectric capacitor of each of the memory cells, and apply a constant voltage to the ferroelectric capacitor. Polarize ferroelectric
By storing the information, "0" and "1"
Later, depending on the presence or absence of polarization reversal when a certain voltage is applied
That performs the operation of discriminating the information of "0" and "1"
Is higher than the highest voltage value applied during the operation.
A high excitation voltage is applied to the ferroelectric capacitor in advance.
By doing so, the polarization of the ferroelectric is increased.
Ferroelectric memory device, characterized in that that. Wherein all said memory cells, when the test signal inputted to the ferroelectric memory device of the first level, between the ferroelectric capacitance of the electrode, the excitation voltage is applied 2. The ferroelectric memory device according to claim 1 , wherein 3. A test signal from the outside to the ferroelectric memory device is input, when the test signal is in the first level, the plurality of all the bit lines, the voltage is held at the ground voltage, All of the plurality of plate lines have a voltage of the excitation voltage.
The plurality of word lines are alternately switched during the test signal input period and held at the operating voltage of each of the transistors. 2. The ferroelectric memory device according to claim 1 , wherein 4. When a test signal is input to the ferroelectric memory device from the outside and the test signal is at a first level, the voltage of all of the plurality of plate lines is held at a ground voltage; The voltage of all the plurality of bit lines is maintained at a voltage higher than the plate line by the voltage value of the excitation voltage , and each of the plurality of word lines is set within the input period of the test signal. 2. The ferroelectric memory device according to claim 1 , wherein the ferroelectric memory device is switched alternately and held at an operating voltage of each of the transistors. 5. An internal address generator, an address switching circuit, and an X decoder circuit, wherein when the test signal is at the first level, an address switching circuit outputs an address signal from the internal address generator to the address switching circuit. 4. The method according to claim 2 , wherein the plurality of word lines are alternately switched within an input period of the test signal based on a signal input to the X decoder circuit via the X decoder circuit. Or the ferroelectric memory device according to 4. 6. An internal address generating circuit, an address switching circuit, and an X decoder circuit, wherein when the test signal is at the first level, the address switching circuit outputs an address signal from the internal address generating circuit to the address switching circuit. 3. The method according to claim 2 , wherein the plurality of word lines are simultaneously switched within an input period of the test signal based on a signal input to the X decoder circuit via the X decoder circuit and decoded by the X decoder circuit. Ferroelectric memory device. 7. The memory cell, wherein a test signal input to the ferroelectric memory device is at a first level.
Between the electrodes of any of the ferroelectric capacitor is selected, the ferroelectric memory device according to claim 1, wherein the excitation voltage is intended to be applied. 8. A test signal is input to the ferroelectric memory device from the outside, and when the test signal is at a first level, the voltages of all of the plurality of bit lines are held at a ground voltage; All of the plurality of plate lines have a voltage of the excitation voltage.
Held to a voltage higher than by a voltage value component of pressure the bit lines, according to claim 7 wherein the strong connected switching transistors to the dielectric capacitance, characterized in that it is intended to be turned on are selected arbitrarily 3. The ferroelectric memory device according to 1. Wherein said ferroelectric memory device test signal from the outside is input to, when the test signal of the first level, the plurality of all the plate lines, the voltage is held at the ground voltage, the The voltage of all of the plurality of bit lines is maintained at a voltage higher than the plate line by the voltage value of the excitation voltage, and the switching transistor connected to the ferroelectric capacitor is arbitrarily selected. 8. The ferroelectric memory device according to claim 7 , wherein the ferroelectric memory device is selected and made conductive. 10. An address buffer circuit, and an X decoder circuit, wherein when the test signal is at the first level, an address signal externally input to the ferroelectric memory device is passed through the address buffer circuit. Input to the X decoder circuit,
Selects a word line in response to the decoded signal by the decoder circuit, wherein the strong claim 7, 8 or 9, wherein the dielectric is intended to conduct selected arbitrarily the connected switching transistor to the capacitor 3. The ferroelectric memory device according to 1. 11. A dummy cell, a plurality of dummy word lines, a plurality of dummy plate lines, a reference potential generation circuit,
A sense amplifier control circuit, wherein the dummy cell includes a switching transistor connected to the plurality of bit lines, electrodes attached to both surfaces of the ferroelectric, and one electrode connected to a source of the transistor,
At least one connected to one of the drains
And a plurality of dummy word lines connected to the gates of the transistors of the plurality of dummy cells, and a test signal input to the ferroelectric memory device is supplied to the first level. The dummy plate line is connected to the other electrode of the ferroelectric capacitors of the plurality of dummy cells, and the reference potential generating circuit In operation, a reference voltage is generated. A sense amplifier control circuit controls the reference potential generation circuit. Further, all of the dummy cells receive a first test signal input to a ferroelectric memory device. 2. The ferroelectric memory according to claim 1, wherein the reference voltage is applied between both electrodes of the ferroelectric capacitor at the level of the ferroelectric capacitor. Li equipment. 12. When a test signal input to the ferroelectric memory device is at a first level, the voltage of all of the plurality of bit lines is held at a ground voltage, and the dummy plate line is The voltage is maintained at a voltage higher than the bit line by the voltage value of the excitation voltage , and the plurality of dummy word lines are alternately switched during the test signal input period to operate the dummy cell transistor. The ferroelectric memory device according to claim 11 , wherein the ferroelectric memory device is held at a voltage. When 13. A test signal inputted to the ferroelectric memory device of the first level, the dummy plate line, the voltage is held at the ground voltage, the plurality of all the bit lines, The voltage is maintained at a voltage higher than the dummy plate line by the voltage value of the excitation voltage , and the plurality of dummy word lines are alternately switched during the input period of the test signal, and 12. The ferroelectric memory device according to claim 11 , wherein the ferroelectric memory device is held at an operating voltage of the transistor.