JP2858836B2 - Image signal processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing circuit for converting character data for one screen stored in a frame memory into a video signal and transmitting the video signal to a CRT display device. The present invention relates to an image signal processing circuit that can realize each digital signal processing circuit with a circuit having low frequency characteristics.

2. Description of the Related Art In a CRT display device used as a terminal device such as a computer, a video signal, a horizontal synchronization signal, and a vertical synchronization signal are often input as separate signals. Data displayed on a CRT display device used for such a monitor is often digital data such as characters and graphics. An image signal processing circuit for converting these data into a video signal and sending it to a CRT display device is configured, for example, as shown in FIG.

That is, the character data sent from the computer is stored in the frame memory 1. This frame memory 1
Is a memory for storing, for example, a character code for one screen of character data that can be displayed at one time on the display screen of the CRT display device 2. As shown in FIG. When the read address signal a is input from the CRT control unit 3 at the time when the character data is stored, one character code b of the corresponding address is read and transmitted to the character generator (CG) 4. Character generator 4
Is, as shown in FIG. 7 (b), the character pattern of the character specified by the character code corresponding to each character code b.
For example, it is stored as a [5 × 7] dot matrix 5. Then, when the line address signal c is input from the CRT control section 3, the [5 × 7] dot matrix 5 is changed from the body matrix [8 × 10] dots to the vertical direction indicated by the line address signal c. It is output as an 8-bit parallel dot data signal d that forms a horizontal row of dot rows belonging to a dot position.

The parallel / serial converter 6 converts the parallel dot data signal d into a parallel dot data signal e and sends it to the next digital / analog converter (hereinafter abbreviated as D / A converter) 7. D
The / A converter 7 converts the digital serial dot data signal e into an analog dot data signal, that is, a video signal i, and sends it to the next CRT display device 2. The CRT display device 2
The input video signal i is displayed on the display screen using the horizontal synchronization signal g and the vertical synchronization signal h input from the CRT control unit 3.

FIG. 8 is a time chart showing the output timing of each signal. When an 8-bit read address signal a is input from the CRT control unit 3 to the frame memory 1, an 8-bit character code h of the corresponding address is output, and the character code b is used to output an address (AD) in the character generator 4.
C) is designated, and an 8-bit parallel dot data signal d designated by the line address c of the dot matrix stored in the address (ADC) is output. Then, the 8-bit parallel dot data signal d is converted by the parallel / serial converter 6 into a serial dot data signal e,
Further, it is converted into a video signal i by the D / A converter 7.

[Problem to be Solved by the Invention] However, the image signal processing circuit configured as shown in FIG. 6 still has the following problem.

That is, since the CRT control unit 3, the frame memory 1, the character generator 4, and the parallel / serial converter 6 are digital circuits, each signal a, b, d, e output from each of the circuits 3, 1, 4, 6 Is usually a TTL digital signal. Therefore, as shown in FIG. 8, the amplitude value V _PP of the signal is 4 V to 5 V. In addition,
The amplitude value V _PP of the analog video signal i output from the D / A converter 7 is usually 0.6 to 1.0 V. Note that the frequency f _H of the horizontal synchronizing signal g in the general CRT display device incorporated in a television set or the like, is 15.75 kHz, the frequency f _B of the video signal i, depending on the number of pixels in the horizontal direction, In order to display an image accurately, the frequency is about 4.2 MHz.

However, in a CRT display device incorporated in a monitor device as a terminal device such as a computer, for example, characters of the above-mentioned [5 × 7] font are horizontally displayed on a display screen by 80 to 80 characters.
When 100 character display is more 16MHz is required as the frequency f _B of the video signal i described above.

Therefore, the eighth output from the parallel / serial converter 6
The digital serial dot data signal e shown in FIG.
f _B = 16MHz signal level becomes a pulse waveform to change 4 V to 5 V. Accordingly, the rise of the pulse in the pulse waveform, the high frequency noise peak value at the time of the fall corresponds to the amplitude value V _PP of the 4~5V occurs.

Since this high-frequency noise has an adverse effect on other electronic devices, it is necessary to take noise prevention measures such as covering the whole of the parallel / serial converter 6 with a shield case.

In general, when the operating frequency increases, it is necessary to use high-grade components capable of high-frequency operation. Therefore, in the case of a display device having a larger number of display dots, it is necessary to operate normally at a high frequency of 16 MHz. The manufacturing cost of the parallel / serial converter 6 increases significantly.

The operating frequency f _D of the frame memory 1 and the character generator 4 is about 1/10 of the serial dot data signal e as shown in FIG. , You will have to run faster.

The present invention has been made in view of such circumstances, and divides a horizontal dot row of a dot matrix of character data to be displayed into a plurality of dot rows, converts the dot row into an analog dot data signal, and converts the signal into an analog dot data signal. It is an object of the present invention to provide an image signal processing circuit that can lower the operating frequency of the entire system including the parallel / serial converter, suppress high-frequency noise generation, and reduce the manufacturing cost by combining.

Means for Solving the Problems In order to solve the above problems, an image signal processing circuit according to the present invention comprises a frame memory for storing character data to be displayed on a display screen of a CRT display device, and a character data stored in the frame memory. Each dot of the horizontal dot row in the dot matrix of each character obtained based on is extracted by shifting the mutual position every predetermined number of points and divided into a plurality of dot rows, each as a parallel dot data signal Dot row dividing means for outputting, a plurality of parallel / serial converters for converting each parallel dot data signal obtained by the dot row dividing means into a serial dot data signal, and output from each parallel / serial converter. Multiple digital / digital converters that convert serial dot data signals to analog dot data signals.
It comprises an analog converter and a signal switching circuit for sequentially switching a plurality of analog dot data signals converted by each of the digital / analog converters and sending out a single video signal to a CRT display device.

In another aspect of the invention, instead of the above-described signal switching circuit, a plurality of analog dot data signals converted by the respective digital / analog converters are added and sent as one video signal to the CRT display device. A signal addition circuit is provided.

[Operation] In the image signal processing circuit configured as described above,
The dots constituting the horizontal dot row of the dot matrix of each character data are not read out as they are, but are positioned at predetermined intervals such as, for example, each dot at an even position and each dot at an odd position. Are divided into a plurality of dot rows extracted by shifting Therefore, the number of dots included in each of the decomposed dot rows is reduced to 1 / divided number as compared with the number of dots before division. Therefore, since the number of data of each parallel dot data signal composed of the divided dot rows decreases, when this parallel dot data signal is converted into a serial dot data signal using a parallel / serial converter, a predetermined period The number of dots included in the area decreases. Therefore, the frequency of the serial dot data signal is reduced to one-divided number as compared with the frequency of the serial dot data signal in an undivided state. Accordingly, the operating frequency of each circuit is reduced to one-fourth.

Each of the divided serial dot data signals is converted into an analog dot data signal by a D / A converter. Then, the signals are alternately switched by the signal switching circuit and are combined into one video signal. Although the frequency of the video signal synthesized by this switching becomes the original high frequency, the amplitude value of the analog video signal is much smaller than that of the digital signal, so that high-frequency noise becomes a particular problem. There is no.

In addition, by switching each analog dot data signal output from the D / A converter alternately by the signal switching circuit, the digital serial dot data signal is converted into the analog dot data signal by the D / A converter. In this case, glitches generated in the case can be removed.

Further, in another invention, a signal addition circuit is used instead of the signal switching circuit, but the operation and effect other than the above-described glitch removal are the same as those of the above-described invention.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a block diagram showing a schematic configuration of an image signal processing circuit according to the embodiment. The same parts as those in FIG. 6 are denoted by the same reference numerals.

Frame memory 1 is the CRT sent from the computer
This is a memory that stores character data for one screen to be displayed on the display device 2 in, for example, character codes. When a read address signal a is input from the CRT control unit 3, the frame memory 1 reads one character code b consisting of 8 bits stored in the corresponding address and sends it to the first and second character generators 11a and 11b. I do. Each character generator 11
In a and 11b, as shown in FIG. 2, a character pattern of a character designated by the corresponding character code is stored as a dot matrix 5 of [5 × 7], for example, corresponding to each character code b. ing.

Then, when the line address signal c is input from the CRT control unit 3, the first character generator 11a, as shown in FIG.
Of the five dots d ₁ , d ₂ , d ₃ , d ₄ , d ₅ constituting one horizontal row of dots belonging to the vertical dot position indicated by the line address signal c, Dots d ₁ , d ₃ , d ₅
Is added with a dot of 0 later, and is output as a 4-bit parallel dot data signal j consisting of [d ₁ , d ₃ , d ₅ , 0].

On the other hand, in the second character generator 11b, when the line address signal c is input from the CRT control unit 3, as shown in FIG.
Of the five dots d ₁ , d ₂ , d ₃ , d ₄ , d ₅ forming one horizontal row of dots belonging to the vertical dot position indicated by the line address signal c, Dots d ₂ , d ₄ ,
Is output as a 4-bit parallel dot data signal k consisting of [0, d ₂ , d ₄ , 0] with 0 dots added before and after.
Therefore, each parallel dot data signal j, k has an output timing time difference of one dot between each other.

The 4-bit parallel dot data signals j, k output from the character generators 11a, 11b are input to the first and second parallel / serial converters 12a, 12b, respectively. 1st, 2nd
The parallel / serial converters 12a and 12b convert the input parallel dot data signals j and k into serial dot data signals m and n and send them to the first and second D / A converters 13a and 13b, respectively. I do.
The first and second D / A converters 13a and 13b convert the input serial dot data signals m and n into analog dot data signals o and p, respectively.
Convert to

The analog dot data signals o, p output from the first and second D / A converters 13a, 13b are input to the signal switching circuit 14. The signal switching circuit 14 has a circuit configuration as shown in FIG. That is, one analog dot data signal o is grounded via the normally closed contact 14a, and the other analog dot data signal p is grounded via the normally closed contact 14b. Each of the contacts 14a and 14b is switch-controlled by a switch signal q output from the CRT control unit 3. Therefore,
Each time the signal level of the switching signal q changes, the grounded analog data signals o and p are alternately switched. Then, contact 14
The analog dot data signals o and p on the side where a and b are released are amplified by the amplifier 14c, combined into one video signal i via the buffer amplifier 14d, and input to the CRT display device 2.

The switching frequency of the switching signal q is determined by each D / A converter 13
The frequency is set to twice the frequency in a and 13b.
Also, since the analog dot data signals o and p are out of phase by one dot as described above, even if these are alternately switched and the waveforms are synthesized, the pulses of the analog dot data signals o and p overlap. There is no.

The CRT display device 2 displays the input video signal i on a display screen using the horizontal synchronization signal g and the vertical synchronization signal h input from the CRT control unit 3.

Next, the operation of the image signal processing circuit thus configured will be described with reference to the time chart of FIG.

First, it is assumed that character data [A Voltage... End.] For one screen as shown in FIG. 7A is stored in the frame memory 1 in the form of character codes.

In this state, when an 8-bit read address signal a is input from the CRT control unit 3 to the frame memory 1, an 8-bit character code b of the corresponding address is output. An address (ADC) in the character generators 11a and 11b is specified, and each of the 4-bit parallel dot data signals j and k specified by the line address signal c of the dot matrix 5 stored in the address (ADC) is output. Is output. The 4-bit parallel dot data signals j, k are respectively connected to the first and second parallel / serial converters 1.
2a, with at 12b, the amplitude value V _PP digital serial dot data signal m of TTL having a pulse waveform of 4 V to 5 V, is converted to n. Therefore, at this point, a time difference (phase difference) of one dot occurs between the serial dot data signals m and n.

The serial dot data signals m and n are the first and second D / A
Converter 13a, with at 13b, the amplitude value V _PP analog dot data signal o having a pulse waveform of 0.6～1.0V, is converted to p. The rise of the pulse in each analog dot data signal o, p is synchronized with the rise of the pulse in each serial dot data signal m, n.

Each of the analog dot data signals o and p whose phases are shifted by one dot is alternately switched by the next signal switching circuit 14 in the latter half of the pulse waveform and synthesized into one video signal i.

Therefore, the video signal i with the synthesized waveform is a correct video signal i including on / off information of all the horizontal dots of the dot matrix 5 constituting each character pattern stored in each of the character generators 11a and 11b. Therefore, a correct character corresponding to the character code is displayed on the CRT display device 2.

In the image signal processing circuit configured as described above, the cycle T _A of each pulse of each analog dot data signal o, p and each serial dot data signal m, n is equal to the cycle T _B of each pulse of the video signal i. Double. Therefore, the amplitude value of 4-5V
The frequency f _A of each digital serial dot data signal m, n having V _PP is 1/2 of the frequency f _B (= 16 MHz) of the video signal i. Therefore, the high-frequency noise level radiated from each of the parallel / serial converters 12a and 12b can be reduced by the reduced frequency. As a result, each parallel / serial converter 12a, 12b
It is not necessary to take any major noise prevention measures.

In addition, since the operating frequency of each of the parallel / serial converters 12a and 12b can be reduced to half of the operating frequency of the parallel / serial converter 6 in the conventional circuit shown in FIG. , 12b, there is no need to use high-grade electronic components, and the circuit configuration can be greatly simplified. Therefore, even if two parallel / serial converters are used, the manufacturing cost of the entire image signal processing circuit can be reduced.

The advantage of synthesizing the signals by alternately switching the analog dot data signals o and p output from the D / A converters 13a and 13b by the signal switching circuit 14 will be described with reference to FIG. That is, each D / A converter 13a, 13b converts the input digital serial dot data signal m, n into an analog voltage value using a ladder network operated by a large number of switching transistors. Since there is a difference in characteristics, an error occurs in the actual switching operation time even if a plurality of switching transistors specified by digital values are driven simultaneously. Therefore, within a short time immediately after the conversion of the digital data into the analog data, the switching transistors that are already conducting and the switching transistors that are going to conduct from among the designated switching transistors are mixed. Therefore, each D / A
Each of the analog dot data signals o, p output from the converters 13a, 13b has a waveform distortion called a glitch 20 at the instant when the signal level changes. This waveform distortion becomes values that can not be ignored frequency f _B becomes higher video signal i.

However, each contact 14a, 14b is closed by the switching signal q,
The waveform portion of each analog dot data signal o, p waveform immediately after each signal level change is grounded. Therefore, only the latter half of the signal waveform is captured in video signal i. Therefore, it is possible to prevent the glitch 20 from being included in the video signal i.

FIG. 5 is a block diagram showing an image signal processing circuit according to another embodiment of the present invention. 1 are given the same reference numerals.

In this embodiment, the CRT is stored in the frame memory 23.
The character data to be displayed on the display device 2 is not in the character code state but is already stored in the dot matrix 5 in a developed state. Therefore, each character generator is not needed. When the line address signal c is input from the CRT control unit 24, the frame memory 23 outputs a parallel dot data signal j including odd-numbered dots and a parallel dot data signal k including even-numbered dots in the dot matrix 5.
Are sent to the first and second parallel / serial converters 12a and 12b.

The analog dot data signals o, p output from the D / A converters 13a, 13b are input to the signal adding circuit 15.
The signal adding circuit 15 simply adds the respective analog dot data signals o and p and sends them to the CRT display device 2 as a video signal i.
Since the phases of o and p are shifted by one dot, each pulse of each analog dot data signal o and p is synthesized with the video signal i without overlapping.

Even in the image signal processing circuit configured as described above,
Since the operating frequency of each of the parallel / serial converters 12a and 12b is 1/2 of that of the conventional circuit shown in FIG. 6, almost the same effects as in the above-described embodiment can be obtained.

Note that the present invention is not limited to the above-described embodiments. In each of the embodiments, each dot in the horizontal dot row of the dot matrix is divided into two dot rows including a dot row including odd-numbered dots and a dot row including even-numbered dots, but the number of divisions is particularly limited to two. However, it can be set arbitrarily according to the value of the operating frequency that requires a parallel / serial converter.

[Effects of the Invention] As described above, in the image signal processing circuit of the present invention, the horizontal dot row of the dot matrix of the character data displayed on the CRT display device is divided into a plurality of dot rows, Is converted into an analog dot data signal, and the signals are combined to obtain a high-frequency video signal for displaying a correct character. Therefore, since the frequency at each digital signal point decreases, the parallel /
The operating frequency of the entire system including the serial converter can be reduced, and frequency noise generation can be suppressed.
The manufacturing cost of the entire circuit can be reduced.

 Also, glitches can be removed from the video signal.

[Brief description of the drawings]

1 (a) and 1 (b) are block diagrams showing an image signal processing circuit according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are techniques for extracting each dot row from a dot matrix in the embodiment. , FIG. 3 is a time chart showing the operation of the embodiment, FIG. 4 is a time chart for explaining the effect of the apparatus of the embodiment, and FIG. 5 is an image according to another embodiment of the present invention. FIG. 6 is a block diagram showing a conventional image signal processing circuit, FIG. 7 is a diagram showing storage contents of a frame memory and a character generator in the conventional circuit, and FIG. 8 is a block diagram showing the conventional circuit. 6 is a time chart showing the operation of the first embodiment. 1,23 ... frame memory, 2 ... CRT display device, 3,24 ...
... CRT controller, 5 ... dot matrix, 11a ... first
, A second character generator, 12a... A first parallel / serial converter, 12b.
... second parallel / serial converter, 13a ... first D / A converter,
13b ... second D / A converter, 14 ... signal switching circuit, 15 ...
Signal addition circuit, 20 ... glitch.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 5/00

Claims (2)

(57) [Claims] 1. A frame memory (1) for storing character data to be displayed on a display screen of a CRT display device (2), and a dot matrix (5) for each character obtained based on the character data in the frame memory. Dot row dividing means for taking out each dot of a horizontal dot row by shifting a mutual position every predetermined number and dividing it into a plurality of dot rows, and outputting them as parallel dot data signals; A plurality of parallel / serial converters (12a, 12b) for converting each parallel dot data signal obtained by the column dividing means into a serial dot data signal; and a serial dot data signal output from each parallel / serial converter. Digital-to-analog converters (13a, 13b) that convert the data into analog dot data signals, and multiple analog-to-analog converters Image signal processing circuit including the signal switching circuit for sending to the CRT display device as a single video signal sequentially switches the dot data signals and (14). 2. A frame memory (23) for storing character data to be displayed on a display screen of a CRT display device (2), and a dot matrix (5) of each character obtained based on the character data in the frame memory. Dot row dividing means for taking out each dot of a horizontal dot row by shifting the mutual position by a predetermined number and dividing it into a plurality of dot rows, each of which is output as a parallel dot data signal; A plurality of parallel / serial converters (12a, 12b) for converting each parallel dot data signal obtained by the dividing means into a serial dot data signal, and a serial dot data signal output from each parallel / serial converter. A plurality of digital / analog converters (13a, 13b) that convert to analog dot data signals, and a plurality of analogs converted by each digital / analog converter An image signal processing circuit comprising: a signal addition circuit (15) for adding a dot data signal and sending it as one video signal to the CRT display device.