JP2726108B2 - Cell switching equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell exchange device for exchanging various information such as voice, data, and images into blocks called cells, and exchanging them at high speed. It is.

[Conventional technology]

A switch network called a banyan network has been known as an example of a method of performing high-speed switching by directly referring to header information of a cell by hardware.

Fig. 5 shows the design of an integrated services packet network (Design
of an Intergrated Services Packet Network), IEEE Journal on Se
lected Areas in Communications), Vol.SAC-4, pp.1373
-1380, November, 1986, an example of a banyan net,
In the figure, 1a and 1b are input cells, 2 is an input port, 3 is a switching device composed of a plurality of 2 × 2 unit switches 4, and 5 is an output port.

In the above document, the name of a packet is used instead of the name of a cell. However, the same expression is used for both a cell and a packet in that multimedia information is blocked and a header including destination information is added. doing.
However, in general, a packet is treated as a variable length of one block, but is different in that a cell is treated as a fixed length in accordance with international standard rules. ATM (Asynchronous Transfer Mod) for high-speed transmission and exchange
e) In communication, the term "cell" is used, and the term "cell" is used instead of a packet in the following description of the conventional example.

Next, the operation will be described. In FIG. 5, a cell switching device 3 including a plurality of 2 × 2 unit switches 4 is configured to select an output port by a corresponding bit of a header part bit string of an input cell 1 (a generic name of 1a and 1b). For example, the unit switches 4 arranged in the first column on the left side connect the input port of the unit switch 4 to the upper output port 5a if the first bit of the header part is “0”, and set “1”. If it is connected to the lower output port 5b. Similarly, the second on the left
The unit switches 4 arranged in a line correspond to the header 2 of the input cell 1.
The output bits 5c and 5d are selected by the bit.
By arranging such unit switches 4 side by side and interconnecting them as shown in FIG. 5, the number of the target output port 5 at the final stage is expressed in a binary number and added to the header of the cell 1. Is input from any input port 2 to reach the desired output port 5.

[Problems to be solved by the invention]

Since the conventional cell switching apparatus is configured as described above, blocking (collision) occurs when the cells 1a and 1b aiming at the same output port 5 are simultaneously input to the input port 2.
There was a problem of causing To cope with this problem, there is a method in which a buffer memory is provided at the input portion or inside of the unit switch 4. However, when cells to a certain output port are concentrated, the buffer memory is blocked and cells to another output port are blocked. However, there was a problem that the light was also blocked.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and can perform switching without causing blocking and without affecting cells to other output ports even when cells are concentrated on one output port. The purpose is to obtain a cell switching device.

[Means for solving the problem]

A cell switching device according to the present invention classifies a plurality of input ports for inputting cells into a plurality of input port groups, and for each of the input port groups, an input-stage cell multiplexing circuit for time-division multiplexing input cells; And an input stage cell selection circuit for selecting and passing cells directed to a specific output port group among a plurality of output ports into a plurality of output port groups from output signals of the input stage cell multiplexing circuit. A staged cell exchange switch module,
A storage circuit for storing cells output from the input stage cell selection circuit or the preceding output stage cell selection circuit and directed to a specific output port group, the number of cells stored in the storage circuit is managed for each destination, and For a destination having a cell of N, a rule of reading more cells than a destination having a small number of cells, or for a destination having a cell storage amount of a certain value or more, N (N is an integer of 2 or more) Cells are read continuously, and n (n is 1 or 0) cells are read for other destinations, or N cells (N is 2 or more) for destinations with the largest cell storage amount Integer)
Cells are read continuously, and n is read for other destinations.
For a destination having many cells for reading out (n is 1 or 0) cells, a storage control circuit for outputting from the storage circuit in accordance with the rule of reading out more cells than a destination having less cells, the storage An output-stage cell multiplexing circuit for multiplexing cells output by the circuit, and an output for selecting and passing a cell directed to the specific output port group or the specific output port from an output signal of the output-stage cell multiplexing circuit An output stage cell exchange switch module having a stage cell selection circuit, and a speed conversion circuit connected to the last stage output stage cell exchange switch module for converting the speed of the time-division multiplexed cells into the speed of the output port. And a cell output stage module. In addition, control is performed to prevent a system in which reading is stopped for an outgoing line having a small number of cells as a destination and a delay time increases to a certain value or more.

[Action]

The cell switching apparatus according to the present invention divides cells arriving at all input ports into a plurality of groups, multiplexes the cells once by an input cell multiplexing circuit of an input cell switching switch module in the group, and then selects a cell. Allocate to output port by address filter by circuit. One or a plurality of output stage cell exchange switch modules receiving this output write the cells into the storage circuit, and again by the cell multiplexing circuit for each output port group divided into a plurality of groups under the storage control circuit. After cell multiplexing, the cells are sorted toward each output port by the final address filter by the cell selection circuit, thereby reducing the probability of cells being discarded.

〔Example〕

An embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 is an overall circuit diagram showing the cell switching device 3. This cell switching device 3 divides input ports 2 for inputting a plurality of cells into a plurality of groups, and for each group, an input-stage cell exchange switch module 60 to 63 for exchanging each input cell, and a preceding-stage cell exchange switch. Output stage cell exchange switch module 70 to exchange cells for a specific output port group sent from the module
73, and a cell output stage module 80-83 at the last stage.

The input-stage cell exchange switch modules 60 to 63, for example, the input-stage cell exchange switch module 60 are provided with a plurality of input-stage cell multiplexing circuits 7 for performing time-division multiplexing of cells and a plurality of output signals of the input-stage cell multiplexing circuits 7. And input stage cell selection circuits 8a to 8d that select cells by an address filter and distribute and pass the cells to a specific output port group among the output ports divided into a plurality of groups. The output-stage cell exchange switch modules 70 to 73, for example, the output-stage cell exchange switch module 70, as shown in FIG. 2, specify a destination of a cell toward a specific output port group output from the preceding cell selection circuit. The header processing circuits 9a to 9d that read and analyze and output the cells output from the header processing circuits 9a to 9d can be stored at the addresses by specifying the write address, and when the read address is specified. The storage circuits 10a to 10d capable of reading stored cells irrespective of the order in which they are written, and the storage control circuit 11, which outputs the addresses of the cells written by the storage circuit while referring to the header processing circuits 9a to 9d An address exchange circuit 16 for distributing by port group (hereinafter, referred to as an outgoing line) so that the assigned addresses can be written for each outgoing line and on a first-come-first-served basis. Outgoing line corresponding address FIFO17a ~ 1
7d, a read right grant circuit 18 for giving a read address while allowing timing to the storage circuits 10a to 10d and permitting read, and when reading a cell from the storage circuits 10a to 10d, the read address is managed and held as an empty address. A vacant address management circuit 19 for providing a write address when a new cell arrives in the storage circuits 10a to 10d.
a to 19d, an output-stage cell multiplexing circuit 12 for multiplexing cells read from the storage circuits 10a to 10d, and an address of a cell directed to a specific group among specific output port groups among the output signals. And output stage cell selection circuits 13a to 13d which are selected by a filter and passed through. Also,
In FIG. 1, the cell output stage modules 80 to 83, for example, the cell output stage module 80 are speed conversion circuits 14a to 14d for converting the speed of the time-division multiplexed cell to the speed of the output port.
Is provided.

Next, the operation will be described. In FIG. 1, the cells have a fixed length, and the arrival of the input cells is random, but the cell input phase is adjusted before being input to the input ports I _{0 to} I ₁₅ , and the cell input from all the input ports 2 is It is assumed that they are supplied with the same cell phase.

First, the operation of the input-stage (first-stage) cell exchange switch modules 60 to 63 will be described with reference to FIG. 3 using the input-stage cell exchange switch module 60 as an example. Input signals a to d
Are time-division multiplexed by the cell multiplexing circuit 7 and multiplexed with the signal e shown in FIG. This signal e is detected by the input-stage cell selection circuits 8a to 8d corresponding to each of the output ports of the input-stage cell exchange switch module 60, when the first address given to the header of the cell is detected. , p, a cell to be directed to a predetermined output port is selected and output. FIG. 3 shows a state in which the cell having the first address "1" is output as the signal f and the cell having the first address "2" is output as the signal p. Here, the multiplexing is performed by multiplexing at a speed that is several times the link speed of the input port, and for example, multiplexing into synchronized time slots in cell units as shown in FIG. Time slots without input cells are allocated as empty slots so that the first address of the header does not correspond to any output port.

As described above, the input stage cell exchange switch module 60
In 63, the cells input at the link speed are switched according to the first address of the header part, and are sent out to the first-stage output port at a multiplexed speed in a burst manner.

Next, a second-stage output-stage cell exchange switch module
70-73 operation, output stage cell exchange switch module 70
Will be described as an example. In FIG. 2, among the outputs of the input-stage cell exchange switch modules 60 to 63, four signals input to the input-stage cell exchange switch module 70 are denoted by f, g, h, and i, respectively. The signals fi are signals in which cells are sent out in bursts on a multiplexed signal line, and the number of cells on the four signals varies. Therefore, these signals are supplied to storage circuits 10a to 10d provided for each input port in the output stage cell exchange switch module 70, and after buffering once, the output is multiplexed by the output stage cell multiplexing circuit 12. Perform the conversion. If the arrival of the input cells is uniform both temporally and spatially, the speed of the output signal j of the output-stage cell multiplexing circuit 12 is equal to or more than the number of ports of the input link speed of the output-stage cell exchange switch module 70 and is equal to or more than the number of ports. On condition that there is, this output stage cell exchange switch module 70
Multiplexing without discarding the cells input to. However, since the actual arrival of the cells varies in time and space, it is necessary to buffer the cells once in the storage circuits 10a to 10d to absorb the overflow of the cells.

The storage control circuit 11 has a function of not reading only cells addressed to the same outgoing line at the time of reading cells, and also preventing the order of the cells from being reversed. Specifically, in order to manage and store the addresses of the storage circuits 10a to 10d for each output line when the cell is stored in the storage circuits 10a to 10d, first, the addresses are allocated by the address exchange circuit 16 for each output line, and Are stored in the outgoing line correspondence addresses FIFO 17a to 17d. The read right grant circuit 18 refers to the output of the outgoing line corresponding address FIFO 17a to 17d, and the output stage cell multiplexing circuit 12 at the subsequent stage
All storage circuits 10a-1 as long as the outputs of 10a-10d can be multiplexed
The read address is given to 0d, and the cell is transmitted. Various methods can be considered for the read control method of the storage circuits 10a to 10d. For example, outgoing line corresponding address FIFO 17a-17d
N (N is an integer of 2 or more) cells are continuously read out for outgoing lines whose remaining storage amount is a certain value or more, and n cells (n is 1 or 0) for other outgoing lines. ), The cells are continuously read and multiplexed, or the number of cells addressed to each other's outgoing lines is compared, and N cells are continuously read out for the outgoing line having the largest remaining amount. For other outgoing lines,
A method of reading and multiplexing n cells is conceivable, but in any case, for an outgoing line having many cells, it is necessary to read out more cells than an outgoing line having few cells. Become. At this time, it is necessary to avoid a method in which reading is stopped for an outgoing line having a small number of cells as a destination and the delay time increases to a certain value or more. Further, in the output stage cell exchange switch module 70 of the final stage, it is necessary to perform speed conversion at a stage subsequent to the outgoing line, and in order not to cause overflow here, it is necessary to uniformly read out each of the storage circuits 10a to 10d. is there. Therefore, in the read right assignment circuit 18 of the final stage output stage cell exchange switch module 70, control is performed to read out cells destined for each outgoing line in the outgoing line order.

Here, as one embodiment, an intermediate-stage output-stage cell exchange switch module 70 that is not the final stage, that is, has an output-stage cell exchange switch module in the subsequent stage will be described. As a method, two cells are read out continuously when the remaining amount of cells by destination / outgoing line exceeds four (corresponding to the number of input ports), and one or zero is read when the remaining number is four or less. Consider a method of reading and multiplexing cells,
The description will be made with reference to the timing charts of FIGS. 3 and 4.

It is assumed that cell rows as shown in FIG. 4 are input as the signals f to i. The signal g indicates a case where nine cells successively arrive from the input-stage cell exchange switch module 61 toward the outgoing lines k, l, m, and n. Outgoing lines k, l, m,
n, the outgoing line corresponding address FIFO is 17a, 17b, 1
7c and 17d correspond. The read right grant circuit 18 monitors the remaining cell storage amount in each of the outgoing line corresponding addresses FIFO 17a to 17d. First, the address storing the first cell is stored in the outgoing line corresponding addresses FIFO 17a to 17d. At this point, the read gate of the outgoing line corresponding address FIFO 17a addressed to k is opened to obtain the address. Then, one cell corresponding to this address is output from the storage circuit 10a to the output-stage cell multiplexing circuit 12, and multiplexing is started. The multiplexing is performed in cell units in the order of the outgoing line correspondence addresses FIFO 17a, 17b, 17c, and 17d. If there is no cell stored, the cell is immediately read from the next FIFO and the multiplexing is started. The first cell is a cell addressed to the outgoing line k, and is the first cell of the signal f (hereinafter, the cell name will be referred to as, for example, the F1 cell using the number F1 or the like of the data portion of the cell). Then, an address is taken out from the outgoing line corresponding address FIFO 17a, and the cell is read out and multiplexed by giving this address to the storage circuit 10a as a read address. At the same time, the read address is added to the empty address management FIFO 191a. When the multiplexing of the cells is completed, the address is taken out from the outgoing line corresponding address FIFO 17b addressed to the outgoing line 1 and the G2 cell is multiplexed. Next is the outgoing address corresponding to outgoing line m.
Although it is the number of the FIFO 17c, since it is empty, the number immediately goes to the outgoing line n, the address is taken out from the outgoing line corresponding address FIFO 17d, and the G3 cell is multiplexed. Next, since the turn is directed to the outgoing line k, the G1 cell is multiplexed. Next is the turn 1
I1 cells are multiplexed. Next, G6 cell at the turn of the outgoing line m,
Similarly, G7 cells are multiplexed at the output line number n. Then,
Although it is the number of the outgoing line k, since the remaining amount of the outgoing line corresponding address FIFO 17a is 5 (indicated by a circle in FIG. 4), two are read out consecutively, and H1 and G4 are multiplexed. Hereinafter, H2, H3, G5, G9,
Multiplexing is performed in the order of F3, H5, F2, H4, I2, G8, F4, and G10.

As described above, the output stage cell exchange switch module 70
The output circuit corresponding to the outgoing line FIFO 17a to 17b
10d can be managed, and cells can be temporarily stored. In general, the sum of cells supplied from the signal lines to the output stage cell exchange switch modules 70 to 71 corresponds to the number of input ports times the input link speed on average unless there is a temporal or spatial deviation. , The total number of cells that can be multiplexed on the multiplexed signal of the output-stage cell exchange switch modules 70-73. The increase / decrease of the cell storage remaining amount in the storage circuits 10a to 10d occurs because the number of cell arrivals fluctuates from the average temporally and spatially. Therefore, as described above, the storage circuits 10a to 10d
By accumulating data in cells, temporal fluctuations are absorbed and cell discard is reduced.

Also, the storage circuits 10a to 10d of the output stage cell exchange switch modules 70 to 73 can write at a multiplexed high speed and read at the outgoing link speed even when a plurality of cells arrive at the same time. So the storage circuits 10a-1
Even if the number of cells within the capacity of 0d is concentrated in the same period, it is not discarded.

In the above embodiment, the number of input ports and the number of output ports of the entire cell exchange switch are the same, but may be different. Further, the number of stages of the output stage cell exchange switch modules 70 to 73 may be expanded by connecting them sequentially in multiple stages. Further, in the above embodiment, the number of input / output ports of the entire cell exchange switch is set to 16 and the 4 × 4 cell exchange switch module is divided into four. However, other values may be used. Further, the cell switch may be configured as one cell exchange switch without being divided into such modules.

In addition, the example of giving the outgoing line number to the two address parts corresponding to the two-stage cell exchange switch module is shown as the address of the header part of the cell, but giving the coded number to one address part etc. Some conversion processing may be performed.

Further, in the above-described embodiment, the case where one cell is output to only one output port has been described. However, depending on how the address is specified, the output stage cell selection circuits 13a to 13e are output so as to output to a plurality of output ports. It is possible to set 13h, and a broadcasting function may be added.

Alternatively, the header section and the data section may be separated from each other in structure and circuits having different speeds may be used, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Next, in the above embodiment, the link speed of the input port was set to be the same. However, by making the read speed from the storage circuits 10a to 10d of the output stage shown in FIG. It is possible, and conversely, the link speed of the input port can be higher than the speed of the output port. The multiplexing speed of the signal j is assumed to be the same as the multiplexing speed of the signal e. However, by increasing the multiplexing speed of the signal j, the cell discarding between the output-stage cell exchange switch module stages is performed. The rate can be even lower.

Next, in the above embodiment, one outgoing line corresponding address FIFO 17a to 17d is provided for each outgoing line of the output stage cell exchange switch module 70, but a plurality of FIFOs are provided for each outgoing line according to priority. It is also possible to multiplex cells having higher priority first based on a code indicating priority added to the header portion of the cell other than the address. Also, in the readout right grant circuit 18, the outgoing line corresponding addresses FIFO 17a to 1
An example is shown in which two consecutive readings are performed when more than four are stored in 7d. However, other values may be used. Any other method may be used.

Further, when a restriction on the operation speed is required, a serial / parallel conversion circuit and a parallel / serial conversion circuit may be provided at the front and rear stages of the switch to process as a parallel signal.

〔The invention's effect〕

As described above, according to the present invention, the cell switching device
After the input cells are multiplexed by the input-stage cell exchange switch module, the cells are distributed, and the output-stage cell exchange switch module stores the cell string input from the previous stage in the storage circuit, and the storage control circuit increases the number of cells in the storage circuit. For a destination having a cell of N, a rule of reading more cells than a destination having a small number of cells, or for a destination having a cell storage amount of a certain value or more, N (N is an integer of 2 or more) Cells are continuously read, and n cells (n is 1) for other destinations
Or 0) cells are read out or N (N is an integer of 2 or more) cells are read continuously for a destination having the largest cell storage amount, and n cells are read for other destinations. (N is 1 or 0) For a destination having a large number of cells to be read, cells are read according to the rule of reading more cells than a destination having a small number of cells. Even if the cells are concentrated in the same period, if the capacity is within the capacity of the storage circuit of the output stage, there is an effect that the cells are not discarded. That is, in the storage control circuit, cells are managed for each destination by the outgoing line correspondence address. Therefore, even if cells are concentrated on one output port and accumulated in the buffer memory,
You can read cells addressed to other output ports,
Congested output ports do not affect output ports that are not. Further, since the control is performed to read more cells to the congested output port, the cells of the output port where the cells are concentrated are controlled so as to decrease faster, and only the concentrated cells are buffered. It prevents memory from being occupied. As a result, it is possible to obtain a cell switching device that does not affect other output ports even if cells are concentrated on one output port.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a cell switching apparatus according to an embodiment of the present invention, FIG. 2 is an enlarged block diagram of an output-stage cell switching switch module in FIG. 1, and FIG. 3 is an input-stage cell switching in FIG. FIG. 4 is a timing chart showing signal timings of respective parts of the switch module, FIG. 4 is a timing chart showing signal timings of respective parts of the intermediate-stage output stage cell exchange switch module in FIG. 2, and FIG. 5 is a concept showing a conventional cell exchange apparatus. FIG. 2 is an input port, 3 is a cell switching device, 5 is an output port,
7 is an input stage cell multiplexing circuit, 8a to 8h are input stage cell selection circuits, 9a to 9h are header processing circuits, 10a to 10h are storage circuits, 11
Is a memory control circuit, 12 is an output stage cell multiplexing circuit, 13a to 13h
Is an output stage cell selection circuit, 14a to 14h are speed conversion circuits, 16 is an address exchange circuit, 17a to 17d are outgoing line corresponding address FIFOs,
18 is a read right grant circuit, 19a to 19h are empty address management circuits, 60 to 63 are input stage cell exchange switch modules, 70
73 to 73 are output stage cell exchange switch modules, and 80 to 83 are cell output stage modules. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shigeru Aoyama 5-1-1, Ofuna, Kamakura-shi, Kanagawa Prefecture, Communication Systems Laboratory, Mitsubishi Electric Corporation (56) References JP-A-63-294036 (JP, A) JP-A-2-284542 (JP, A) Proceedings of the 1989 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, B-192

Claims (4)

(57) [Claims] 1. An input stage cell multiplexing circuit for classifying a plurality of input ports for inputting cells into a plurality of input port groups and time-division multiplexing input cells for each of the input port groups, and an input stage An input-stage cell switching switch having an input-stage cell selection circuit for selecting and passing cells directed to a specific output port group among a plurality of output ports into a plurality of output port groups from output signals of a cell multiplexing circuit A module and a storage circuit for storing cells output from the input stage cell selection circuit or the preceding output stage cell selection circuit and directed to a specific output port group, and the number of cells stored in this storage circuit is managed for each destination. For a destination having many cells, the storage circuit reads out more cells than a destination having fewer cells. A storage control circuit to be output, an output stage cell multiplexing circuit for multiplexing cells output by the storage circuit, and a specific output port group or a specific output port from an output signal of the output stage cell multiplexing circuit. An output-stage cell exchange switch module having an output-stage cell selection circuit for selecting and passing cells; and an output-stage cell exchange switch module connected to the last-stage output-stage cell exchange switch module and controlling the speed of the time-division multiplexed cell to the output port A cell exchange device comprising: a cell output stage module having a speed conversion circuit for converting speed. 2. An input stage cell multiplexing circuit for classifying a plurality of input ports for inputting cells into a plurality of input port groups and time-division multiplexing input cells for each of the input port groups, and an input stage. An input-stage cell switching switch having an input-stage cell selection circuit for selecting and passing cells directed to a specific output port group among a plurality of output ports into a plurality of output port groups from output signals of a cell multiplexing circuit A module and a storage circuit for storing cells output from the input stage cell selection circuit or the preceding output stage cell selection circuit and directed to a specific output port group, and the number of cells stored in this storage circuit is managed for each destination. Then, for a destination having a cell storage amount equal to or more than a certain value, N (N is an integer of 2 or more) cells are continuously read out, and the other destinations are read. A storage control circuit for outputting from the storage circuit according to the rule of reading n (n is 1 or 0) cells, an output stage cell multiplexing circuit for multiplexing the cells output by the storage circuit, and this output stage An output stage cell exchange switch module having an output stage cell selection circuit for selecting and passing a cell directed to the specific output port group or the specific output port from the output signal of the cell multiplexing circuit, and the final output stage A cell output stage module connected to the cell exchange switch module and having a speed conversion circuit for converting the speed of the time-division multiplexed cell into the speed of the output port. 3. An input stage cell multiplexing circuit for classifying a plurality of input ports for inputting cells into a plurality of input port groups and time-division multiplexing input cells for each of the input port groups, and an input stage. An input-stage cell switching switch having an input-stage cell selection circuit for selecting and passing cells directed to a specific output port group among a plurality of output ports into a plurality of output port groups from output signals of a cell multiplexing circuit A module and a storage circuit for storing cells output from the input stage cell selection circuit or the preceding output stage cell selection circuit and directed to a specific output port group, and the number of cells stored in this storage circuit is managed for each destination. However, for the destination with the largest cell storage amount, N
Cells (N is an integer of 2 or more) are read continuously, and n (n is 1 or 0) cells are read out for other destinations. For a destination having many cells, cells are read out. Storage control circuit for outputting from the storage circuit according to the rule of reading more cells than destinations with less output, an output stage cell multiplexer for multiplexing the cells output by the storage circuit, and an output stage cell multiplexer. An output-stage cell exchange switch module having an output-stage cell selection circuit for selecting and passing a cell directed to a specific output port group or the specific output port from an output signal, and a final-stage output-stage cell exchange switch module. A cell output stage module having a speed conversion circuit for converting the speed of the time-division multiplexed cell to the speed of the output port. Exchange equipment. 4. The method according to claim 1, wherein reading is stopped for an outgoing line having a small number of cells as destinations, and control is performed to avoid a system in which a delay time increases to a certain value or more. The cell switching device according to any one of the above.