JP2701780B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit including a high-speed input buffer using a voltage comparison circuit.

[0002]

2. Description of the Related Art FIGS. 3A and 3B are circuit diagrams of a conventional input buffer in a semiconductor integrated circuit of this kind. The input buffer included in the conventional example shown in FIG. 3A includes a voltage comparison circuit 9 and a reference voltage source 10 corresponding to a reference voltage terminal 57, an input terminal 58, and an output terminal 59.
When the potential of the input signal input from the input terminal 58 is higher than the potential of the reference voltage input from the reference voltage terminal 57, the output terminal 59 outputs an “H” level signal. When the potential of the input signal output and input from the input terminal 58 is lower than the potential of the reference voltage input from the reference voltage terminal 57, an “L” level signal is output from the output terminal 59. Then, each is input to an internal circuit (not shown) included in the semiconductor integrated circuit. In this case, as the speed of the semiconductor integrated circuit increases, the speed of the input buffer is also required to be higher. With the increase in the speed, the voltage level of the input signal to the input buffer is suppressed to a low level. .

In order to process this low-level, small-amplitude input signal, the input buffer is provided with a voltage comparison circuit using a differential input circuit, as shown in FIG. The voltage comparison circuit 9 includes a constant current source 13, PMOS transistors 14, 15 and an NMOS transistor 1 corresponding to a reference voltage terminal 57, an input terminal 58, an output terminal 59, a power supply terminal 60, and a ground terminal 61.
6, a differential input circuit including a constant current source 18, an NMO
An output circuit including an S transistor 20 and a buffer 19 is provided. In FIG. 4A, a constant current source 13 is connected in series to the differential input circuit.
During operation, a constant current corresponding to the constant current source 13 always flows.

An input buffer according to another conventional example shown in FIG. 3B includes a reference voltage terminal 62 and an input terminal 6.
3. A voltage comparison circuit 11 and a reference voltage source 12 are provided corresponding to the power save terminal 64 and the output terminal 65. The power save terminal 64 is connected to the voltage comparison circuit 11. In the normal operation state, as in the case of the input buffer in the above-described conventional example, when the potential of the input signal input from the input terminal 63 is higher than the potential of the reference voltage input from the reference voltage terminal 62, When an "H" level signal is output from the output terminal 65 and the potential of the input signal input from the input terminal 63 is lower than the potential of the reference voltage input from the reference voltage terminal 62, An “L” level signal is output from the output terminal 65 and input to the internal circuit of the semiconductor integrated circuit. In this conventional example, for the purpose of suppressing current consumption, the current by the constant current source in the voltage comparison circuit 11 is cut off by the control signal input from the power save terminal 64 when the operation is not performed. The circuit is configured.

In this prior art, the voltage level of the input signal to the input buffer is suppressed to a low level as the speed of the input buffer is increased. As an input buffer, as shown in FIG.
The voltage comparison circuit 11 is configured as a voltage comparison circuit using a differential input circuit including a reference voltage terminal 62, an input terminal 63, a power save terminal 64, an output terminal 65, a power supply terminal 66, and a ground terminal. 67, constant current source 21, PMOS transistors 22 to 24 and N
A differential input circuit including MOS transistors 25 and 26;
An output circuit including a constant current source 27, a PMOS transistor 28, an NMOS transistor 29, and a buffer 30 is provided. As shown in FIG. 4B, the differential input circuit and the output circuit respectively include PMOS transistors 22 and 28 each having a function of interrupting a current path.
And its on / off is controlled by a control signal input from a power save terminal 64.
This makes it possible to temporarily stop the steady-state current in these differential input circuits and output circuits. However, when the steady current is stopped, the function as the input buffer is also stopped.

[0006]

In general, in a large-scale semiconductor integrated circuit having a circuit scale of several million gates with a dramatic improvement in the degree of integration of the semiconductor integrated circuit, An extremely large test pattern is required to detect the failure of the test. For example, it is said that when the number of gates becomes n times larger, the test pattern needs to be n ₂ times larger.

Among them, in the case of a CMOS type semiconductor integrated circuit, almost no power supply current statically flows into the semiconductor integrated circuit unless a current is intentionally supplied by a constant current source or the like. Generally, the static current at that time is about several μA. However, when a defect occurs in the semiconductor integrated circuit due to a manufacturing defect, a current flows into the semiconductor integrated circuit. Therefore, by measuring the static current in the semiconductor integrated circuit, it is possible to find a manufacturing defect of the semiconductor integrated circuit. that time,
Using a large test pattern as described above by changing the form of the input signal to the semiconductor integrated circuit in various ways, thereby creating different internal operating states in the semiconductor integrated circuit and measuring the static current several times Without this, it is possible to detect a defect in the semiconductor integrated circuit.

[0008] In order to deal with the situation of detecting a defect in such a semiconductor integrated circuit, in a semiconductor integrated circuit including a high-speed input buffer using the above-described conventional voltage comparison circuit, a constant current is included in the voltage comparison circuit of the input buffer. A source is provided, and a current constantly flows during operation, and the current value is about several mA. By measuring the static current of the conventional semiconductor integrated circuit including this input buffer,
When performing a test for detecting a malfunction of the semiconductor integrated circuit, it is necessary to relax the standard of the current by the steady current by the constant current source. That is, at the time of measuring the static current, the current standard, which should be about several μA, must be about several mA as described above, and there is a disadvantage that a minute defect cannot be detected.

Further, in the case of a semiconductor integrated circuit including an input buffer using a voltage comparison circuit capable of stopping a steady current by providing a power save terminal, the control signal input to the power save terminal causes Although it is possible to prevent the steady current flowing through the voltage comparison circuit from flowing,
In this case, the voltage comparison circuit is in a non-operational state, and it is not possible to measure the static current by changing the form of the input signal to create a different internal operation state in the internal circuit in the semiconductor integrated circuit. This makes it possible to detect a defect in the semiconductor integrated circuit.

[0010]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention has an operation function of comparing a voltage of an external input signal with a predetermined reference voltage and outputting an "H" level or "L" level signal. A voltage comparison circuit whose operation function is controlled on / off by a predetermined test control signal, an auxiliary input buffer functioning as an input buffer for the external input signal, and a level of the test control signal. And an output signal of the voltage comparison circuit, and the output signal of the inverter controls the on / off of the operation function. A first three-state buffer that functions to output to an internal circuit; and an output signal of the auxiliary input buffer. And a second three-state buffer functioning to output the input output signal to the internal circuit when the operation function is turned on. , As input circuit means.

The auxiliary input buffer includes a PMOS transistor having a source connected to the power supply side, a gate connected to the input side, and a drain connected to the output side; a drain connected to the output side; May be configured as a CMOS level input buffer including an NMOS transistor connected to the input side and having a source connected to the low potential side.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an input buffer included in an embodiment of the present invention. As shown in FIG. 1, the input buffer according to the present embodiment includes a voltage comparison circuit 1 and a CMOS level input buffer 2 corresponding to a reference voltage terminal 51, an input terminal 52, a test control terminal 53, and an output terminal 54. , 3-state buffers 3 and 5
, An inverter 4 and a reference voltage source 6. The voltage comparison circuit 1 of the input buffer according to the present embodiment is configured in the same manner as the voltage comparison circuit shown in FIG. FIG. 2 is a circuit diagram showing an example of the internal configuration of the CMOS level input buffer 2.
5 and an output terminal 56, and are constituted by a PMOS transistor 7 and an NMOS transistor 8.

In FIG. 1, when the control signal input from the test control terminal 53 is input at the “L” level, the constant current source included in the voltage comparison circuit 1 is activated, and the input from the input terminal 52 is input. The potential of the input signal is compared with the potential of the reference voltage applied from the reference power supply 6 input from the reference voltage terminal 51. When the potential of the input signal input from the input terminal 52 is higher than the potential of the reference voltage input from the reference voltage terminal 51, the voltage comparison circuit 1 outputs an "H" level signal. When the potential of the input signal input from the input terminal 52 is lower than the potential of the reference voltage input from the reference voltage terminal 51, an “L” level signal is output from the voltage comparison circuit 1, Input to the three-state buffer 3. 3
The state buffer 3 is turned on because the “L” level control signal input from the test control terminal 53 is inverted by the inverter 4 and input as an “H” level control signal. Therefore, the voltage comparison circuit 1
The output signal of “H” level or “L” level is output to the output terminal 54 via the three-state buffer 3 and is input to an internal circuit (not shown) of the semiconductor integrated circuit. The input signal is also input to the CMOS level input buffer 2, and is input to the three-state buffer 5 via the CMOS level input buffer 2. However, the control terminal of the three-state buffer 5 receives an “L” level control signal input to the test control terminal 53, and the three-state buffer 5 is in an off state. No signal is output to the output terminal 54.

When a "H" level control signal is input to the test control terminal 53, the current from the constant current source is turned off in the voltage comparison circuit 1, and the three-state buffer 3 is also turned off. . Therefore, in this case, the potential of the input signal input from the input terminal 52 is not compared with the potential of the reference voltage applied from the reference power supply 6 input from the reference voltage terminal 51, and the three-state buffer 3 No signal is output. On the other hand, the 3-state buffer 5 is turned on, and the input signal input from the input terminal 52 is applied to the CMOS level input buffers 2 and 3.
The signal is output to the output terminal 54 via the state buffer 5 and is input to an internal circuit (not shown) of the semiconductor integrated circuit.

In the normal operation of the input buffer according to the present embodiment, the control signal input to the test control terminal 53 is set at the "L" level, and the input buffer including the voltage comparison circuit 1 has a small amplitude. It is set to function as a high-speed input buffer corresponding to an input signal. Also,
In testing the input buffer in this embodiment,
The control signal input to the test control terminal 53 is set to “H” level, the current flowing through the voltage comparison circuit 1 is cut off, and the CMOS level input buffer 2 functions as an input buffer. Moreover, the CMOS level input buffer 2 is configured as shown in FIG. 2, and has a circuit configuration in which the static current does not flow. Therefore, when the static current is measured by changing the internal state of the semiconductor integrated circuit in order to detect a defect of the semiconductor integrated circuit, the test control signal is set to “H” level and the voltage of the input buffer is compared. The input buffer itself can be operated as an input buffer by the CMOS level input buffer 2 while the current of the circuit is reduced to zero. Through this CMOS level input buffer 2, measurement of a failure detection inside the semiconductor integrated circuit is performed. be able to.
Thus, when measuring the static current, the current of the voltage comparison circuit 1 is set to zero, and the extra current during the normal operation of the input buffer is eliminated through the CMOS level input buffer 2 through which the static current does not flow. Thus, more accurate current measurement can be performed.

Although the input signal level is different between the normal operation and the static current measurement of the present embodiment, the semiconductor inspection apparatus used for testing the semiconductor integrated circuit is free to use any signal level. Since the signal level for the test can be set, there is no problem in the test based on the static current measurement described above.

[0018]

As described above, the present invention is applied to a semiconductor integrated circuit including an input buffer using a voltage comparison circuit, and when detecting a defect inside the semiconductor integrated circuit, an extra current flowing through the input buffer is detected. Eliminating the current has the effect of improving the static current measurement accuracy for detecting the failure.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an input buffer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a CMOS level input buffer in the present embodiment.

FIG. 3 is a block diagram showing a configuration of an input buffer in a conventional example.

FIG. 4 is a circuit diagram illustrating a configuration of a voltage comparison circuit example.

[Explanation of symbols]

1, 9, 11 Voltage comparison circuit 2 CMOS level input buffer 3, 5, 3-state buffer 4 Inverter 6, 10, 12 Reference voltage source 7 PMOS transistor 8 NMOS transistor 13, 18, 21, 27 Constant current source 14, 15, 22 ~ 24,28 PMOS transistor 16,17,20,25,26,29 NMOS transistor

Claims (2)

(57) [Claims] An operation function of comparing a voltage of an external input signal with a predetermined reference voltage and outputting an "H" level or an "L" level signal, and operating by a predetermined test control signal A voltage comparison circuit that controls the on / off of the voltage control circuit; an auxiliary input buffer that functions as an input buffer for the external input signal; an inverter that inverts and outputs the level of the test control signal; and an output of the voltage comparison circuit. A signal is input, and on / off of an operation function is controlled by an output signal of the inverter,
A first three-state buffer functioning to output the input output signal to a predetermined internal circuit when the operation function is turned on; an output signal of the auxiliary input buffer being input and operating by the test control signal A second three-state buffer that controls on / off of a function and outputs the input output signal to the internal circuit when the operation function is on. A semiconductor integrated circuit comprising a buffer as input circuit means. 2. A PMOS transistor having a source connected to the power supply side, a gate connected to the input side, and a drain connected to the output side; a drain connected to the output side; 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured as a CMOS level input buffer including: an NMOS transistor connected to the input side and a source connected to the low potential side.