JP2799042B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a semiconductor memory device capable of high-speed serial access by applying a nibble mode.

(Prior Art) Among MOS semiconductor memories, a dynamic RAM (DRAM) having one transistor and one capacitor has been most highly integrated. Recent DRAMs are equipped with a high-speed access mode such as a page mode, a nibble mode, and a static column mode, in addition to a normal access mode. On the other hand, there is also a strong demand from the field of image processing or the field of computer systems using a cache memory for serial access that can access one row of data at high speed and serially.

The conventional page mode is a mode in which a selected row of data can be accessed randomly and at high speed. By using this page mode and serially giving an address from the outside, serial access can be performed in which one line of data is accessed serially at high speed. However, in serial access using this page mode, the column address must be fetched from the outside each time in response to the toggle of ▲ ▼, so there is a limit in speed.

On the other hand, nibble and
There is a mode. FIGS. 7 and 8 show timing charts of the read cycle and the write cycle in the nibble mode, respectively. The nibble mode is similar to the page mode described above in that high-speed access of consecutive bits in the column direction is performed only by the toggle of ▼. However, in nibble mode, ▲
From the second cycle onward, the fetch of the column address is not required. In this regard, nibble mode is generally faster than page mode, which is a major advantage.

However, the nibble mode has the greatest difficulty in that the number of bits that can be accessed is limited, and cannot be applied to serial access. The number of bits that can be accessed is limited for the following reasons. In the nibble mode, a plurality of data are collectively sent to the data latch register in the first cycle of ▲, and from there, ▲
High-speed access is realized by sequentially transferring data to the output port by the toggle of ▼. Therefore, the number of data latch registers is limited to the number of bits that can be accessed. Number of registers and 1
If the number of rows of data is the same, one row of data can be accessed serially at high speed, but 4-bit nibbles are now common, mainly due to chip area constraints.

Next, the problem when the nibble mode is applied to the serial access mode will be specifically described with reference to FIG. FIG. 9 is a timing chart at the time of reading when serial access is performed using the nibble mode.
In the figure, CSLi (i = 0, 1,...) Represents a column selection line which is determined and activated by a column address, and QSE is a sense of a data latch register which is an intermediate buffer connected to an input / output data line. Represents a signal. In the nibble mode, a plurality of data are transferred to a data latch register by selecting one column selection line, and a sensing operation is performed here. The bit length is the same as the number of bit line pairs accessible in the nibble mode. In the case of the figure,
This indicates that 4-bit data is transferred by one column selection line CSL. Therefore, assuming that a column address counter is built in the on-chip and serial access is realized by sequentially increasing the internal address, as shown in FIG. 9, 4n + 1 (n = 1, 2,...) ▲ ▼
It is necessary to switch the column selection line in the cycle and to activate the sense signal QSE in the data latch register. Therefore, the access time in the (4n + 1) th cycle is longer than that in the other cycles as shown in FIG. Generally, the extended access time is about twice that of other cycles. This is a major obstacle in achieving uninterrupted high-speed serial access.

(Problems to be Solved by the Invention) As described above, in the conventional DRAM, if the serial access mode for serially accessing one row of data at a high speed is to be realized by the application of the nibble mode, the column address is increased. There is a problem that a waste occurs at the time of switching between the devices and that continuous high-speed serial access cannot be performed.

The present invention solves such a problem and provides a high-speed serial
It is an object of the present invention to provide a semiconductor memory device that enables access.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device according to the present invention comprises: a memory cell array in which a plurality of memory cells are arranged; an address buffer for receiving an external address; A row decoder for selecting a row of the memory cell array according to the input row address; a first column selection line corresponding to the column address based on a column address fetched by the address buffer; The column next to the column address
By selecting the second column selection line corresponding to the address and raising the selected column selection line, the second column selection line is activated before the arrival of the next column address of the column address. And a sense amplifier for exchanging data with a memory cell selected by the row decoder and the column decoder.

(Operation) According to the present invention, when a column selection line determined by a column address rises, the column selection line to be selected by the next column address is changed to the column selection line.
It is started up before the arrival of the address. In other words, in the present invention, the column decoder has a look ahead function. Then, the data to be selected by the next address is already transferred to the data register by the previously selected column selection line before the arrival of the address. This eliminates the time loss at the time of column address switching as in the case of arrival, and realizes uninterrupted high-speed serial access.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 shows a configuration of a column decoder in a VRAM of one embodiment. FIG. 2 is a block diagram showing the entire configuration of the DRAM, and FIG. 3 is a diagram showing a specific configuration from the memory cell array to the data output unit.

As shown in FIG. 2, the DRAM of this embodiment comprises a row address buffer 1, a column address buffer 2 for taking in an external address, clock generators 3 and 4 for driving these address buffers 1 and 2, A column decoder 5 and a row decoder 6 for decoding the fetched address, a memory cell array 7 in which a 1-transistor / 1-capacitor dynamic memory cell driven by these decoder outputs is arranged, and data exchange with the memory cell array 7 is performed. Amplifier and input / output (I / O)
It has a gate 8, an input buffer 9 for latching input / output data, an output buffer 10, a substrate bias generation circuit 11, and a refresh counter 12 for self-refreshing the memory cell array. These main components are not different from the conventional DRAM. In this embodiment, in addition to these, a serial address which generates a serial address in the column direction is used.
The counter 13 is built in. This serial address
The counter 13 is configured to count up in response to the toggle of ▲, and its output is input to the column address buffer 2. The output of serial address counter 13 is
The data may be directly input to the output unit, that is, the input unit of the column decoder 5 instead of the input unit of the address buffer 2.

As is well known, the memory cell array 7 includes a plurality of word lines and bit line pairs intersecting each other, and a memory cell is arranged at the intersection. In FIG. 3, one word line WL of such a memory cell array 7 and a memory cell MC arranged along the word line WL, and a plurality of bit line pairs BL and BL for exchanging data with these memory cells MC are shown.
▲ ▼ is shown. Further, in this embodiment, as shown in FIG. 3, four pairs of DQ0, ▲ ▼ to DQ3, ▲ ▼
An I / O data line 21 is provided. I / O data line 21
Each I / O corresponds to the output buffer 10 in FIG.
Data latch registers 22 (221 to 224) provided corresponding to the O data lines 21;
And a data output buffer 24 connected to an external output terminal. Each of the column selection lines CSL selected by the column decoder 5 is branched into two, and the I / O gates 8 corresponding to two pairs of adjacent bit lines are simultaneously driven. That is, the two bit line pairs selected by one column selection line CSLn-1 are the first and second I / O data line pairs DQ0, ▲ ▼ and DQ1, ▲, respectively.
And the next two bit line pairs selected by the next column selection line CSLn are the third and fourth I / O data line pairs DQ2, ▲ ▼ and DQ3, ▲, respectively.
▼ is to be connected.

The column decoder 5 has a look-ahead function of simultaneously selecting not only the column selection line determined by the address of the own cycle but also the column selection line selected by the next address. Figure 1 shows such a column.
3 is a configuration example of a decoder 5. This column decoder 5
Is a plurality of NAND gates G1 (G11, G12, G13,...) For decoding the same column address as in a normal decoder.
, A plurality of two-input NAND circuits provided at the output unit of the address decoding unit 41.
There is a column selection line driving section 52 composed of gates G2 (G21, G22, G23,...). Each NAND gate G2 of the column selection line drive unit 51
Is connected to the output terminal of the NAND gate G1 corresponding to each of the address decoding unit 51 to one of the two input terminals,
An output terminal of the address decoding unit 51 corresponding to the immediately preceding column address is branched and connected to the other input terminal. In FIG. 1, a signal line LA indicated by a thick line is a so-called look-ahead signal line.

Next, the operation of serial access by the DRAM configured as described above will be described.

Prior to the operation of the entire DRAM, the operation of the column decoder 5 in FIG. 1 will be described as follows. address·
In the decoding unit 51, the output terminal of one of the NAND gates becomes “L” level in order to select one column selection line according to the input column address. Now, for example, it is assumed that the output terminal of the NAND gate G11 has become “L” level. Then, the “L” level of this output is input to one input terminal of the corresponding NAND gate G21 of the column selection line driving unit 52, and at the same time, is input to one input terminal of the next NAND gate G22 through the look ahead signal line LA. enter. As a result, the output terminals of the two NAND gates G21 and G22 become "H" level, and the column selection line CSLn-1 corresponding to the input column address and the column selection line corresponding to the next column address simultaneously. CSLn will be selected. When the next column address is input, the address decoder 51
Then, the output of the NAND gate G11 returns to “H” level, and the next NAN
The output terminal of the D gate G12 becomes “L” level. As a result, in the column selection line driving section 52, the output of the NAND gate G21, that is, the column selection line CSLn-1 returns to "L" level. At this time, in the NAND gate G22 corresponding to the selected address, one input returns to the “H” level and the other input goes to the “L” level, so that its output, that is, the column selection line CSLn is at the “H” level. Will be kept. Also, at this time, one input terminal of the next NAND gate G23 becomes “L” level through the look ahead signal line LA, whereby the column selection line CSLn + 1 to be selected by the next column address becomes “H”. "Become a level. In the same manner, the column selection lines are started in advance before their own column addresses arrive, and the selection that the two column selection lines always go to the “H” level is sequentially performed.

FIG. 4 is an operation timing chart of a read cycle in the serial access mode by the DRAM of this embodiment. Row address strobe signal ▲ ▼ is “L”
Level, and enters an active cycle to take in row address. In the first cycle of the column address strobe signal ▼ (the first toggle in ▼), the column selection line CSL0 determined by the column address and the column determined by the column address one bit ahead of that address. Two selection lines CSL1 rise at the same time. As a result, 4-bit data is read out and transferred to the data latch register 22 via the I / O data line 21. Then, at the rising edge A1 of the sense activation signal QSE, the transferred 4-bit data is latched. This 4-bit data is referred to as ▲ ▼
Are sequentially transferred to the output terminal via the multiplexer 23 and output to the outside. At the end of the second cycle of ▲ ▼, the serial address counter 13
Increments the column address. At this time, the internal column address should be in a state of selecting the column selection line CSL1, but inside the chip, the column selection line CSL1 has already been selected by the look-up function of the column decoder 5 described above. Been “H”
Level. Then, at the same time that the next column selection line CSL2 is selected, the first column selection line CSL0 is not selected. As a result, new 2-bit data is read out to the I / O line 21 and transferred to the data latch register 22.
This data is sensed and latched at the second rising edge A2 of the sense activation signal QSE.

Similarly, the nibble mode is applied in a state where a column selection line is newly selected every two cycles of ▲ ▼ according to the increment of the internal column address and two column selection lines are always selected. Data reading in the serial access mode is performed. According to this embodiment, there is no longer an extended access during column address switching as in the prior art, and continuous serial access is possible. Note that the column selection line has been selected in advance, but remains selected until the end of its own cycle. Therefore, although detailed description is omitted, this method can be similarly used in the read / write cycle mode.

By the way, an image-only memory having a pointer function has been developed. The pointer function is a so-called cueing function that enables serial access from an arbitrary address to a column address. Such a function is extremely useful in facilitating horizontal todd scrolling in an image memory, for example. Therefore, by adding this function to a general-purpose DRAM capable of serial access mode, high value-added DRAM
Can be obtained.

FIG. 5 shows the configuration of the column decoder of the DRAM according to the embodiment to which such a pointer function is added, corresponding to FIG. The difference from FIG. 1 is that the output line of the address decode unit for the column selection line CSL2n (（)
, Look-ahead signal line for column select line CSL0
It is used as LA.

As a result, as shown by the arrow in FIG. 5, the column selection line CSL0 is selected after the column selection line CSL2n, and as a result, the pointer function is obtained.

In the configuration of FIG. 5, the selection of the column selection line moves sequentially from the top to the bottom of the drawing. Therefore, the look ahead signal line for the uppermost column selection line CSL0 is extremely longer than the other look ahead signal lines. This causes the look-ahead operation of the column selection line CSL0 to be extremely delayed due to wiring delay. This may lead to a reduction in the operating margin.

FIG. 6 shows a column decoder of an embodiment in which the configuration of FIG. 5 is modified in consideration of such a problem. In this embodiment, the physical order of access of the column selection lines is changed as indicated by the arrow in the figure. That is, as the look ahead signal line, a downward LA1 and an upward LA2 are prepared, and these are arranged alternately. In other words, the column selection lines are CSL0, CSL2n, CSL1, CSL2
An array of n−1, CSL2,... In other words, the column selection line corresponding to the one-bit increment from the physical lowest address and the column selection line corresponding to the one-bit decrement from the highest address are alternately and arranged in a line. .

With such a configuration, the lengths of all the look-ahead signal lines are equal, and it is possible to prevent a decrease in the operation margin due to the above-described wiring delay.

The present invention is not limited to the above embodiment. For example, in the embodiment, the column decoder has the simplest NAND gate configuration. However, for example, a column decoder having a similar function can be configured by using a NOR gate. In the embodiment, the general-purpose DRAM has been described, but not only an image-only memory using dynamic memory cells but also a serial
The present invention can be similarly applied to a static RAM having an access mode.

[Effects of the Invention] As described above, according to the present invention, a semiconductor memory that enables continuous high-speed serial access in a conventional nibble mode using a column decoder adopting a look-ahead method. The device can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a column decoder in a DRAM according to an embodiment of the present invention, FIG. 2 is a block diagram showing an entire configuration of the DRAM, and FIG. 3 is a configuration of a data input / output unit of the DRAM. FIG. 4 is a timing chart for explaining the operation of the DRAM, FIG. 5 is a diagram showing the configuration of a column decoder of another embodiment, and FIG. 6 is a column of still another embodiment. FIG. 7 is a diagram showing the structure of a decoder, FIG. 7 is an operation timing diagram of a read cycle in a conventional DRAM nibble mode, FIG. 8 is an operation timing diagram of a write cycle in the same manner, and FIG. FIG. 9 is a timing chart for explaining a problem of a serial access operation applied to a mode. 1... Row address buffer, 2... Column address buffer, 3... ▲ ▼ system clock generator, 4.
5 ... column decoder, 6 ... row decoder, 7 ...
... memory cell array, 8 ... sense amplifier and I / O gate, 9 ... input buffer, 10 ... output buffer, 11 ...
... Substrate bias circuit, 12 ... Refresh counter,
13: Serial counter, 51: Address decode unit, 52: Column select line drive unit, 21: I / O data line, 2
2 Data latch register, 23 Multiplexer, 34 Data output buffer.

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/407

Claims (5)

(57) [Claims] A memory cell array in which a plurality of memory cells are arranged; an address buffer for receiving an external address; and a row decoder for selecting a row of the memory cell array based on a row address fetched by the address buffer. A first column selection line corresponding to the column address based on the column address fetched by the address buffer, and a second column selection line corresponding to a column address next to the column address And by raising the selected column selection line, the column decoder which raises the second column selection line before the arrival of the next column address of the column address, and A cell for exchanging data with the memory cell selected by the decoder and the column decoder A semiconductor memory device comprising: a sense amplifier. 2. A memory cell array having a plurality of pairs of word lines and bit lines arranged crossing each other, and a dynamic memory cell disposed at each crossing position thereof, and A plurality of sense amplifiers and input / output gates respectively provided; a plurality of pairs of input / output data lines selectively connected to the bit line pair via the sense amplifiers and the input / output gates; A plurality of data latch registers provided for each of the lines, an address buffer for taking in an external address, a row decoder for selecting a row of the memory cell array based on a row address taken in by the address buffer, A column address corresponding to the column address is taken based on the column address fetched by the address buffer. By selecting a first column selection line and a second column selection line corresponding to a column address next to the column address, and raising the selected column selection line, the second column selection line is set. A column decoder that starts up before the arrival of the next column address of the column address. 3. A memory cell array having a plurality of pairs of word lines and bit lines arranged crossing each other, and a dynamic memory cell arranged at each crossing position between the word lines and bit lines. A plurality of sense amplifiers and input / output gates respectively provided; a plurality of pairs of input / output data lines selectively connected to the bit line pair via the sense amplifiers and the input / output gates; A plurality of data latch registers provided for each line, an address buffer for taking in an external address, and an internal column address which is counted up by a column address strobe signal and sequentially generates an internal column address for serial access The address counter and the row address captured by the address buffer A row decoder for selecting a row of the memory cell array, a first column selection line corresponding to the column address based on the column address fetched by the address buffer, and a column next to the column address Selecting a second column selection line corresponding to the address and raising the selected column selection line, thereby setting the second column selection line before the arrival of the next column address of the column address; And a column decoder that starts up. 4. The address decoder according to claim 1, wherein the column decoder has an output terminal corresponding to a column selection line to be selected corresponding to a column address, and one of the output terminals of the address decoder is connected to one of the output terminals. The other input terminal is connected to the output terminal of the address decoding unit corresponding to the column address immediately before the corresponding column address, and the output terminal is connected to a column selection line. Multiple connected 2-input NA
4. The semiconductor memory device according to claim 1, further comprising: a column selection line driving unit including an ND gate. 5. An array of column select lines includes a column select line corresponding to one bit increment from a physical lowest address and a column select line corresponding to one bit decrement from a highest address. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device has a form in which said memory cells are arranged alternately and in a line.